FreeCalypso > hg > fc-small-hw
view mmtb1/schem+bom/vsrc/board.v @ 12:ee17927ee326
lunalcd1/pcb/Makefile added
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 03 Apr 2020 00:02:03 +0000 |
parents | 0f9bdd60ce50 |
children |
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/* * This is the top level structural Verilog module for the MMTB1 board. */ module board (); wire GND, VBAT, Vio; wire PWON, nTESTRESET; wire TX_IRDA, RX_IRDA; wire TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM; wire GPIO2_DCD, GPIO3_DTR; wire VSIM, SIM_CLK, SIM_RST, SIM_IO; wire EARP, EARN, MICP, MICN; /* power input to the rig */ conn_3pin pwr_input_conn (.pin_1(VBAT), .pin_2(), .pin_3(GND) ); capacitor big_cap (VBAT, GND); /* DUT interface connector */ interface dut_if (.GND(GND), .VBAT(VBAT), .PWON(PWON), .nTESTRESET(nTESTRESET), .Vio(Vio), .TX_IRDA(TX_IRDA), .RX_IRDA(RX_IRDA), .TX_MODEM(TX_MODEM), .RX_MODEM(RX_MODEM), .RTS_MODEM(RTS_MODEM), .CTS_MODEM(CTS_MODEM), .GPIO2_DCD(GPIO2_DCD), .GPIO3_DTR(GPIO3_DTR), .VSIM(VSIM), .SIM_IO(SIM_IO), .SIM_CLK(SIM_CLK), .SIM_RST(SIM_RST), .EARP(EARP), .EARN(EARN), .MICP(MICP), .MICN(MICN) ); /* PWON and nTESTRESET pushbuttons */ pushbutton_wrap pwr_btn (PWON, GND); pushbutton_wrap reset_btn (nTESTRESET, GND); /* power on LED */ led_circuit led (.GND(GND), .VBAT(VBAT), .Signal(Vio) ); /* SIM socket */ sim_socket_block sim (.GND(GND), .VSIM(VSIM), .SIM_CLK(SIM_CLK), .SIM_RST(SIM_RST), .SIM_IO(SIM_IO) ); /* UART interfaces */ uart_bringout uart_if (.GND(GND), .TX_MODEM(TX_MODEM), .RX_MODEM(RX_MODEM), .RTS_MODEM(RTS_MODEM), .CTS_MODEM(CTS_MODEM), .GPIO_DCD(GPIO2_DCD), .GPIO_DTR(GPIO3_DTR), .TX_IRDA(TX_IRDA), .RX_IRDA(RX_IRDA) ); /* earpiece and microphone connectors */ header_2pin J5 (EARP, EARN); header_2pin J6 (MICP, MICN); endmodule