FreeCalypso > hg > fc-small-hw
view fc-uja/schem+bom/vsrc/USB_block.v @ 10:f8735d13a3ea
lunalcd1.pcb: layout started, close to complete
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 02 Apr 2020 22:41:19 +0000 |
parents | 0f9bdd60ce50 |
children |
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/* * This module encapsulates the USB connector, the FT2232D block and * the glue components between them. */ module USB_block (GND, P_5V, VCCIOA, VCCIOB, ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB, PWREN); output GND, P_5V; input VCCIOA, VCCIOB; inout [7:0] ADBUS, BDBUS; inout [3:0] ACBUS, BCBUS; input SI_WUA, SI_WUB; output PWREN; /* interconnecting wires */ wire VBUS; wire DM_connector_side, DM_chip_side; wire DP_connector_side, DP_chip_side; wire RSTOUT; usb_conn conn (.GND(GND), .VBUS(VBUS), .Dminus(DM_connector_side), .Dplus(DP_connector_side), .ID() /* no connect */ ); /* ferrite bead on the power supply */ inductor VBUS_ferrite (VBUS, P_5V); /* series resistors on USB data lines */ resistor DM_series_R (DM_connector_side, DM_chip_side); resistor DP_series_R (DP_connector_side, DP_chip_side); /* we can now bring in the FT2232D block */ FT2232D_block FT2232D (.GND(GND), .VCC(P_5V), .VCCIOA(VCCIOA), .VCCIOB(VCCIOB), .USBDP(DP_chip_side), .USBDM(DM_chip_side), .RESET(P_5V), .RSTOUT(RSTOUT), .PWREN(PWREN), .ADBUS(ADBUS), .ACBUS(ACBUS), .SI_WUA(SI_WUA), .BDBUS(BDBUS), .BCBUS(BCBUS), .SI_WUB(SI_WUB) ); resistor DP_pullup_R (DP_chip_side, RSTOUT); /* power bypass caps */ capacitor VBUS_in_cap (VBUS, GND); capacitor P_5V_cap (P_5V, GND); capacitor P_5V_cap2 (P_5V, GND); endmodule