FreeCalypso > hg > fc-small-hw
graph
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lunalcd3.pcb: manually add bottom strap to LCD footprintThu, 18 Nov 2021 06:11:27 +0000, by Mychaela Falconia
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lunalcd3 project startedThu, 18 Nov 2021 04:59:47 +0000, by Mychaela Falconia
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lunalcd2/src/Makefile: generate BOM outputsSat, 26 Jun 2021 21:16:48 +0000, by Mychaela Falconia
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lunalcd2/src/MCL: resistor parts nailed downSat, 26 Jun 2021 21:16:08 +0000, by Mychaela Falconia
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lunalcd2/src/MCL: different part for two-post VBAT supply headerSat, 26 Jun 2021 20:40:29 +0000, by Mychaela Falconia
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lunalcd2/pcb: add MakefileFri, 25 Jun 2021 23:08:00 +0000, by Mychaela Falconia
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lunalcd2.pcb: manual DRC fixesFri, 25 Jun 2021 22:59:37 +0000, by Mychaela Falconia
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lunalcd2.pcb complete except for DRCFri, 25 Jun 2021 22:52:20 +0000, by Mychaela Falconia
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lunalcd2.pcb almost completeFri, 25 Jun 2021 22:31:24 +0000, by Mychaela Falconia
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lunalcd2.pcb startedFri, 25 Jun 2021 20:29:36 +0000, by Mychaela Falconia
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lunalcd2/src/Makefile: generate elements.pcbFri, 25 Jun 2021 19:11:21 +0000, by Mychaela Falconia
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lunalcd2/src/Makefile: generate pcb-netlist.txtFri, 25 Jun 2021 19:08:13 +0000, by Mychaela Falconia
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lunalcd2: MCL binding completeFri, 25 Jun 2021 19:01:35 +0000, by Mychaela Falconia
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lunalcd2: structural Verilog source capturedFri, 25 Jun 2021 18:44:11 +0000, by Mychaela Falconia