FreeCalypso > hg > fc-small-hw
graph
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sim-fpc-pasv/pcb: add Makefile for Gerber output default tipWed, 02 Nov 2022 07:22:44 +0000, by Mychaela Falconia
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sim-fpc-pasv: PCB layout doneTue, 25 Oct 2022 07:31:52 +0000, by Mychaela Falconia
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sim-fpc-pasv: schem+BOM design completeTue, 25 Oct 2022 06:13:01 +0000, by Mychaela Falconia
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sim-fpc-pasv MCL: FPC connector footprintTue, 25 Oct 2022 05:13:55 +0000, by Mychaela Falconia
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sim-fpc-pasv: starting project with MCLTue, 25 Oct 2022 03:17:34 +0000, by Mychaela Falconia
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lunalcd3: add Makefile for Gerber output generationSat, 04 Dec 2021 22:28:05 +0000, by Mychaela Falconia
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lunalcd3.pcb: add orientation marker to U1Thu, 18 Nov 2021 07:44:45 +0000, by Mychaela Falconia
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lunalcd3.pcb: add orientation marker to SW1Thu, 18 Nov 2021 07:40:13 +0000, by Mychaela Falconia
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lunalcd3.pcb: layout changes around top bracketThu, 18 Nov 2021 06:55:23 +0000, by Mychaela Falconia
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lunalcd3.pcb: extend ground plane for top bracket additionThu, 18 Nov 2021 06:45:36 +0000, by Mychaela Falconia
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lunalcd3.pcb: add top bracket to LCD footprintThu, 18 Nov 2021 06:44:24 +0000, by Mychaela Falconia
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lunalcd3.pcb: reroute LCD power trace around right ear of bottom bracketThu, 18 Nov 2021 06:29:01 +0000, by Mychaela Falconia
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lunalcd3.pcb: manually add bottom strap to LCD footprintThu, 18 Nov 2021 06:11:27 +0000, by Mychaela Falconia
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lunalcd3 project startedThu, 18 Nov 2021 04:59:47 +0000, by Mychaela Falconia
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lunalcd2/src/Makefile: generate BOM outputsSat, 26 Jun 2021 21:16:48 +0000, by Mychaela Falconia
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lunalcd2/src/MCL: resistor parts nailed downSat, 26 Jun 2021 21:16:08 +0000, by Mychaela Falconia
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lunalcd2/src/MCL: different part for two-post VBAT supply headerSat, 26 Jun 2021 20:40:29 +0000, by Mychaela Falconia
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lunalcd2/pcb: add MakefileFri, 25 Jun 2021 23:08:00 +0000, by Mychaela Falconia
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lunalcd2.pcb: manual DRC fixesFri, 25 Jun 2021 22:59:37 +0000, by Mychaela Falconia
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lunalcd2.pcb complete except for DRCFri, 25 Jun 2021 22:52:20 +0000, by Mychaela Falconia
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lunalcd2.pcb almost completeFri, 25 Jun 2021 22:31:24 +0000, by Mychaela Falconia
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lunalcd2.pcb startedFri, 25 Jun 2021 20:29:36 +0000, by Mychaela Falconia
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lunalcd2/src/Makefile: generate elements.pcbFri, 25 Jun 2021 19:11:21 +0000, by Mychaela Falconia
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lunalcd2/src/Makefile: generate pcb-netlist.txtFri, 25 Jun 2021 19:08:13 +0000, by Mychaela Falconia
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lunalcd2: MCL binding completeFri, 25 Jun 2021 19:01:35 +0000, by Mychaela Falconia
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lunalcd2: structural Verilog source capturedFri, 25 Jun 2021 18:44:11 +0000, by Mychaela Falconia
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lunalcd2: footprint for the DIP switch packFri, 25 Jun 2021 17:12:02 +0000, by Mychaela Falconia
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lunalcd2 project started with MCLWed, 23 Jun 2021 23:53:15 +0000, by Mychaela Falconia