# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1592026081 0
# Node ID 43097651a26d9554eb7647c4c9bebc8516f7ee2f
# Parent  dbcb1d02d2561b2a4796468cad864d005f0de05b
duart28/src/primitives: adapted from fc-uja

diff -r dbcb1d02d256 -r 43097651a26d duart28/src/primitives
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/primitives	Sat Jun 13 05:28:01 2020 +0000
@@ -0,0 +1,27 @@
+/*
+ * This file defines the primitives to be instantiated from the structural
+ * Verilog source for the board: IC package types, basic components and
+ * subpackages to be mapped later in the MCL binding step.
+ */
+
+resistor	numpins 2;
+capacitor	numpins 2;
+inductor	numpins 2;
+
+/* IC packages */
+pkg_LQFP48	numpins 48;
+pkg_5pin	numpins 5;
+pkg_8pin	numpins 8;
+
+/* 74LVC125A single buffer and common part subpackages */
+buffer_ic_slot		mapped_pins (A, Y, nOE);
+buffer_ic_common	mapped_pins (Vcc, GND);
+
+/* crystal resonator */
+xtal_2pin_pkg	numpins 2;
+
+/* connectors */
+header_2pin		numpins 2;
+header_3pin		numpins 3;
+header_10pin		numpins 10;
+conn_miniUSB_plus4	numpins 9;