FreeCalypso > hg > fc-small-hw
changeset 0:0f9bdd60ce50
fc-small-hw separated from old freecalypso-schem repo
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/README Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,23 @@ +The little board to be built in this project is an adapter for connecting an +OMAP BeagleBoard-xM to a FreeCalypso device, specifically connecting Calypso's +MCSI to OMAP's McBSP (primary objective) and also connecting a 4-wire UART +(data + hw flow control) between the two devices - BB expansion interface +provides such a UART, and it costs us very little extra effort to connect it +along with MCSI. + +The present adapter will plug into the expansion header on the bottom side of +the BeagleBoard, implement logic voltage level translation between OMAP's 1.8 V +and Calypso's 2.8 V using the 1.8 V and 5 V power supplies provided by the +BeagleBoard, and bring 2.8 V UART and MCSI interfaces out on headers, intended +to be connected to a FreeCalypso board with jumper wires. + +The logic voltage level translation function will be accomplished using two +74AVC4T774PW ICs, one for the UART and one for MCSI. As a somewhat arbitrary +pick made for greater ease of PCB layout, the A side of each translating +transceiver IC will be the 2.8 V side and the B side will be the 1.8 V side. +Each of the 4 1-bit channels in the 74AVC4T774PW has its own direction control +pin, allowing us to neatly use one of these ICs for each 4-wire interface +despite mixed signal directions. MCSI_CLK and MCSI_FSYNCH are assumed to be +outputs from the Calypso like they are when driven by the DSP ROM code in the +silicon, and they will be voltage-translated in the Calypso to OMAP direction; +the other direction is NOT supported.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/pcb/Makefile Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,25 @@ +ALL= gerbers.zip bb2fc_pcb.ps bb2fc_pcb.pdf +EXPARG= + +all: ${ALL} + +.SUFFIXES: .ps .pdf + +.ps.pdf: + ps2pdf $*.ps + +bb2fc_pcb.ps: bb2fc.pcb + pcb -x ps --psfile $@ ${EXPARG} bb2fc.pcb + +gerbers.d: bb2fc.pcb + -rm -rf $@ + mkdir $@ + pcb -x gerber --gerberfile gerbers.d/bb2fc ${EXPARG} bb2fc.pcb + +gerbers.zip: gerbers.d + -rm -f $@ + cd gerbers.d; zip ../gerbers.zip * + +clean: + rm -f *.ps *.pdf bb2fc.pcb- + rm -rf gerbers.*
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/pcb/bb2fc.pcb Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,1308 @@ +# release: pcb 20140316 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20091103] + +PCB["" 1650.00mil 2140.00mil] + +Grid[1000.000000 0.0000 0.0000 0] +PolyArea[3100.006200] +Thermal[0.500000] +DRC[6.00mil 6.00mil 6.00mil 5.00mil 20.00mil 8.00mil] +Flags("nameonpcb,uniquename,clearnew,snappin") +Groups("1,c:2,s:3:4:5:6:7:8") +Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,60.00mil,35.00mil,10.00mil:Fat,40.00mil,60.00mil,35.00mil,10.00mil:Skinny,6.00mil,24.02mil,11.81mil,6.00mil"] + +Symbol[' ' 18.00mil] +( +) +Symbol['!' 12.00mil] +( + SymbolLine[0.0000 45.00mil 0.0000 50.00mil 8.00mil] + SymbolLine[0.0000 10.00mil 0.0000 35.00mil 8.00mil] +) +Symbol['"' 12.00mil] +( + SymbolLine[0.0000 10.00mil 0.0000 20.00mil 8.00mil] + SymbolLine[10.00mil 10.00mil 10.00mil 20.00mil 8.00mil] +) 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"clearline"] + Line[6.0310mm 35.0820mm 4.4660mm 36.6470mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 34.4320mm 4.7910mm 34.4320mm 10.00mil 20.00mil "clearline"] + Line[4.7910mm 34.4320mm 4.4660mm 34.1070mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 1330.00mil 8.2050mm 1330.00mil 10.00mil 20.00mil "clearline"] + Line[8.2050mm 1330.00mil 5.9900mm 31.5670mm 10.00mil 20.00mil "clearline"] + Line[5.9900mm 31.5670mm 4.4660mm 31.5670mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 33.1320mm 10.6030mm 33.1320mm 10.00mil 20.00mil "clearline"] + Line[10.6030mm 33.1320mm 6.4980mm 29.0270mm 10.00mil 20.00mil "clearline"] + Line[6.4980mm 29.0270mm 4.4660mm 29.0270mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 22.6360mm 8.2350mm 22.6360mm 10.00mil 20.00mil "clearline"] + Line[8.2350mm 22.6360mm 4.4660mm 18.8670mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 21.9860mm 10.1250mm 21.9860mm 10.00mil 20.00mil "clearline"] + Line[10.1250mm 21.9860mm 4.4660mm 16.3270mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 840.00mil 12.0150mm 840.00mil 10.00mil 20.00mil "clearline"] + Line[12.0150mm 840.00mil 4.4660mm 13.7870mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 20.6860mm 13.9050mm 20.6860mm 10.00mil 20.00mil "clearline"] + Line[13.9050mm 20.6860mm 4.4660mm 11.2470mm 10.00mil 20.00mil "clearline"] + Line[37.7400mm 37.6630mm 37.7400mm 45.7910mm 25.00mil 20.00mil "clearline"] + Line[35.6420mm 44.9490mm 37.6600mm 44.9490mm 25.00mil 20.00mil "clearline"] + Line[37.6600mm 44.9490mm 37.7400mm 45.0290mm 25.00mil 20.00mil "clearline"] + Line[35.6420mm 47.6490mm 35.6420mm 51.0490mm 25.00mil 20.00mil "clearline"] + Line[35.6420mm 51.0490mm 35.5660mm 51.1250mm 25.00mil 20.00mil "clearline"] + Line[37.7400mm 47.0610mm 37.7400mm 50.2510mm 25.00mil 20.00mil "clearline"] + Line[37.7400mm 50.2510mm 36.8660mm 51.1250mm 25.00mil 20.00mil "clearline"] + Line[34.6920mm 44.9490mm 34.6920mm 41.9810mm 25.00mil 20.00mil "clearline"] + Line[33.7420mm 44.9490mm 33.7420mm 45.8570mm 10.00mil 20.00mil "clearline"] + Line[33.7420mm 45.8570mm 34.1840mm 46.2990mm 10.00mil 20.00mil "clearline"] + Line[34.1840mm 46.2990mm 35.2000mm 46.2990mm 10.00mil 20.00mil "clearline"] + Line[35.2000mm 46.2990mm 35.7080mm 45.7910mm 10.00mil 20.00mil "clearline"] + Line[35.7080mm 45.7910mm 35.7080mm 45.0150mm 10.00mil 20.00mil "clearline"] + Line[35.7080mm 45.0150mm 35.6420mm 44.9490mm 10.00mil 20.00mil "clearline"] + Line[32.5480mm 37.9170mm 34.9460mm 37.9170mm 25.00mil 20.00mil "clearline"] + Line[34.9460mm 37.9170mm 35.2000mm 37.6630mm 25.00mil 20.00mil "clearline"] + Line[31.2480mm 37.9170mm 31.2480mm 40.5690mm 25.00mil 20.00mil "clearline"] + Line[31.2480mm 40.5690mm 31.3900mm 40.7110mm 25.00mil 20.00mil "clearline"] + Line[28.3420mm 51.1250mm 35.5660mm 51.1250mm 25.00mil 20.00mil "clearline"] + Line[850.00mil 32.4820mm 23.1090mm 32.4820mm 10.00mil 20.00mil "clearline"] + Line[23.1090mm 32.4820mm 23.7700mm 31.8210mm 10.00mil 20.00mil "clearline"] + Line[23.7700mm 31.8210mm 25.8602mm 31.8210mm 10.00mil 20.00mil "clearline"] + Line[21.7380mm 29.5350mm 24.0822mm 29.5350mm 10.00mil 20.00mil "clearline"] + Line[21.7380mm 29.5350mm 21.7380mm 31.6840mm 10.00mil 20.00mil "clearline"] + Line[21.7380mm 31.6840mm 850.00mil 31.8320mm 10.00mil 20.00mil "clearline"] + Line[24.9818mm 29.5350mm 26.8180mm 29.5350mm 10.00mil 20.00mil "clearline"] + Line[26.7598mm 31.8210mm 26.7598mm 29.5932mm 10.00mil 20.00mil "clearline"] + Line[26.7598mm 29.5932mm 26.8180mm 29.5350mm 10.00mil 20.00mil "clearline"] + Line[850.00mil 36.3820mm 24.0130mm 36.3820mm 10.00mil 20.00mil "clearline"] + Line[24.0130mm 36.3820mm 24.0240mm 36.3930mm 10.00mil 20.00mil "clearline"] + Line[850.00mil 35.7320mm 23.3630mm 35.7320mm 10.00mil 20.00mil "clearline"] + Line[23.3630mm 35.7320mm 24.0240mm 36.3930mm 10.00mil 20.00mil "clearline"] + Line[21.7380mm 17.0890mm 24.0822mm 17.0890mm 10.00mil 20.00mil "clearline"] + Line[21.7380mm 17.0890mm 21.7380mm 19.2380mm 10.00mil 20.00mil "clearline"] + Line[21.7380mm 19.2380mm 850.00mil 19.3860mm 10.00mil 20.00mil "clearline"] + Line[850.00mil 20.0360mm 23.1090mm 20.0360mm 10.00mil 20.00mil "clearline"] + Line[23.1090mm 20.0360mm 23.7700mm 19.3750mm 10.00mil 20.00mil "clearline"] + Line[23.7700mm 19.3750mm 25.8602mm 19.3750mm 10.00mil 20.00mil "clearline"] + Line[24.9818mm 17.0890mm 26.8180mm 17.0890mm 10.00mil 20.00mil "clearline"] + Line[26.7598mm 19.3750mm 26.7598mm 17.1472mm 10.00mil 20.00mil "clearline"] + Line[26.7598mm 17.1472mm 26.8180mm 17.0890mm 10.00mil 20.00mil "clearline"] + Line[850.00mil 23.9360mm 26.0450mm 23.9360mm 10.00mil 20.00mil "clearline"] + Line[26.0450mm 23.9360mm 26.0560mm 23.9470mm 10.00mil 20.00mil "clearline"] + Line[850.00mil 23.2860mm 25.4170mm 23.2860mm 10.00mil 20.00mil "clearline"] + Line[25.4170mm 23.2860mm 26.0670mm 23.9360mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 23.9360mm 21.2410mm 23.9360mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 19.3860mm 850.00mil 19.3860mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 20.0360mm 19.5640mm 20.0360mm 10.00mil 20.00mil "clearline"] + Line[19.5640mm 20.0360mm 20.2140mm 19.3860mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 23.2860mm 17.0650mm 23.2860mm 10.00mil 20.00mil "clearline"] + Line[17.0650mm 23.2860mm 17.6740mm 22.6770mm 10.00mil 20.00mil "clearline"] + Line[17.6740mm 22.6770mm 17.6740mm 21.9150mm 10.00mil 20.00mil "clearline"] + Line[17.6740mm 21.9150mm 19.5530mm 20.0360mm 10.00mil 20.00mil "clearline"] + Line[13.6100mm 31.8210mm 15.7790mm 31.8210mm 10.00mil 20.00mil "clearline"] + Line[15.7790mm 31.8210mm 15.7900mm 31.8320mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 35.7320mm 14.0170mm 35.7320mm 10.00mil 20.00mil "clearline"] + Line[14.0170mm 35.7320mm 13.6100mm 36.1390mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 32.4820mm 19.8070mm 32.4820mm 10.00mil 20.00mil "clearline"] + Line[19.8070mm 32.4820mm 20.4680mm 31.8210mm 10.00mil 20.00mil "clearline"] + Line[20.4680mm 31.8210mm 21.5790mm 31.8210mm 10.00mil 20.00mil "clearline"] + Line[21.5790mm 31.8210mm 850.00mil 31.8320mm 10.00mil 20.00mil "clearline"] + Line[15.7900mm 36.3820mm 17.1550mm 36.3820mm 10.00mil 20.00mil "clearline"] + Line[17.1550mm 36.3820mm 17.1660mm 36.3930mm 10.00mil 20.00mil "clearline"] + Line[17.1660mm 36.3930mm 17.9280mm 35.6310mm 10.00mil 20.00mil "clearline"] + Line[17.9280mm 35.6310mm 17.9280mm 33.5990mm 10.00mil 20.00mil "clearline"] + Line[17.9280mm 33.5990mm 19.0450mm 32.4820mm 10.00mil 20.00mil "clearline"] +) +Layer(2 "solder") +( + Line[35.2000mm 37.6630mm 29.6120mm 37.6630mm 25.00mil 20.00mil "clearline"] + Line[29.6120mm 37.6630mm 23.7700mm 31.8210mm 25.00mil 20.00mil "clearline"] + Line[23.7700mm 31.8210mm 23.7700mm 19.3750mm 25.00mil 20.00mil "clearline"] + Line[28.3420mm 51.1250mm 21.7380mm 44.5210mm 25.00mil 20.00mil "clearline"] + Line[21.7380mm 44.5210mm 21.7380mm 17.0890mm 25.00mil 20.00mil "clearline"] + Polygon("clearpoly") + ( + [1.1640mm 1.0870mm] [40.7880mm 1.0870mm] [40.7880mm 53.4110mm] [1.1640mm 53.4110mm] + ) +) +Layer(3 "GND") +( +) +Layer(4 "power") +( +) +Layer(5 "signal1") +( +) +Layer(6 "signal2") +( +) +Layer(7 "signal3") +( +) +Layer(8 "signal4") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( + Text[270.00mil 380.00mil 0 100 "MCSI" "clearline"] + Text[270.00mil 1040.00mil 0 100 "UART" "clearline"] + Text[160.00mil 1870.00mil 0 100 "BB2FC Adapter" "clearline"] + Text[160.00mil 1950.00mil 0 100 "Mychaela N. Falconia" "clearline"] +) +NetList() +( + Net("Calypso_MCSI_CLK" "(unknown)") + ( + Connect("J2-4") + Connect("U1-5") + ) + Net("Calypso_MCSI_FSYNCH" "(unknown)") + ( + Connect("J2-3") + Connect("U1-4") + ) + Net("Calypso_MCSI_RXD" "(unknown)") + ( + Connect("J2-5") + Connect("U1-6") + ) + Net("Calypso_MCSI_TXD" "(unknown)") + ( + Connect("J2-2") + Connect("U1-3") + ) + Net("Calypso_UART_CTS" "(unknown)") + ( + Connect("J3-2") + Connect("U2-3") + ) + Net("Calypso_UART_RTS" "(unknown)") + ( + Connect("J3-5") + Connect("U2-6") + ) + Net("Calypso_UART_RxD" "(unknown)") + ( + Connect("J3-4") + Connect("U2-5") + ) + Net("Calypso_UART_TxD" "(unknown)") + ( + Connect("J3-3") + Connect("U2-4") + ) + Net("GND" "(unknown)") + ( + Connect("C1-2") + Connect("C2-2") + Connect("C3-2") + Connect("C4-2") + Connect("C5-2") + Connect("C6-2") + Connect("C7-2") + Connect("J1-27") + Connect("J1-28") + Connect("J2-1") + Connect("J3-1") + Connect("U1-8") + Connect("U1-9") + Connect("U1-10") + Connect("U2-1") + Connect("U2-7") + Connect("U2-9") + Connect("U2-10") + Connect("U3-2") + ) + Net("OMAP_McBSP_CLK" "(unknown)") + ( + Connect("J1-14") + Connect("U1-12") + ) + Net("OMAP_McBSP_DR" "(unknown)") + ( + Connect("J1-18") + Connect("U1-14") + ) + Net("OMAP_McBSP_DX" "(unknown)") + ( + Connect("J1-12") + Connect("U1-11") + ) + Net("OMAP_McBSP_FS" "(unknown)") + ( + Connect("J1-16") + Connect("U1-13") + ) + Net("OMAP_UART_CTS" "(unknown)") + ( + Connect("J1-4") + Connect("U2-11") + ) + Net("OMAP_UART_RTS" "(unknown)") + ( + Connect("J1-10") + Connect("U2-14") + ) + Net("OMAP_UART_RxD" "(unknown)") + ( + Connect("J1-8") + Connect("U2-13") + ) + Net("OMAP_UART_TxD" "(unknown)") + ( + Connect("J1-6") + Connect("U2-12") + ) + Net("P_1V8" "(unknown)") + ( + Connect("C3-1") + Connect("C5-1") + Connect("C7-1") + Connect("J1-1") + Connect("U1-15") + Connect("U2-15") + ) + Net("P_2V8" "(unknown)") + ( + Connect("C2-1") + Connect("C4-1") + Connect("C6-1") + Connect("U1-1") + Connect("U1-2") + Connect("U1-7") + Connect("U1-16") + Connect("U2-2") + Connect("U2-8") + Connect("U2-16") + Connect("U3-5") + ) + Net("P_5V" "(unknown)") + ( + Connect("C1-1") + Connect("J1-2") + Connect("U3-1") + Connect("U3-3") + ) +)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/74AVC4T774PW.pinout Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,17 @@ +#pin name pin number +DIR:1 1 +DIR:2 2 +A:1 3 +A:2 4 +A:3 5 +A:4 6 +DIR:3 7 +DIR:4 8 +OE 9 +GND 10 +B:4 11 +B:3 12 +B:2 13 +B:1 14 +VccB 15 +VccA 16
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/MCL Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,111 @@ +part 0603C-X5R-1uF: + value=1uF + footprint=0603 + description=Ceramic chip capacitor, X5R, 1 uF, 0603 + manufacturer=Samsung Electro-Mechanics + manufacturer_part_number=CL10A105KB8NNNC + vendor=Digi-Key + vendor_part_number=1276-1860-1-ND + npins=2 + +part 0402C-100n: + value=100n + footprint=0402 + description=Ceramic chip capacitor, X5R, 0.1 uF, 0402 + manufacturer=Murata + manufacturer_part_number=GRM155R61C104KA88J + vendor=Digi-Key + vendor_part_number=490-6310-1-ND + npins=2 + +# 5V input bypass cap +C1: + hier=C1 + part=0603C-X5R-1uF + +# 2.8V regulator output bypass cap +C2: + hier=C2 + part=0603C-X5R-1uF + +# 1.8V input bypass cap +C3: + hier=C3 + part=0603C-X5R-1uF + +# U1 VccA cap +C4: + hier=C4 + part=0402C-100n + +# U1 VccB cap +C5: + hier=C5 + part=0402C-100n + +# U2 VccA cap +C6: + hier=C6 + part=0402C-100n + +# U2 VccB cap +C7: + hier=C7 + part=0402C-100n + +# BeagleBoard-xM connector +J1: + hier=bb_xm_conn + manufacturer=Mill-Max + manufacturer_part_number=435-40-228-00-160000 + description=Header, 0.100", dual row, 28 posts, 3.18 mm mating height + vendor=Digi-Key + vendor_part_number=ED1372-28-ND + footprint=HEADER28_3 + npins=28 + +part header-5pin: + footprint=JUMPER5 + description=Header, 0.100", single row, 5 posts + manufacturer=Molex + manufacturer_part_number=0901200125 + vendor=Digi-Key + vendor_part_number=WM8075-ND + npins=5 + +# 2.8V MCSI connector +J2: + hier=J2 + part=header-5pin + +# 2.8V UART connector +J3: + hier=J3 + part=header-5pin + +part buffer-ic: + manufacturer=NXP or TI + device=74AVC4T774PW + footprint=file:SN74AVC4T774PW + npins=16 + pinout=74AVC4T774PW.pinout + +# Buffer IC for MCSI +U1: + part=buffer-ic + slotmap=U1.slotmap + +# Buffer IC for UART +U2: + part=buffer-ic + slotmap=U2.slotmap + +# 2.8V regulator +U3: + hier=reg.pkg + manufacturer=TI + device=TLV70028DDC + part=yes + description=LDO regulator, 2.8 V output, SOT-5 + footprint=file:TLV700xxDDC + npins=5
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/Makefile Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,28 @@ +BOMS= tallied-bom.txt tallied-bom.csv comptab.txt +NETS= sverp.unet bound.unet pcb-netlist.txt + +all: ${BOMS} ${NETS} elements.pcb + +sverp.unet: schem.v regulator.v primitives + ueda-sverp -o $@ schem.v regulator.v + +bound.unet: MCL sverp.unet + unet-bind -c sverp.unet $@ + +pcb-netlist.txt: bound.unet + unet2pcb bound.unet $@ + +tallied-bom.txt: MCL + ueda-mkbom -cr > $@ + +tallied-bom.csv: MCL + ueda-csvbom > $@ + +comptab.txt: MCL + ueda-shortbom > $@ + +elements.pcb: MCL + ueda-getfps -ch | ueda-runm4 > $@ + +clean: + rm -f *.unet *.txt *.csv errs elements.pcb
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/U1.slotmap Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,6 @@ +#instance slot +U1slot1 1 +U1slot2 2 +U1slot3 3 +U1slot4 4 +U1common
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/U2.slotmap Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,6 @@ +#instance slot +U2slot1 1 +U2slot2 2 +U2slot3 3 +U2slot4 4 +U2common
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/primitives Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,12 @@ +capacitor numpins 2; + +/* LDO regulator IC */ +pkg_5pin numpins 5; + +/* 74AVC4T774PW single buffer and common part subpackages */ +buffer_ic_slot mapped_pins (A, B, DIR); +buffer_ic_common mapped_pins (VccA, VccB, GND, OE); + +/* connectors */ +header_5pin numpins 5; +conn_28pin numpins 28;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/regulator.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,13 @@ +module regulator (IN, OUT, GND, EN); + +input IN, GND, EN; +output OUT; + +pkg_5pin pkg ( .pin_1(IN), + .pin_2(GND), + .pin_3(EN), + .pin_4(), /* no connect */ + .pin_5(OUT) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/schem.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,129 @@ +module board (); + +wire GND, P_5V, P_1V8, P_2V8; +wire REGEN; + +wire OMAP_McBSP_DR, OMAP_McBSP_FS, OMAP_McBSP_CLK, OMAP_McBSP_DX; +wire OMAP_UART_RTS, OMAP_UART_RxD, OMAP_UART_TxD, OMAP_UART_CTS; + +wire Calypso_MCSI_TXD, Calypso_MCSI_RXD, Calypso_MCSI_CLK, Calypso_MCSI_FSYNCH; +wire Calypso_UART_TxD, Calypso_UART_RxD, Calypso_UART_RTS, Calypso_UART_CTS; + +conn_28pin bb_xm_conn ( .pin_1(P_1V8), + .pin_2(P_5V), + .pin_3(), + .pin_4(OMAP_UART_CTS), + .pin_5(), + .pin_6(OMAP_UART_TxD), + .pin_7(), + .pin_8(OMAP_UART_RxD), + .pin_9(), + .pin_10(OMAP_UART_RTS), + .pin_11(), + .pin_12(OMAP_McBSP_DX), + .pin_13(), + .pin_14(OMAP_McBSP_CLK), + .pin_15(), + .pin_16(OMAP_McBSP_FS), + .pin_17(), + .pin_18(OMAP_McBSP_DR), + .pin_19(), + .pin_20(), + .pin_21(), + .pin_22(), + .pin_23(), + .pin_24(), + .pin_25(REGEN), + .pin_26(), + .pin_27(GND), + .pin_28(GND) + ); + +capacitor C1 (P_5V, GND); +capacitor C3 (P_1V8, GND); + +regulator reg ( .IN(P_5V), + .OUT(P_2V8), + .GND(GND), + .EN(P_5V) + ); + +capacitor C2 (P_2V8, GND); + +/* U1 for MCSI */ + +buffer_ic_common U1common (.VccA(P_2V8), + .VccB(P_1V8), + .GND(GND), + .OE(GND) + ); + +capacitor C4 (P_2V8, GND); +capacitor C5 (P_1V8, GND); + +buffer_ic_slot U1slot1 (.A(Calypso_MCSI_TXD), + .B(OMAP_McBSP_DR), + .DIR(P_2V8) + ); + +buffer_ic_slot U1slot2 (.A(Calypso_MCSI_FSYNCH), + .B(OMAP_McBSP_FS), + .DIR(P_2V8) + ); + +buffer_ic_slot U1slot3 (.A(Calypso_MCSI_CLK), + .B(OMAP_McBSP_CLK), + .DIR(P_2V8) + ); + +buffer_ic_slot U1slot4 (.A(Calypso_MCSI_RXD), + .B(OMAP_McBSP_DX), + .DIR(GND) + ); + +header_5pin J2 (.pin_1(GND), + .pin_2(Calypso_MCSI_TXD), + .pin_3(Calypso_MCSI_FSYNCH), + .pin_4(Calypso_MCSI_CLK), + .pin_5(Calypso_MCSI_RXD) + ); + +/* U2 for UART */ + +buffer_ic_common U2common (.VccA(P_2V8), + .VccB(P_1V8), + .GND(GND), + .OE(GND) + ); + +capacitor C6 (P_2V8, GND); +capacitor C7 (P_1V8, GND); + +buffer_ic_slot U2slot1 (.A(Calypso_UART_CTS), + .B(OMAP_UART_RTS), + .DIR(GND) + ); + +buffer_ic_slot U2slot2 (.A(Calypso_UART_TxD), + .B(OMAP_UART_RxD), + .DIR(P_2V8) + ); + +buffer_ic_slot U2slot3 (.A(Calypso_UART_RxD), + .B(OMAP_UART_TxD), + .DIR(GND) + ); + +buffer_ic_slot U2slot4 (.A(Calypso_UART_RTS), + .B(OMAP_UART_CTS), + .DIR(P_2V8) + ); + +header_5pin J3 (.pin_1(GND), + .pin_2(Calypso_UART_CTS), + .pin_3(Calypso_UART_TxD), + .pin_4(Calypso_UART_RxD), + .pin_5(Calypso_UART_RTS) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/bb2fc/schem+bom/sympath Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,1 @@ +.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/design-spec Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,536 @@ +FreeCalypso UART+JTAG Adapter +Board design specification + +1. Purpose and scope + +The circuit board described in this specification will be an adapter for +connecting a host PC or laptop (via USB) to the following 3 development +interfaces on FreeCalypso GSM devices: + +* A 3-wire UART interface intended for RVTMUX on Calypso's IrDA UART +* Calypso JTAG +* Iota nTESTRESET + +The core function of interfacing from USB to a UART, JTAG and GPIO will be +performed by an FT2232D chip, but the board described herein has two key +differences from a generic FT2232x board, key differences which necessitate the +development of a custom board: + +* Our board will have 3-state buffers on the JTAG lines and an open drain + driver on the nTESTRESET line, wired in such a way that they cannot be + accidentally turned on while the FT2232D is in its power-up default UART + mode, prior to the software switch into the MPSSE+GPIO mode. + +* The target connection interface will be presented not only on general-purpose + headers, but also on a special FFC connector, to be used with our future + FreeCalypso handset boards that will use the FFC-based development interface + copied from Foxconn's Pirelli DP-L10 phone. + +The gadget to be built is intended to serve the following two purposes, in this +order of importance: + +Application 1: the present adapter will be required to do initial bring-up, +deep development and production-time programming and testing on our upcoming +FreeCalypso handset boards. Calypso's MODEM UART will be wired to the handset's +built-in USB-serial port also acting as the charging power source, but that +interface is intended for end users - deep development, initial bring-up and +production processes will need to be done through the IrDA UART wired to the +FFC interface through the present adapter. JTAG is not expected to be needed, +but is "thrown in for free" - however, the Iota nTESTRESET line will be very +useful for commanding system switch-on that can be distinguished from both the +end user power-on button and the charger plug event, as well as for easy +recovery from any hung state. + +Application 2: it costs us nothing extra to bring the target connection +interface out on generic headers in addition to the FFC connector. If anyone +needs to play with JTAG on our FCDEV3B or on a Motorola C1xx phone hacked up +with little wires, the present adapter will be more robust compared to +unbuffered COTS FT2232x breakout boards thanks to our 3-state buffers +protecting the JTAG lines from FT2232's initial UART mode garbage. + +However, the present FreeCalypso UART+JTAG adapter board is NOT intended to be +used as a generic JTAG adapter for non-Calypso targets. The set of additional +signals needed besides JTAG is quite different between the two: most traditional +(non-GSM) ARM processors and DSPs have TRST and/or SRST signals, and sometimes +also DBGRQ/DBGACK - whereas the Calypso+Iota chipset has no TRST, and the way +Iota's nTESTRESET signal works is quite different. Companies like Tin Can Tools +(Flyswatter2) already provide superb-quality and very cheap FT2232x-based JTAG +adapters for "generic" applications, and there is no point in trying to compete +with them - instead we need a Calypso-specific adapter that provides a UART, +nTESTRESET control and JTAG in this order of priority. + +2. Detailed design + +2.1. FT2232D core block + +The FTDI chip chosen for this adapter board is FT2232D. One of the FT2232x +devices is needed because we need MPSSE for JTAG plus a second channel for the +RVTMUX UART, leaving FT2232C/D/L and FT2232H as the two viable candidates. The +FT2232H high speed device does not offer anything useful for our application, +hence the more basic FT2232D has been chosen on the principle of "bez nadobnosti +nosimyj nabryushnik vreden" (a Russian proverb) - introducing USB high speed +capability (480 Mbps USB signaling) with FT2232H would increase the chances of +USB signal integrity problems due to suboptimal PCB layout or suboptimal USB +cable quality while providing absolutely no useful gain in our application, +whereas FT2232D is inherently safer in this regard by not having that USB high +speed capability in the first place. FT2232D is a direct drop-in for the +earlier FT2232C and FT2232L chips; FT2232D is a currently active part available +from Digi-Key whereas its predecessors are surplus-only parts. + +FT2232C/D devices only support MPSSE on Channel A, hence our FreeCalypso +UART+JTAG adapter will follow the general canon for such adapters in that JTAG +and test reset will be on Channel A, whereas Channel B will be used for the +RVTMUX UART. + +There will be a 93C46 EEPROM connected to the FT2232D chip. This EEPROM is +needed so that we can give our adapter a custom USB ID (out of the range of USB +IDs allocated by FTDI to Falconia Partners LLC); this custom USB ID is needed +for several reasons: + +* We don't want the ftdi_sio driver in the Linux kernel to create two ttyUSBx + devices for both FT2232D channels only to have the first of the pair disappear + when a custom libftdi-based program is run to make use of JTAG and/or reset + functions on Channel A - instead we would like to have this driver create + only one ttyUSBx device for the UART on Channel B. There already exist + several other UART+JTAG adapters whose creators and users had the same need, + and the ftdi_sio driver in Linux supports them. The existing adapters of + this kind are identified by custom USB IDs, and once our own adapter advances + past the vaporware phase, we'll be submitting a one-line patch to the Linux + kernel driver to add our custom USB ID to the list. + +* We will have a custom libftdi-based program for sending nTESTRESET to the + FreeCalypso GSM device target through our adapter; this program will have an + easier time locating our USB device among other potential FTDI-based devices + if we use a custom USB ID. + +* When the time comes to configure OpenOCD to do JTAG through our adapter, + having a custom USB ID will similarly help prevent erroneous binding to other + FTDI-based devices that may be present. + +2.2. Buffering logic for JTAG + +One significant design blemish of the otherwise quite versatile FT2232D is that +"bit" modes like MPSSE cannot be configured in the EEPROM, instead they can only +be entered dynamically on software command from the host. As the result, an +FT2232D channel that is meant to be used for, say, JTAG on a given board will +still operate in its default UART mode when USB power is first applied, and will +remain in this state indefinitely long, until the user runs a program on the +host that issues a software command to enter the "bit" mode - which may never +happen. If an FT2232D channel is wired for JTAG but the chip operates in its +default UART mode, the following problems will occur if the signals are wired +directly without additional buffering logic: + +* The ADBUS0 line which becomes TCK in JTAG mode is TxD in UART mode, and will + thus drive a high level on power-up - even though the quiescent state on TCK + should be low. + +* JTAG TDO line (output from the target) needs to be connected to ADBUS2 - this + signal becomes an input in MPSSE mode - but in the power-up default UART mode + ADBUS2 is an output. Thus this default output can end up fighting with the + target's TDO output, potentially damaging the target, the adapter or both. + +(The other two JTAG signals - TDI and TMS driven from ADBUS1 and ADBUS3 - are + less of a problem because in the power-up default UART mode these FT2232D pins + are inputs with weak internal pull-ups on them.) + +Our solution to this problem is to insert 3-state buffers (unidirectional in +the JTAG signal direction) into all 4 JTAG lines. We shall use 3-state buffers +with active-low enables, and the two enable lines (one for the TCK, TDI and TMS +outputs from the adapter, the other for the TDO input) will come from FT2232D +pins ADBUS5 and ADBUS6. In the MPSSE mode used for JTAG these pins become GPIOs +and will need to be configured as outputs driving low in order to enable JTAG, +but in the power-up default UART mode they are inputs with internal pull-ups, +and we will have additional external pull-ups for safety. The effects will be +as follows: + +* As long as the FT2232D channel is in UART mode, the 3-state buffers can never + be enabled. All JTAG outputs from the adapter will be tristated (i.e., the + same as if the adapter weren't there, presenting the target with its normal + sans-JTAG state), there will be no fighting on ADBUS2, and the UART will sense + all of its inputs as inactive high. + +* As the MPSSE mode is entered on software command, the initial pin direction + mask byte should be 0x01, keeping ADBUS0 as an output, but then an MPSSE GPIO + command should be given, enabling the other outputs along with sensible + initial values. + +* ADBUS6 should be driven low to enable the TDO receiving buffer (it will have + a weak pull-up on the buffer's input in order to not float when there is no + target connected) right after ADBUS2 is switched to being an input, but + ADBUS5 can be driven low or high at any time afterward to enable or disable + the JTAG outputs. + +2.3. Sideband signals alongside JTAG + +2.3.1. Iota nTESTRESET driver + +The test reset line in the Calypso+Iota solution (nTESTRESET) is handled by the +VRPC block in the Iota ABB which is essentially a PMIC. It is always pulled up +inside the GSM device to a non-logic power rail, and this circuit works even +when the mobile is in the switched-off state with all of the main voltage +regulators for regular logic turned off. The raw nTESTRESET line is not meant +to ever be driven by any kind of active push-pull logic driver; instead it is +meant to be shorted to GND to trigger the reset, through either a pushbutton +switch or an OC/OD driver. + +Back when TI made their x-Sample and Leonardo development boards, they +apparently preferred to drive their JTAG+reset test interface (14-pin header in +TI's JTAG pinout) with whatever generic (non-Calypso-specific) JTAG adapter +they already had at the time, and as their 14-pin JTAG interface was defined, +pin 2 (reset) was defined to be TRST with an active push-pull driver in the +JTAG host adapter (or "emulator" as they call it). These x-Sample and Leonardo +boards have a little on-board circuit between this connector pin 2 and the +actual nTESTRESET; this circuit consists of two transistors and has the effect +of protecting the internal nTESTRESET line from whatever the external driver +may be doing: if the external adapter drives a logic low, the transistor circuit +pulls nTESTRESET low via what is effectively an OC driver, otherwise the JTAG +block presents a Hi-Z state to the nTESTRESET line. This circuit has been +copied from Leonardo schematics on our own FCDEV3B, but the current plan is to +not include it on the handset board, instead bringing out nTESTRESET in its +native form on the FFC interface like the Pirelli DP-L10 board appears to do. + +Our FreeCalypso UART+JTAG adapter will drive this nTESTRESET pin with an open +drain driver. This driving arrangement is compatible with both approaches: +either direct nTESTRESET connection or the transistor circuit on FCDEV3B and on +TI's boards. It does, however, make our adapter specific to Calypso+Iota GSM +devices: more generic ARM processors and DSPs will often have more standard +TRST and/or SRST signals instead, possibly needing active push-pull drivers. + +To protect the reset line from FTDI's UART-default bogosity, the input to the +non-inverting open drain driver will come from ADBUS7, which is an input in the +FT2232D's power-up default UART mode. Like ADBUS5 and ADBUS6 controls for the +3-state buffers for JTAG, this ADBUS7 line will have an additional external +pull-up for safety, thus the reset can never be triggered accidentally while +the FT2232D channel is in UART mode - the only way to trigger the test reset +will be to first put the channel into the MPSSE+GPIO mode, then make ADBUS7 an +output driving low. + +2.3.2. Calypso nEMU0 and nEMU1 pins + +The Calypso chip has two JTAG-sideband pins called nEMU0 and nEMU1. They form +some kind of debug/development interface which is not needed in normal product +operation, and all Calypso-based GSM phone and modem product boards known to us +leave them unconnected - even those product boards on which the regular JTAG +pins are brought out (Pirelli DP-L10 and some Mot C1xx variants). TI's +Leonardo schematics leave them unconnected as well, but their more complete +x-Sample boards have them brought out to the 14-pin JTAG connector. Our +FCDEV3B has them brought out as well. + +The problem with these nEMU0 and nEMU1 pins is that they are undocumented: the +docs we have only say that they are bidirectional signals with pull-ups, and +nothing else. We have on-board pull-ups on these two lines on our FCDEV3B +(copied from TI's E-Sample board) strengthening the Calypso chip's supposed +internal pull-ups, but we don't know what will happen if either or both pins +are driven low externally (at boot or any other time), nor do we know if the +Calypso chip itself ever drives or pulses them low as outputs. Common sense +suggests that one of their likely functions is probably to hold the ARM7 core +in the debug halt state directly out of reset, and possibly disable the +watchdog timer which is otherwise enabled and ticking at this time - but we +don't know any of the details. + +Because we don't know exactly how these nEMU0 and nEMU1 pins work, the only +sense in which we can support them is to provide a way to use our FreeCalypso +UART+JTAG adapter as a reverse engineering tool, experimentally playing with +these nEMU[1:0] pins on an FCDEV3B. We are going to make the following simple +provision to facilitate such experimentation: we are going to connect FT2232D +pins ACBUS2 and ACBUS3 to pins 13 and 14 on the 14-pin JTAG header, which are +the pins for nEMU0 and nEMU1. Unlike all other signals, this one will be a +direct connection without any buffering. ACBUS2 and ACBUS3 function as open +drain LED drivers in the power-up default UART mode, and these pins have been +chosen on the reasoning that they are expected to stay non-driving as long as +no one actually opens Channel A as a UART and tries to send something through +it. The following important additional considerations apply: + +* These nEMU0 and nEMU1 signals are NOT included in the FFC interface defined + by Foxconn/Pirelli which we are copying for our FreeCalypso handset boards. + The positive implication is that the development interface for these FC + handset boards will not be adversely affected by the potentially dangerous + unbuffered connection to FT2232D pins; the negative implication is that if we + ever do learn how to use these nEMU[1:0] pins to do whatever they can do, + that ability won't be available on the handset boards. However, the latter + loss is deemed to be acceptable: the most plausible function of these + nEMU[1:0] pins is to enter JTAG debug state directly out of reset, and we + don't need this ability when we have the internal boot ROM enabled via nIBOOT: + we can interrupt and divert the boot process serially, and then enter the + debug state through the regular JTAG scan chain. + +* Anyone using the 14-pin JTAG header interface to connect to a target such as + FCDEV3B that does have nEMU0 and nEMU1 signals on pins 13 and 14 still has + the freedom to connect or not connect these signals as desired. With our + current FCDEV3B certain mechanical constraints practically impose the + requirement of making a custom cable in any case: the spacing between headers + on the FCDEV3B is too tight for standard ribbon cables terminated with IDC + connectors (there is no room for the bulky sides of those IDC connectors), + hence one needs to crimp female terminals onto individual wires and insert + them into a crimp housing instead. In light of these considerations, you + should only connect pins 13 and 14 between our adapter and your target if you + are specifically interested in experimenting with driving or sensing Calypso's + nEMU0 and nEMU1 signals, otherwise leave them unconnected. + +* Our entire "support" for these nEMU[1:0] pins will consist of two PCB traces + connecting FT2232D's ACBUS2 and ACBUS3 pins to two pins on the 14-pin JTAG + header. This arrangement, which could be considered quite risky under + different circumstances, does absolutely nothing and cannot cause any harm if + those two header pins are NOT subsequently connected to an actual Calypso + target. + +2.4. FT2232D I/O pin summary + +Channel A pins will be assigned and connected as follows: + +ADBUS0: JTAG TCK (fixed by FTDI) +ADBUS1: JTAG TDI (fixed by FTDI) +ADBUS2: JTAG TDO (fixed by FTDI) +ADBUS3: JTAG TMS (fixed by FTDI) +ADBUS4: unused and unconnected +ADBUS5: active-low output enable control for JTAG outputs +ADBUS6: active-low output enable control for TDO receiving buffer +ADBUS7: active-low nTESTRESET control + +ACBUS0: unused and unconnected +ACBUS1: unused and unconnected +ACBUS2: wired to JTAG header pin 13 (nEMU0) +ACBUS3: wired to JTAG header pin 14 (nEMU1) + +The 3 pins that are unused and unconnected (ADBUS4, ACBUS0 and ACBUS1) can be +configured as either inputs with internal pull-ups or outputs. For the +remaining pins which do have assigned functions, the following software init +sequence should be adhered to: + +* As the MPSSE mode is entered on software command, the initial pin direction + mask byte should be 0x01. The critical points are to set ADBUS0 as an output + at this point so it never glitches through a non-driving state (it is TxD in + the power-up default UART mode), make ADBUS2 an input as it will need to be + once TDO is enabled, and set ADBUS5-7 as inputs. ADBUS5-7 need to be inputs + at this stage (the connected logic will sense the inactive high level from + pull-up resistors) because the initial output value for initialized-as-output + pins is not defined. + +* MPSSE Set Data Bits High Byte (0x82) command should be given to set ACBUS2 + and ACBUS3 as inputs, leaving nEMU[0:1] pins undisturbed until and unless you + are playing with them. + +* MPSSE Set Data Bits Low Byte (0x80) command should be given to make ADBUS0 + (TCK) an output driving 0, make ADBUS1 (TDI) an output driving 1, keep ADBUS2 + as an input from the MPSSE mode entry step, make ADBUS3 (TMS) an output + driving 1, and make ADBUS6 (TDO receiving buffer control) an output driving 0. + ADBUS5 (JTAG output buffer control) and ADBUS7 (nTESTRESET driver) should be + configured as outputs at this point, but their driving values will depend on + the application. + +Channel B will be used as a data-leads-only UART with standard wiring requiring +no software intervention: + +BDBUS0: TxD (UART output) +BDBUS1: RxD (UART input) +the rest: unused and unconnected + +2.5. Logic voltage levels and buffering + +Many FT2232x-based JTAG adapters have level-translating buffers between FT2232x +pins and the target interface in order to support targets with different logic +voltage levels, usually from 3.3 V down to 1.8 V, or sometimes an even wider +allowed range: for example, the Flyswatter2 adapter from Tin Can Tools supports +target logic voltage levels from 1.6 to 5.0 V. + +In our case such voltage level shifting is not really needed: Calypso is 2.8 V +native, but perfectly tolerant of 3.3 V inputs as well. The following +approaches have been considered for our FreeCalypso UART+JTAG adapter: + +Approach 1: put a 3.3 V regulator on our board, run FT2232D I/O pins at 3.3 V, +run the 3-state buffers for JTAG at 3.3 V as well, and connect the UART lines +to FT2232D Channel B pins directly, without buffering. This approach relies on +Calypso's inputs being tolerant of 3.3 V and Calypso's 2.8 V outputs producing +voltage levels suitable for 3.3 V inputs. In practice this approach has already +been used quite extensively in other contexts: we connect Calypso I/O to 3.3 V +logic when we connect FCDEV3B UARTs to generic off-the-shelf FT2232x adapter +boards, users of headset jack serial adapters for Motorola and Openmoko phones +do likewise, Openmoko connected Calypso's 2.8 V UART to their 3.3 V application +processor, and Foxconn/Pirelli appear to have done likewise with their built-in +USB-serial interface based on a CP2102 chip with 3.3 V I/O. + +Approach 2: put both 3.3 V and 2.8 V regulators on our board, run FT2232D I/O +pins at 3.3 V (the lowest I/O voltage officially supported by FT2232x chips), +have the inputs from the Calypso target go directly to 3.3 V logic like with +Approach 1, but run the 3-state buffers for JTAG outputs plus an always-enabled +buffer for the UART output at 2.8 V. This approach makes the adapter's outputs +2.8 V proper, but at the cost of an extra on-board regulator. + +Approach 3: similar to Approach 2, but omit the on-board 2.8 V regulator and +instead power the 2.8 V output buffers from the target voltage reference pin +provided both on TI's 14-pin JTAG interface (used on development boards, both +TI's and our own FCDEV3B) and on the FFC interface we are copying from +Foxconn/Pirelli. Compared to Approach 2, this approach eliminates the extra +on-board regulator, but would cause some power to be drawn from the target to +power the output buffers. This approach would also create difficulties if a +user wishes to use the generic header interface (as opposed to the highly +specialized FFC interface), and there is no source from which the target +reference voltage pin can be supplied. A compromise approach could be +implemented by putting a 3-pin jumper header on our board, selecting the power +to the output buffers between internal 3.3 V and the external target voltage +reference pin, but having that jumper set to the internal 3.3 V supply would +effectively bring us back to Approach 1. + +Approach 4: do what the "big guys" do in terms of voltage level translation: +use special dual-supply translating buffers in both directions, supporting any +target voltage level at least between 1.8 and 3.3 V or possibly wider. This +approach would be appropriate for a more general-purpose JTAG adapter that needs +to work with, say, 1.8 V targets, but given that our adapter is specific to the +Calypso which has 2.8V-native, 3.3V-tolerant I/O, the extra complexity of +full-blown voltage level translation is not really justifiable. + +Approaches 3 and 4 are excessively complex and cumbersome, and cannot be +justified in our Calypso-specific application. The practical choice is thus +between approaches 1 and 2. My (Mother Mychaela's) initial leaning was toward +Approach 1, but upon further reflection I swayed over to Approach 2. The cost +of the additional on-board 2.8 V regulator in terms of PCB real estate and +layout complexity is not too great, and given that our adapter is very +specifically for the Calypso and no other targets, it makes more sense to put +out Calypso's native voltage levels, rather than merely compatible ones. + +Approach 2 will be used on our FreeCalypso UART+JTAG adapter, with the following +additional nuances: + +* A 74LVC125A output buffer (4 individual buffers in one package) powered from + the 2.8 V regulator will be used for the 4 logic outputs from our adapter: + JTAG outputs TCK, TDI and TMS, and the single UART output. The output enables + for the JTAG outputs will come from ADBUS5, whereas the UART output will be + always enabled. + +* Another similar buffer, but powered from the 3.3 V regulator will be used for + the two logic signals going the other way: JTAG TDO and the UART input. The + buffer for TDO will be enabled by ADBUS6, the UART input will be always + enabled. There will be a pull-up resistor to local 2.8 V on the input + (target interface) side of each buffer. The buffer for TDO is needed for + 3-state control, but an identical buffer will also be used for the UART input + for the sake of symmetry, and to present the target with a pull-up to 2.8 V + rather than FT2232D's internal pull-up to 3.3 V. + +* All pull-ups on the interface between FT2232D pins and the just-described + buffers will be to 3.3 V. + +* A dedicated 3.3 V regulator will be used, instead of trying to use the feeble + one built into the FT2232D, as the datasheet-stated limit of 5 mA seems like + too little margin. + +* The only interface on which the target would ever see 3.3 V rather than 2.8 V + will be the purely experimental provision for Calypso nEMU[1:0] described in + section 2.3.2, to be used only by those who are specifically interested in + that line of experimentation, and not in any other use cases. It makes no + sense to attempt voltage level-translating buffering for these signals when + we don't even know if they are really inputs or outputs, and under what + conditions. + +The target voltage reference pins on the TI-style 14-pin JTAG header connector +and on the Foxconn/Pirelli-style FFC connector will remain unused and +unconnected. One could make an argument that not using the target-provided I/O +voltage reference is wrong, but the issue needs to be seen in context. TI's +14-pin JTAG interface was designed for use in a wide range of applications, +covering I/O voltages at least between 1.8 and 3.3 V, and TI's XDS JTAG adapters +support this wide range of I/O voltages just like the ones made by community +vendors like Amontec and Tin Can Tools. In the case of Foxconn and their +Pirelli DP-L10 design, we can never know for certain, but it is highly plausible +that they weren't making a custom FT2232x-based JTAG adapter of their own like +we are doing, and instead had a passive adapter that connected their FFC +interface to some existing TI XDS JTAG adapter, likely via that very same 14-pin +interface. In that case the existing TI XDS JTAG adapter they were using needed +a target voltage reference pin, and so they included one in their custom FFC +interface. But our circumstances are different: we are making a custom +UART+JTAG adapter for reasons of our own, and because our custom adapter is +very specific to the Calypso, having our own on-board 2.8 V regulator is more +robust than depending on an I/O buffer supply from the target. + +2.6. Target connection interfaces + +2.6.1. Generic header interface + +Our FreeCalypso UART+JTAG adapter will feature two header connectors: a 14-pin +header in TI's pinout for JTAG, nEMU[1:0] and nTESTRESET, and a separate 3-pin +header for the UART. This header interface option will make it possible to use +our adapter with the FCDEV3B, with TI's D-Sample board (JTAG+company 14-pin +interface only) and even with hacked-up C1xx phones with little wires soldered +to JTAG test pads. As explained in section 2.3.2, always give explicit thought +as to whether pins 13 and 14 (nEMU0 and nEMU1) should be connected or not in +your application. + +The UART on FT2232D Channel B will be completely independent of JTAG and other +Channel A functions, and can be used as a completely generic data-leads-only +asynchronous serial interface at 2.8 V. + +2.6.2. FFC interface + +Our upcoming FreeCalypso handset boards will need to use an FFC interface for +development functions. At the very minimum this interface needs to connect the +Calypso's IrDA UART carrying RVTMUX, and do it in such a way that this serial +interface can be connected without applying a "charger present" condition to +the VRPC block in the Iota ABB - hence the need for an interface outside of the +handset's built-in USB-serial port. Furthermore, if we copy the FFC interface +from Foxconn's Pirelli DP-L10 design instead of inventing our own, we get not +only a UART channel, but also JTAG and nTESTRESET on the same interface. There +is very little need for JTAG in FreeCalypso, but it is certainly a nice-to-have. +Having the ability to drive nTESTRESET from the development host will also come +very useful: once we implement proper handset on/off logic in the firmware, +meaning that different switch-on causes will be treated like they should be in +a real handset, switch-on from nTESTRESET will become the development and +production boot mode. + +Our FFC interface is effectively defined by the unpopulated FFC connector +footprint and its wiring found in Pirelli DP-L10 phones. It is a 12-pin FFC +interface with 0.5 mm pitch, the unpopulated connector footprint on Pirelli's +PCB has pin numbers marked on the silk screen, and the pins are assigned as +follows: + +Pin Function +---------------- +1 V-IO rail +2 UART Rx (input to the target) +3 Iota nTESTRESET +4 JTAG TDI +5 JTAG TMS +6 JTAG TCK +7 UART Tx (output from the target) +8 JTAG TDO +9 unused +10 GND +11 unused +12 unused + +At one time we had a plan to add Calypso nEMU[1:0] signals to this interface by +putting them on the last two unused pins, but this addition has been rejected +for the time being: because we have no documentation for what these nEMU[1:0] +pins do and all we can do with them are reverse engineering experiments, these +signals should be kept out of handset products and limited to development boards +like FCDEV3B for the time being. + +There is, however, one critical aspect of this FFC interface which cannot be +recovered from the Pirelli DP-L10 artifacts and instead has to be defined anew: +the question of top vs. bottom orientation. Our decision process in this regard +begins with the availability of FFC jumpers, i.e., the flat flexible piece that +goes between the two boards. The FFC jumper version with same-side contacts is +readily available from Digi-Key as very inexpensive single pieces, but the +version with opposite-side contacts is only available with a prohibitely +expensive MOQ. Having settled on the FFC jumper with same-side contacts, we +are left with two options: have the contacts on both sides face upward, or have +them face downward. The decision between the two is completely arbitrary and +we have no way of knowing which way Foxconn had it back in their day, but we +have to decide one way or the other starting with the design of this adapter +board. The Mother's arbitrary decision is to have the contacts on both sides +of the FFC jumper face upward, meaning that: + +* The FFC connector on the FreeCalypso UART+JTAG Adapter board will need to be + the top-side contacts version. + +* If we are going to populate an FFC connector on a decased Pirelli motherboard + in order to exercise our adapter against that pre-existing target, the top- + side contacts version will need to be used. We'll need to do the same if we + make our own handset board on which the FFC connector is on the side with the + display and the main keypad buttons. + +* If we make our own handset board on which the FFC connector is on the bottom + side of the motherboard (the side opposite the display), which is the current + plan, the connector will need to be the bottom-side contacts version. + +Because pin 1 is on the left on the existing target board with the connector on +the top side (Pirelli DP-L10) and we are using the same-side jumper version that +flips the left/right orientation, pin 1 will need to be on the right in the +connector footprint definition on the adapter board.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/MCL Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,94 @@ +# Connectors + +J1: + description=USB connector, receptacle, mini-B + manufacturer=AMP/TE + manufacturer_part_number=1734035-2 + vendor=Digi-Key + vendor_part_number=A31727CT-ND + npins=9 # 5 actual pins + 4 mounting pads +# the datasheet with the PCB footprint drawing is at +# ftp.ifctf.org:/pub/GSM/part_datasheets/USB/ENG_CD_1734035_E1_C_1734035.pdf + +J2: + manufacturer=Hirose + manufacturer_part_number=FH12A-12S-0.5SH + description=FPC connector, 12 positions, top contacts + vendor=Digi-Key + vendor_part_number=HFK112CT-ND + footprint=FH12_12S_05SH_1R # pin 1 on the right + npins=14 # 12 + 2 mounting pads + +J3: + footprint=HEADER14_2 + description=Header, 0.100", dual row, 14 posts + manufacturer=Molex + manufacturer_part_number=0901310127 + vendor=Digi-Key + vendor_part_number=WM50035-14-ND + npins=14 + +J4: + footprint=JUMPER3 + description=Header, 0.100", single row, 3 posts + manufacturer=Molex + manufacturer_part_number=0901200123 + vendor=Digi-Key + vendor_part_number=WM8073-ND + npins=3 + +# ICs + +U1: + manufacturer=FTDI + device=FT2232D + description=USB to UART/JTAG/GPIO adapter IC + vendor=Digi-Key + vendor_part_number=768-1010-1-ND + npins=48 + +U2: + device=93C46 + description=Serial EEPROM, 64x16, SOIC-8 package + footprint=SO8 + npins=8 + +U3: + manufacturer=TI + device=TLV70033DDC + part=yes + description=LDO regulator, 3.3 V output, SOT-5 + footprint=file:TLV700xxDDC + npins=5 + +U4: + manufacturer=TI + device=TLV70028DDC + part=yes + description=LDO regulator, 2.8 V output, SOT-5 + footprint=file:TLV700xxDDC + npins=5 + +# buffer for driving outputs from the adapter +U5: + device=74LVC125A + manufacturer=NXP + manufacturer_part_number=74LVC125APW + description=Quad buffer IC, TSSOP14 package + npins=14 + +# buffer for receiving outputs from the target +U6: + device=74LVC2G125 + manufacturer=NXP + manufacturer_part_number=74LVC2G125DP + description=Dual buffer IC, TSSOP8 package + npins=8 + +# OD buffer for driving nTESTRESET +U7: + device=74LVC1G07 + manufacturer=NXP + manufacturer_part_number=74LVC1G07GM + description=Open drain buffer IC, SOT886 package + npins=6
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/Makefile Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,13 @@ +VSRCS= vsrc/FT2232D_block.v vsrc/FT2232D_chip.v vsrc/USB_block.v \ + vsrc/application_block.v vsrc/board.v vsrc/eeprom_93Cx6_16bit.v \ + vsrc/od_buffer.v vsrc/regulator_ic.v vsrc/regulator_with_caps.v \ + vsrc/target_if.v vsrc/usb_conn.v +NETS= sverp.unet + +all: ${NETS} + +sverp.unet: ${VSRCS} primitives Makefile + ueda-sverp -o $@ ${VSRCS} + +clean: + rm -f *.unet
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/primitives Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,28 @@ +/* + * This file defines the primitives to be instantiated from the structural + * Verilog source for the board: IC package types, basic components and + * subpackages to be mapped later in the MCL binding step. + */ + +resistor numpins 2; +capacitor numpins 2; +inductor numpins 2; + +/* IC packages */ +pkg_LQFP48 numpins 48; +pkg_XSON6 numpins 6; +pkg_5pin numpins 5; +pkg_8pin numpins 8; + +/* 74LVC125A/74LVC2G125 single buffer and common part subpackages */ +buffer_ic_slot mapped_pins (A, Y, nOE); +buffer_ic_common mapped_pins (Vcc, GND); + +/* crystal resonator */ +xtal_2pin_pkg numpins 2; + +/* connectors */ +header_3pin numpins 3; +header_14pin numpins 14; +conn_12pin_plus2 numpins 14; +conn_miniUSB_plus4 numpins 9;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/FT2232D_block.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,85 @@ +/* + * This module encapsulates the FT2232D chip and its immediate accessories: + * the oscillator crystal, the EEPROM, the AVCC filter and the cap on 3V3OUT. + */ + +module FT2232D_block (GND, VCC, VCCIOA, VCCIOB, + USBDP, USBDM, RESET, RSTOUT, PWREN, + ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB); + +input GND, VCC, VCCIOA, VCCIOB; + +inout USBDP, USBDM; + +input RESET; +output RSTOUT, PWREN; + +inout [7:0] ADBUS, BDBUS; +inout [3:0] ACBUS, BCBUS; +input SI_WUA, SI_WUB; + +/* FT2232D pins handled within this block */ + +wire EECS, EESK, EEDATA; +wire XTIN, XTOUT; +wire AVCC, FTDI_3V3; + +/* instantiate the FT2232D */ + +FT2232D_chip FT2232D (.GND(GND), + .AGND(GND), + .VCC(VCC), + .AVCC(AVCC), + .VCCIOA(VCCIOA), + .VCCIOB(VCCIOB), + .OUT_3V3(FTDI_3V3), + .USBDP(USBDP), + .USBDM(USBDM), + .EECS(EECS), + .EESK(EESK), + .EEDATA(EEDATA), + .RESET(RESET), + .RSTOUT(RSTOUT), + .TEST(GND), + .PWREN(PWREN), + .XTIN(XTIN), + .XTOUT(XTOUT), + .ADBUS(ADBUS), + .ACBUS(ACBUS), + .SI_WUA(SI_WUA), + .BDBUS(BDBUS), + .BCBUS(BCBUS), + .SI_WUB(SI_WUB) + ); + +/* AVCC filter */ + +resistor AVCC_filter_R (VCC, AVCC); +capacitor AVCC_cap (AVCC, GND); + +/* 3V3OUT */ + +capacitor FTDI_3V3_cap (FTDI_3V3, GND); + +/* crystal oscillator */ + +xtal_2pin_pkg xtal (XTIN, XTOUT); +capacitor XTIN_cap (XTIN, GND); +capacitor XTOUT_cap (XTOUT, GND); + +/* serial EEPROM */ + +wire EEPROM_DOUT; + +eeprom_93Cx6_16bit eeprom (.GND(GND), + .VCC(VCC), + .CS(EECS), + .SK(EESK), + .DIN(EEDATA), + .DOUT(EEPROM_DOUT) + ); + +resistor DOUT_series_R (EEPROM_DOUT, EEDATA); +resistor DOUT_pullup_R (EEPROM_DOUT, VCC); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/FT2232D_chip.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,78 @@ +/* + * This module encapsulates the FT2232D chip and its pinout. + */ + +module FT2232D_chip (GND, AGND, VCC, AVCC, VCCIOA, VCCIOB, OUT_3V3, + USBDP, USBDM, EECS, EESK, EEDATA, RESET, RSTOUT, TEST, PWREN, + XTIN, XTOUT, ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB); + +input GND, AGND, VCC, AVCC, VCCIOA, VCCIOB; +output OUT_3V3; + +inout USBDP, USBDM; +output EECS, EESK; +inout EEDATA; + +input RESET, TEST; +output RSTOUT, PWREN; + +input XTIN; +output XTOUT; + +inout [7:0] ADBUS, BDBUS; +inout [3:0] ACBUS, BCBUS; +input SI_WUA, SI_WUB; + +/* instantiate the package; the mapping of signals to pins is defined here */ + +pkg_LQFP48 pkg (.pin_1(EESK), + .pin_2(EEDATA), + .pin_3(VCC), + .pin_4(RESET), + .pin_5(RSTOUT), + .pin_6(OUT_3V3), + .pin_7(USBDP), + .pin_8(USBDM), + .pin_9(GND), + .pin_10(SI_WUA), + .pin_11(ACBUS[3]), + .pin_12(ACBUS[2]), + .pin_13(ACBUS[1]), + .pin_14(VCCIOA), + .pin_15(ACBUS[0]), + .pin_16(ADBUS[7]), + .pin_17(ADBUS[6]), + .pin_18(GND), + .pin_19(ADBUS[5]), + .pin_20(ADBUS[4]), + .pin_21(ADBUS[3]), + .pin_22(ADBUS[2]), + .pin_23(ADBUS[1]), + .pin_24(ADBUS[0]), + .pin_25(GND), + .pin_26(SI_WUB), + .pin_27(BCBUS[3]), + .pin_28(BCBUS[2]), + .pin_29(BCBUS[1]), + .pin_30(BCBUS[0]), + .pin_31(VCCIOB), + .pin_32(BDBUS[7]), + .pin_33(BDBUS[6]), + .pin_34(GND), + .pin_35(BDBUS[5]), + .pin_36(BDBUS[4]), + .pin_37(BDBUS[3]), + .pin_38(BDBUS[2]), + .pin_39(BDBUS[1]), + .pin_40(BDBUS[0]), + .pin_41(PWREN), + .pin_42(VCC), + .pin_43(XTIN), + .pin_44(XTOUT), + .pin_45(AGND), + .pin_46(AVCC), + .pin_47(TEST), + .pin_48(EECS) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/USB_block.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,67 @@ +/* + * This module encapsulates the USB connector, the FT2232D block and + * the glue components between them. + */ + +module USB_block (GND, P_5V, VCCIOA, VCCIOB, + ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB, PWREN); + +output GND, P_5V; + +input VCCIOA, VCCIOB; +inout [7:0] ADBUS, BDBUS; +inout [3:0] ACBUS, BCBUS; +input SI_WUA, SI_WUB; +output PWREN; + +/* interconnecting wires */ + +wire VBUS; +wire DM_connector_side, DM_chip_side; +wire DP_connector_side, DP_chip_side; +wire RSTOUT; + +usb_conn conn (.GND(GND), + .VBUS(VBUS), + .Dminus(DM_connector_side), + .Dplus(DP_connector_side), + .ID() /* no connect */ + ); + +/* ferrite bead on the power supply */ + +inductor VBUS_ferrite (VBUS, P_5V); + +/* series resistors on USB data lines */ + +resistor DM_series_R (DM_connector_side, DM_chip_side); +resistor DP_series_R (DP_connector_side, DP_chip_side); + +/* we can now bring in the FT2232D block */ + +FT2232D_block FT2232D (.GND(GND), + .VCC(P_5V), + .VCCIOA(VCCIOA), + .VCCIOB(VCCIOB), + .USBDP(DP_chip_side), + .USBDM(DM_chip_side), + .RESET(P_5V), + .RSTOUT(RSTOUT), + .PWREN(PWREN), + .ADBUS(ADBUS), + .ACBUS(ACBUS), + .SI_WUA(SI_WUA), + .BDBUS(BDBUS), + .BCBUS(BCBUS), + .SI_WUB(SI_WUB) + ); + +resistor DP_pullup_R (DP_chip_side, RSTOUT); + +/* power bypass caps */ + +capacitor VBUS_in_cap (VBUS, GND); +capacitor P_5V_cap (P_5V, GND); +capacitor P_5V_cap2 (P_5V, GND); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/application_block.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,66 @@ +/* + * This module encapsulates the application function of our board: + * going from FT2232D to target interfaces. + */ + +module application_block (GND, P_3V3, P_2V8, ADBUS, ACBUS, BDBUS); + +input GND, P_3V3, P_2V8; + +inout [7:0] ADBUS, BDBUS; +inout [3:0] ACBUS; + +/* target interface wires */ + +wire JTAG_TCK, JTAG_TDI, JTAG_TDO, JTAG_TMS; +wire nTESTRESET; +wire UART_TxD, UART_RxD; + +target_if target_if ( .GND(GND), + .JTAG_TCK(JTAG_TCK), + .JTAG_TDI(JTAG_TDI), + .JTAG_TDO(JTAG_TDO), + .JTAG_TMS(JTAG_TMS), + .nTESTRESET(nTESTRESET), + .nEMU[0](ACBUS[2]), + .nEMU[1](ACBUS[3]), + .UART_TxD(UART_TxD), + .UART_RxD(UART_RxD) + ); + +/* output buffers */ + +buffer_ic_common output_buf_common (.Vcc(P_2V8), .GND(GND)); +capacitor output_buf_bypass_cap (P_2V8, GND); + +buffer_ic_slot buf_JTAG_TCK (.A(ADBUS[0]), .Y(JTAG_TCK), .nOE(ADBUS[5])); +buffer_ic_slot buf_JTAG_TDI (.A(ADBUS[1]), .Y(JTAG_TDI), .nOE(ADBUS[5])); +buffer_ic_slot buf_JTAG_TMS (.A(ADBUS[3]), .Y(JTAG_TMS), .nOE(ADBUS[5])); + +buffer_ic_slot buf_UART_TxD (.A(BDBUS[0]), .Y(UART_TxD), .nOE(GND)); + +/* input buffers */ + +buffer_ic_common input_buf_common (.Vcc(P_3V3), .GND(GND)); +capacitor input_buf_bypass_cap (P_3V3, GND); + +buffer_ic_slot buf_JTAG_TDO (.A(JTAG_TDO), .Y(ADBUS[2]), .nOE(ADBUS[6])); +buffer_ic_slot buf_UART_RxD (.A(UART_RxD), .Y(BDBUS[1]), .nOE(GND)); + +/* input pull-up resistors */ + +resistor JTAG_TDO_pullup (JTAG_TDO, P_2V8); +resistor UART_RxD_pullup (UART_RxD, P_2V8); + +/* reset signal driver */ + +od_buffer reset_driver (.GND(GND), .Vcc(P_3V3), .A(ADBUS[7]), .Y(nTESTRESET)); +capacitor reset_driver_bypass_cap (P_3V3, GND); + +/* pull-up resistors on control lines */ + +resistor ADBUS5_pullup (ADBUS[5], P_3V3); +resistor ADBUS6_pullup (ADBUS[6], P_3V3); +resistor ADBUS7_pullup (ADBUS[7], P_3V3); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/board.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,32 @@ +module board (); + +wire GND, P_5V, P_3V3, P_2V8; + +wire [7:0] ADBUS, BDBUS; +wire [3:0] ACBUS, BCBUS; + +USB_block usb ( .GND(GND), + .P_5V(P_5V), + .VCCIOA(P_3V3), + .VCCIOB(P_3V3), + .ADBUS(ADBUS), + .ACBUS(ACBUS), + .SI_WUA(P_3V3), + .BDBUS(BDBUS), + .BCBUS(BCBUS), + .SI_WUB(P_3V3), + .PWREN() /* no connect */ + ); + +regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3)); +regulator_with_caps reg_2V8 (.GND(GND), .IN(P_5V), .OUT(P_2V8)); + +application_block app ( .GND(GND), + .P_3V3(P_3V3), + .P_2V8(P_2V8), + .ADBUS(ADBUS), + .ACBUS(ACBUS), + .BDBUS(BDBUS) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/eeprom_93Cx6_16bit.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,19 @@ +module eeprom_93Cx6_16bit (GND, VCC, CS, SK, DIN, DOUT); + +input GND, VCC; +input CS, SK, DIN; +output DOUT; + +/* instantiate the package; the mapping of signals to pins is defined here */ + +pkg_8pin pkg (.pin_1(CS), + .pin_2(SK), + .pin_3(DIN), + .pin_4(DOUT), + .pin_5(GND), + .pin_6(VCC), /* ORG input on some 93Cx6 variants */ + .pin_7(), /* no connect */ + .pin_8(VCC) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/od_buffer.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,17 @@ +module od_buffer (GND, Vcc, A, Y); + +input GND, Vcc; +input A; +output Y; + +/* instantiate the package; the mapping of signals to pins is defined here */ + +pkg_XSON6 pkg (.pin_1(), /* no connect */ + .pin_2(A), + .pin_3(GND), + .pin_4(Y), + .pin_5(), /* no connect */ + .pin_6(Vcc) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/regulator_ic.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,13 @@ +module regulator_ic (IN, OUT, GND, EN); + +input IN, GND, EN; +output OUT; + +pkg_5pin pkg ( .pin_1(IN), + .pin_2(GND), + .pin_3(EN), + .pin_4(), /* no connect */ + .pin_5(OUT) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/regulator_with_caps.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,15 @@ +module regulator_with_caps (GND, IN, OUT); + +input GND, IN; +output OUT; + +regulator_ic reg (.IN(IN), + .OUT(OUT), + .GND(GND), + .EN(IN) + ); + +capacitor input_cap (IN, GND); +capacitor output_cap (OUT, GND); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/target_if.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,59 @@ +/* This module captures our target interfaces. */ + +module target_if (GND, JTAG_TCK, JTAG_TDI, JTAG_TDO, JTAG_TMS, nTESTRESET, + nEMU, UART_TxD, UART_RxD); + +input GND; + +input JTAG_TCK, JTAG_TDI, JTAG_TMS; +output JTAG_TDO, nTESTRESET; +inout [1:0] nEMU; + +input UART_TxD; +output UART_RxD; + +/* TI JTAG header */ + +header_14pin ti_jtag_hdr (.pin_1(JTAG_TMS), + .pin_2(nTESTRESET), + .pin_3(JTAG_TDI), + .pin_4(), /* no connect */ + .pin_5(), /* no connect */ + .pin_6(), /* no connect */ + .pin_7(JTAG_TDO), + .pin_8(GND), + .pin_9(), /* no connect */ + .pin_10(GND), + .pin_11(JTAG_TCK), + .pin_12(GND), + .pin_13(nEMU[0]), + .pin_14(nEMU[1]) + ); + +/* 3-pin UART header */ + +header_3pin uart_hdr ( .pin_1(GND), + .pin_2(UART_RxD), + .pin_3(UART_TxD) + ); + +/* FFC connector for FreeCalypso handset boards */ + +conn_12pin_plus2 ffc_conn (.pin_1(), /* no connect */ + .pin_2(UART_TxD), + .pin_3(nTESTRESET), + .pin_4(JTAG_TDI), + .pin_5(JTAG_TMS), + .pin_6(JTAG_TCK), + .pin_7(UART_RxD), + .pin_8(JTAG_TDO), + .pin_9(), /* no connect */ + .pin_10(GND), + .pin_11(), /* no connect */ + .pin_12(), /* no connect */ + /* mounting pads */ + .pin_13(GND), + .pin_14(GND) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fc-uja/schem+bom/vsrc/usb_conn.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,21 @@ +/* + * This module captures the mini-USB connector. + */ + +module usb_conn (GND, VBUS, Dminus, Dplus, ID); + +inout GND, VBUS, Dminus, Dplus, ID; + +conn_miniUSB_plus4 conn (.pin_1(VBUS), + .pin_2(Dminus), + .pin_3(Dplus), + .pin_4(ID), + .pin_5(GND), + /* mounting pads */ + .pin_6(GND), + .pin_7(GND), + .pin_8(GND), + .pin_9(GND) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lcdtest1/README Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,4 @@ +This board is an ad hoc adapter for connecting a HaoRan HT020K1QC36S LCD +to an FT2232D board used in the MCU host bus emulation mode. The objective +here is only to connect the LCD for picture quality testing - no mechanical +prototyping for the handset is done on this board.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lcdtest1/pcb/Makefile Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,25 @@ +ALL= gerbers.zip lcdtest1_pcb.ps lcdtest1_pcb.pdf +EXPARG= --fab-author 'Harhan Engineering Co.' + +all: ${ALL} + +.SUFFIXES: .ps .pdf + +.ps.pdf: + ps2pdf $*.ps + +lcdtest1_pcb.ps: lcdtest1.pcb + pcb -x ps --psfile $@ ${EXPARG} lcdtest1.pcb + +gerbers.d: lcdtest1.pcb + -rm -rf $@ + mkdir $@ + pcb -x gerber --gerberfile gerbers.d/lcdtest1 ${EXPARG} lcdtest1.pcb + +gerbers.zip: gerbers.d + -rm -f $@ + cd gerbers.d; zip ../gerbers.zip * + +clean: + rm -f *.ps *.pdf lcdtest1.pcb- + rm -rf gerbers.*
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lcdtest1/pcb/lcdtest1.pcb Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,1190 @@ +# release: pcb 20140316 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20091103] + +PCB["" 2500.00mil 1800.00mil] + +Grid[1000.000000 0.0000 0.0000 0] +PolyArea[3100.006200] +Thermal[0.500000] +DRC[6.00mil 6.00mil 6.00mil 5.00mil 15.00mil 6.00mil] +Flags("nameonpcb,uniquename,clearnew,snappin") +Groups("1,c:2,s:3:4:5:6:7:8") +Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,60.00mil,35.00mil,10.00mil:Fat,40.00mil,60.00mil,35.00mil,10.00mil:Skinny,6.00mil,24.02mil,11.81mil,6.00mil"] + +Symbol[' ' 18.00mil] +( +) +Symbol['!' 12.00mil] +( + SymbolLine[0.0000 45.00mil 0.0000 50.00mil 8.00mil] + SymbolLine[0.0000 10.00mil 0.0000 35.00mil 8.00mil] +) +Symbol['"' 12.00mil] +( + SymbolLine[0.0000 10.00mil 0.0000 20.00mil 8.00mil] + SymbolLine[10.00mil 10.00mil 10.00mil 20.00mil 8.00mil] +) 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Line[35.8940mm 12.8540mm 35.8940mm 11.0960mm 10.00mil 20.00mil "clearline"] + Line[35.8940mm 11.0960mm 1420.00mil 430.00mil 10.00mil 20.00mil "clearline"] + Line[36.3940mm 12.8540mm 36.3940mm 11.1040mm 10.00mil 20.00mil "clearline"] + Line[36.3940mm 11.1040mm 1440.00mil 430.00mil 10.00mil 20.00mil "clearline"] + Line[36.8940mm 12.8540mm 36.8940mm 11.1120mm 10.00mil 20.00mil "clearline"] + Line[36.8940mm 11.1120mm 1460.00mil 430.00mil 10.00mil 20.00mil "clearline"] + Line[42.7940mm 9.6040mm 40.3380mm 9.6040mm 10.00mil 20.00mil "clearline"] + Line[40.3380mm 9.6040mm 1560.00mil 350.00mil 10.00mil 20.00mil "clearline"] + Line[26.8940mm 12.8540mm 26.8940mm 15.0160mm 10.00mil 20.00mil "clearline"] + Line[26.8940mm 15.0160mm 1050.00mil 600.00mil 10.00mil 20.00mil "clearline"] + Line[930.00mil 600.00mil 1050.00mil 600.00mil 10.00mil 20.00mil "clearline"] +) +Layer(2 "solder") +( + Polygon("clearpoly") + ( + [100.00mil 100.00mil] [2400.00mil 100.00mil] [2400.00mil 1700.00mil] [100.00mil 1700.00mil] + ) +) +Layer(3 "GND") +( +) +Layer(4 "power") +( +) +Layer(5 "signal1") +( +) +Layer(6 "signal2") +( +) +Layer(7 "signal3") +( +) +Layer(8 "signal4") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( + Text[400.00mil 970.00mil 0 100 "GND" "clearline"] + Text[410.00mil 1450.00mil 0 100 "GND" "clearline"] + Text[410.00mil 870.00mil 0 100 "5V" "clearline"] + Text[410.00mil 1350.00mil 0 100 "3.3V" "clearline"] + Text[830.00mil 1490.00mil 3 100 "RESET" "clearline"] + Text[930.00mil 1500.00mil 3 100 "CS" "clearline"] + Text[1030.00mil 1500.00mil 3 100 "RS" "clearline"] + Text[1120.00mil 1500.00mil 3 100 "WR" "clearline"] + Text[1230.00mil 1500.00mil 3 100 "RD" "clearline"] + Text[1330.00mil 1500.00mil 3 100 "DB0" "clearline"] + Text[1430.00mil 1500.00mil 3 100 "DB1" "clearline"] + Text[1530.00mil 1500.00mil 3 100 "DB2" "clearline"] + Text[1630.00mil 1500.00mil 3 100 "DB3" "clearline"] + Text[1730.00mil 1500.00mil 3 100 "DB4" "clearline"] + Text[1830.00mil 1500.00mil 3 100 "DB5" "clearline"] + Text[1930.00mil 1500.00mil 3 100 "DB6" "clearline"] + Text[2030.00mil 1500.00mil 3 100 "DB7" "clearline"] + Text[2200.00mil 1300.00mil 1 100 "HT020K1QC36S LCD Test Board" "clearline"] +) +NetList() +( + Net("CS" "(unknown)") + ( + Connect("J1-23") + Connect("J2-12") + ) + Net("DB[0]" "(unknown)") + ( + Connect("J1-8") + Connect("J2-8") + ) + Net("DB[1]" "(unknown)") + ( + Connect("J1-7") + Connect("J2-7") + ) + Net("DB[2]" "(unknown)") + ( + Connect("J1-6") + Connect("J2-6") + ) + Net("DB[3]" "(unknown)") + ( + Connect("J1-5") + Connect("J2-5") + ) + Net("DB[4]" "(unknown)") + ( + Connect("J1-4") + Connect("J2-4") + ) + Net("DB[5]" "(unknown)") + ( + Connect("J1-3") + Connect("J2-3") + ) + Net("DB[6]" "(unknown)") + ( + Connect("J1-2") + Connect("J2-2") + ) + Net("DB[7]" "(unknown)") + ( + Connect("J1-1") + Connect("J2-1") + ) + Net("GND" "(unknown)") + ( + Connect("J1-9") + Connect("J1-10") + Connect("J1-11") + Connect("J1-12") + Connect("J1-13") + Connect("J1-14") + Connect("J1-15") + Connect("J1-16") + Connect("J1-17") + Connect("J1-26") + Connect("J1-37") + Connect("J1-38") + Connect("J3-2") + Connect("J4-2") + Connect("R1-2") + Connect("R2-2") + Connect("R3-2") + ) + Net("LEDK[1]" "(unknown)") + ( + Connect("J1-28") + Connect("R1-1") + ) + Net("LEDK[2]" "(unknown)") + ( + Connect("J1-29") + Connect("R2-1") + ) + Net("LEDK[3]" "(unknown)") + ( + Connect("J1-30") + Connect("R3-1") + ) + Net("P_3V3" "(unknown)") + ( + Connect("J1-18") + Connect("J1-19") + Connect("J1-25") + Connect("J4-1") + ) + Net("P_5V" "(unknown)") + ( + Connect("J1-27") + Connect("J3-1") + ) + Net("RD" "(unknown)") + ( + Connect("J1-20") + Connect("J2-9") + ) + Net("RESET" "(unknown)") + ( + Connect("J1-24") + Connect("J2-13") + ) + Net("RS" "(unknown)") + ( + Connect("J1-22") + Connect("J2-11") + ) + Net("WR" "(unknown)") + ( + Connect("J1-21") + Connect("J2-10") + ) +)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lcdtest1/schem+bom/MCL Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,62 @@ +# Connectors + +J1: + hier=fpc + manufacturer=Hirose + manufacturer_part_number=FH12-36S-0.5SH + description=FPC connector, 36 positions + vendor=Digi-Key + vendor_part_number=HFJ136CT-ND + footprint=FH12_36S_05SH_1L # pin 1 on the left + npins=38 # 36 + 2 mounting pads + +J2: + hier=data + description=Header, 0.100", single row, 13 posts + source=Breakaway from scrap + part=yes + footprint=JUMPER13 + npins=13 + +part header-2pin: + footprint=JUMPER2 + description=Header, 0.100", 2 posts + manufacturer=Molex + manufacturer_part_number=0901200122 + vendor=Digi-Key + vendor_part_number=WM8072-ND + npins=2 + +J3: + # 5V power + hier=pwr_5V + part=header-2pin + +J4: + # 3.3V power + hier=pwr_3V3 + part=header-2pin + +# Resistors + +part led-series-resistor: + footprint=0603 + value=120R + description=Chip resistor, 120 ohm, 1%, 0603 + manufacturer=Vishay Dale + manufacturer_part_number=CRCW0603120RFKEA + vendor=Digi-Key + vendor_part_number=541-120HCT-ND + npins=2 + +R1: + hier=R1 + part=led-series-resistor + +R2: + hier=R2 + part=led-series-resistor + +R3: + hier=R3 + part=led-series-resistor
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lcdtest1/schem+bom/Makefile Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,28 @@ +BOMS= tallied-bom.txt tallied-bom.csv comptab.txt +NETS= sverp.unet bound.unet pcb-netlist.txt + +all: ${BOMS} ${NETS} elements.pcb + +sverp.unet: schem.v primitives + ueda-sverp -o $@ schem.v + +bound.unet: MCL sverp.unet + unet-bind -c sverp.unet $@ + +pcb-netlist.txt: bound.unet + unet2pcb bound.unet $@ + +tallied-bom.txt: MCL + ueda-mkbom -cr > $@ + +tallied-bom.csv: MCL + ueda-csvbom > $@ + +comptab.txt: MCL + ueda-shortbom > $@ + +elements.pcb: MCL + ueda-getfps -ch | ueda-runm4 > $@ + +clean: + rm -f *.unet *.txt *.csv errs elements.pcb
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lcdtest1/schem+bom/primitives Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,8 @@ +/* connectors */ +header_2pin numpins 2; +header_13pin numpins 13; +conn_36pin numpins 36; +conn_36pin_plus2 numpins 38; + +/* passives */ +resistor numpins 2;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/lcdtest1/schem+bom/schem.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,77 @@ +module board (); + +wire GND, P_5V, P_3V3; +wire [7:0] DB; +wire RD, WR, RS, CS, RESET; +wire [1:3] LEDK; + +conn_36pin_plus2 fpc ( .pin_1(DB[7]), + .pin_2(DB[6]), + .pin_3(DB[5]), + .pin_4(DB[4]), + .pin_5(DB[3]), + .pin_6(DB[2]), + .pin_7(DB[1]), + .pin_8(DB[0]), + .pin_9(GND), + .pin_10(GND), /* unused lower data bus */ + .pin_11(GND), /* unused lower data bus */ + .pin_12(GND), /* unused lower data bus */ + .pin_13(GND), /* unused lower data bus */ + .pin_14(GND), /* unused lower data bus */ + .pin_15(GND), /* unused lower data bus */ + .pin_16(GND), /* unused lower data bus */ + .pin_17(GND), /* unused lower data bus */ + .pin_18(P_3V3), /* IOVCC */ + .pin_19(P_3V3), /* VCI */ + .pin_20(RD), + .pin_21(WR), + .pin_22(RS), + .pin_23(CS), + .pin_24(RESET), + .pin_25(P_3V3), /* IM0 tied high */ + .pin_26(GND), + .pin_27(P_5V), /* LEDA */ + .pin_28(LEDK[1]), + .pin_29(LEDK[2]), + .pin_30(LEDK[3]), + /* the remaining pins are NC */ + .pin_31(), + .pin_32(), + .pin_33(), + .pin_34(), + .pin_35(), + .pin_36(), + /* ground the two mounting pads */ + .pin_37(GND), + .pin_38(GND) + ); + +resistor R1 (LEDK[1], GND); +resistor R2 (LEDK[2], GND); +resistor R3 (LEDK[3], GND); + +header_13pin data (.pin_1(DB[7]), + .pin_2(DB[6]), + .pin_3(DB[5]), + .pin_4(DB[4]), + .pin_5(DB[3]), + .pin_6(DB[2]), + .pin_7(DB[1]), + .pin_8(DB[0]), + .pin_9(RD), + .pin_10(WR), + .pin_11(RS), + .pin_12(CS), + .pin_13(RESET) + ); + +header_2pin pwr_5V (.pin_1(P_5V), + .pin_2(GND) + ); + +header_2pin pwr_3V3 (.pin_1(P_3V3), + .pin_2(GND) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/README Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,59 @@ +MMTB1 is a Modem Module Test Board intended for testing and exercising Huawei +GTM900 and FreeCalypso FCM40 modem modules. Specifically, the following two +usages are envisioned: + +1) When MMTB1 is first built, it will be used with GTM900-B and possibly with + GTM900-P modules. MMTB1 will allow the combination of FC firmware on GTM900 + hw to be exercised properly, and then the combination of MMTB1+GTM900 can be + officially recommended to community members seeking to play with FreeCalypso + fw. + +2) When FCM40 gets built much later, MMTB1 will be used for production testing + and bring-up of first FCM40 modules. MMTB1 is more GTM900-oriented and + therefore won't be ideal for exercising FCM40 modules, but it will be + sufficient for basic bring-up, missing only microphone and MCSI interfaces. + Once that milestone is passed, a new MMTB version will be created + specifically for FCM40 functional demonstration. + +MMTB1 is going to break out the FPC interface of GTM900 as follows: + +* The power input connector will be the same as on FCDEV3B. + +* The two Calypso UARTs will be brought out to a 10-pin header in the same + pinout as on FCDEV3B, with GPIOs 2 & 3 (DCD and DTR) brought to the two pins + which are unused and unconnected on FCDEV3B. + +* PWON and RESET pushbuttons will be provided on MMTB1 just like on FCDEV3B, as + well as a green power-on LED. The LED will be controlled by the Vio output + coming out of the modem module, but without loading the Vio rail itself, + using raw VBAT and the same MOSFET circuit as on FCDEV3B. + +* There will be a SIM socket on the MMTB1 itself. + +* There will be two 2-pin headers for analog audio, one for the earpiece + speaker and one for the microphone, connected to the corresponding GTM900 + interface pins. + +The following GTM900 interfaces will NOT be brought out or exercised in any way: + +* ADIN1 (general-purpose ADC) connection on pin 14; +* GPIO1 connection (DSR output) on pin 16; +* GPIO0 connection (RI output) on pin 17; +* Vbackup connection on pin 30; +* LPG output on pin 32; +* AUXO secondary audio output on pins 33 & 34; +* AUXI secondary audio input on pins 39 & 40. + +These interfaces have been omitted because they are not essential for the +intended application of exercising FreeCalypso fw on GTM900 hw, because I am +lazy (not interested in doing more PCB layout work than I have to) and because +I couldn't find a suitable MOSFET to implement another LED circuit for LPG. + +No pull-up or pull-down resistors are provided on UART inputs to the Calypso, +including GPIO3 serving as the DTR input: I will always have all of the UART +signals connected to an FT2232x dual UART adapter (PLDkit FT2232C/D breakout +boards at first, then later our own DUART28) by way of a custom-crimped cable +that mates with the 10-pin header as a solid piece, leaving no possibility of +any UART signals being left unconnected. If anyone does not like this +arrangement, feel free to make your own alternative GTM900 breakout/interface +board.
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/pcb/mmtb1.pcb Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,1402 @@ +# release: pcb 20140316 + +# To read pcb files, the pcb version (or the git source date) must be >= the file version +FileVersion[20091103] + +PCB["" 3000.00mil 2500.00mil] + +Grid[500.000000 0.0000 0.0000 0] +PolyArea[3100.006200] +Thermal[0.500000] +DRC[10.00mil 10.00mil 10.00mil 5.00mil 15.00mil 10.00mil] +Flags("nameonpcb,uniquename,clearnew,snappin") +Groups("1,c:2,s:3:4:5:6:7:8") +Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,60.00mil,35.00mil,10.00mil:Fat,60.00mil,60.00mil,35.00mil,10.00mil:Skinny,6.00mil,24.02mil,11.81mil,6.00mil"] + +Symbol[' ' 18.00mil] +( +) +Symbol['!' 12.00mil] +( + SymbolLine[0.0000 45.00mil 0.0000 50.00mil 8.00mil] + SymbolLine[0.0000 10.00mil 0.0000 35.00mil 8.00mil] +) +Symbol['"' 12.00mil] +( + SymbolLine[0.0000 10.00mil 0.0000 20.00mil 8.00mil] + SymbolLine[10.00mil 10.00mil 10.00mil 20.00mil 8.00mil] +) +Symbol['#' 12.00mil] +( + SymbolLine[0.0000 35.00mil 20.00mil 35.00mil 8.00mil] + SymbolLine[0.0000 25.00mil 20.00mil 25.00mil 8.00mil] + SymbolLine[15.00mil 20.00mil 15.00mil 40.00mil 8.00mil] + SymbolLine[5.00mil 20.00mil 5.00mil 40.00mil 8.00mil] +) +Symbol['$' 12.00mil] +( + SymbolLine[15.00mil 15.00mil 20.00mil 20.00mil 8.00mil] + SymbolLine[5.00mil 15.00mil 15.00mil 15.00mil 8.00mil] + SymbolLine[0.0000 20.00mil 5.00mil 15.00mil 8.00mil] + SymbolLine[0.0000 20.00mil 0.0000 25.00mil 8.00mil] + SymbolLine[0.0000 25.00mil 5.00mil 30.00mil 8.00mil] + SymbolLine[5.00mil 30.00mil 15.00mil 30.00mil 8.00mil] + SymbolLine[15.00mil 30.00mil 20.00mil 35.00mil 8.00mil] + SymbolLine[20.00mil 35.00mil 20.00mil 40.00mil 8.00mil] + SymbolLine[15.00mil 45.00mil 20.00mil 40.00mil 8.00mil] + SymbolLine[5.00mil 45.00mil 15.00mil 45.00mil 8.00mil] + SymbolLine[0.0000 40.00mil 5.00mil 45.00mil 8.00mil] + SymbolLine[10.00mil 10.00mil 10.00mil 50.00mil 8.00mil] +) +Symbol['%' 12.00mil] +( + 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+ Line[745.00mil 2150.00mil 840.00mil 2150.00mil 10.00mil 20.00mil ""] + Line[865.00mil 2125.00mil 840.00mil 2150.00mil 10.00mil 20.00mil ""] + Line[6.0050mm 35.2680mm 6.0050mm 57.5690mm 10.00mil 20.00mil "clearline"] + Line[10.5050mm 35.2680mm 10.5050mm 43.2180mm 10.00mil 20.00mil "clearline"] + Line[10.5050mm 49.6190mm 10.5050mm 57.5690mm 10.00mil 20.00mil "clearline"] + Line[2070.00mil 400.00mil 2330.00mil 400.00mil 25.00mil 20.00mil "clearline"] + Line[48.3480mm 395.00mil 51.1510mm 395.00mil 25.00mil 20.00mil "clearline"] + Line[51.1510mm 395.00mil 51.2780mm 400.00mil 25.00mil 20.00mil "clearline"] + Line[1835.00mil 530.00mil 1835.00mil 10.0720mm 25.00mil 20.00mil "clearline"] + Line[47.1090mm 14.8620mm 51.0510mm 14.8620mm 25.00mil 20.00mil "clearline"] + Line[51.0510mm 14.8620mm 2010.00mil 585.00mil 25.00mil 20.00mil "clearline"] + Line[68.1720mm 29.0980mm 65.9280mm 29.0980mm 10.00mil 20.00mil "clearline"] + Line[65.9280mm 29.0980mm 2595.00mil 1145.00mil 10.00mil 20.00mil "clearline"] + Line[68.1720mm 37.0980mm 65.9270mm 37.0980mm 10.00mil 20.00mil "clearline"] + Line[65.9270mm 37.0980mm 2595.00mil 1460.00mil 10.00mil 20.00mil "clearline"] + Line[68.1720mm 36.0980mm 71.3440mm 36.0980mm 10.00mil 20.00mil "clearline"] + Line[71.3440mm 36.0980mm 2810.00mil 1420.00mil 10.00mil 20.00mil "clearline"] + Line[2810.00mil 36.0980mm 2810.00mil 43.4500mm 10.00mil 20.00mil "clearline"] + Line[2810.00mil 43.4500mm 71.4220mm 43.4980mm 10.00mil 20.00mil "clearline"] + Line[10.5050mm 43.3430mm 14.5690mm 43.3430mm 10.00mil 20.00mil "clearline"] + Line[14.5690mm 43.3430mm 575.00mil 1705.00mil 10.00mil 20.00mil "clearline"] + Line[10.5050mm 49.6190mm 14.5670mm 49.6190mm 10.00mil 20.00mil "clearline"] + Line[14.5670mm 49.6190mm 575.00mil 1955.00mil 10.00mil 20.00mil "clearline"] + Line[1290.00mil 2230.00mil 36.1040mm 2230.00mil 25.00mil 20.00mil "clearline"] + Line[36.1040mm 2230.00mil 38.3900mm 2140.00mil 25.00mil 20.00mil "clearline"] + Line[745.00mil 55.9100mm 19.7150mm 55.9100mm 10.00mil 20.00mil "clearline"] + Line[19.7150mm 55.9100mm 815.00mil 2240.00mil 10.00mil 20.00mil "clearline"] + Line[815.00mil 2240.00mil 1280.00mil 2240.00mil 10.00mil 20.00mil "clearline"] + Line[1280.00mil 2240.00mil 1290.00mil 2230.00mil 10.00mil 20.00mil "clearline"] + Line[25.9200mm 58.3360mm 31.0720mm 58.3360mm 10.00mil 20.00mil "clearline"] + Line[31.0720mm 58.3360mm 1290.00mil 2230.00mil 10.00mil 20.00mil "clearline"] + Line[25.9200mm 41.1760mm 29.8170mm 41.1760mm 10.00mil 20.00mil "clearline"] + Line[29.8170mm 41.1760mm 1175.00mil 1620.00mil 10.00mil 20.00mil "clearline"] + Polygon("clearpoly") + ( + [2560.00mil 800.00mil] [2625.00mil 800.00mil] [2625.00mil 955.00mil] [2560.00mil 955.00mil] + ) +) +Layer(2 "solder") +( + Line[2590.00mil 1465.00mil 2595.00mil 1460.00mil 10.00mil 20.00mil "clearline"] + Line[575.00mil 1955.00mil 1320.00mil 1955.00mil 10.00mil 20.00mil "clearline"] + Line[1320.00mil 1955.00mil 1855.00mil 1420.00mil 10.00mil 20.00mil "clearline"] + Line[1855.00mil 1420.00mil 2555.00mil 1420.00mil 10.00mil 20.00mil "clearline"] + Line[2555.00mil 1420.00mil 2595.00mil 1460.00mil 10.00mil 20.00mil "clearline"] + Line[575.00mil 1705.00mil 1430.00mil 1705.00mil 10.00mil 20.00mil "clearline"] + Line[1430.00mil 1705.00mil 1990.00mil 1145.00mil 10.00mil 20.00mil "clearline"] + Line[1990.00mil 1145.00mil 2595.00mil 1145.00mil 10.00mil 20.00mil "clearline"] + Line[1815.00mil 675.00mil 2320.00mil 675.00mil 10.00mil 20.00mil "clearline"] + Line[2320.00mil 675.00mil 2750.00mil 1105.00mil 10.00mil 20.00mil "clearline"] + Polygon("clearpoly") + ( + [40.00mil 40.00mil] [2960.00mil 40.00mil] [2960.00mil 2460.00mil] [40.00mil 2460.00mil] + ) +) +Layer(3 "GND") +( +) +Layer(4 "power") +( +) +Layer(5 "signal1") +( +) +Layer(6 "signal2") +( +) +Layer(7 "signal3") +( +) +Layer(8 "signal4") +( +) +Layer(9 "silk") +( +) +Layer(10 "silk") +( + Text[250.00mil 2325.00mil 0 100 "RESET" "clearline"] + Text[260.00mil 1755.00mil 0 100 "PWON" "clearline"] +) +NetList() +( + Net("CTS_MODEM" "(unknown)") + ( + Connect("J2-21") + Connect("J3-10") + ) + Net("EARN" "(unknown)") + ( + Connect("J2-36") + Connect("J5-2") + ) + Net("EARP" "(unknown)") + ( + Connect("J2-35") + Connect("J5-1") + ) + Net("GND" "(unknown)") + ( + Connect("C1-2") + Connect("C2-2") + Connect("J1-3") + Connect("J2-6") + Connect("J2-7") + Connect("J2-8") + Connect("J2-9") + Connect("J2-10") + Connect("J2-29") + Connect("J2-41") + Connect("J2-42") + Connect("J3-1") + Connect("J3-2") + Connect("J4-4") + Connect("J4-5") + Connect("J4-8") + Connect("K1-3") + Connect("K1-4") + Connect("K2-3") + Connect("K2-4") + Connect("Q1-2") + ) + Net("GPIO2_DCD" "(unknown)") + ( + Connect("J2-23") + Connect("J3-7") + ) + Net("GPIO3_DTR" "(unknown)") + ( + Connect("J2-22") + Connect("J3-9") + ) + Net("led.LED_to_Q" "(unknown)") + ( + Connect("D1-1") + Connect("Q1-3") + ) + Net("led.R_to_LED" "(unknown)") + ( + Connect("D1-2") + Connect("R1-2") + ) + Net("MICN" "(unknown)") + ( + Connect("J2-38") + Connect("J6-2") + ) + Net("MICP" "(unknown)") + ( + Connect("J2-37") + Connect("J6-1") + ) + Net("nTESTRESET" "(unknown)") + ( + Connect("J2-31") + Connect("K2-1") + Connect("K2-2") + ) + Net("PWON" "(unknown)") + ( + Connect("J2-15") + Connect("K1-1") + Connect("K1-2") + ) + Net("RTS_MODEM" "(unknown)") + ( + Connect("J2-20") + Connect("J3-8") + ) + Net("RX_IRDA" "(unknown)") + ( + Connect("J2-12") + Connect("J3-5") + ) + Net("RX_MODEM" "(unknown)") + ( + Connect("J2-19") + Connect("J3-6") + ) + Net("SIM_CLK" "(unknown)") + ( + Connect("J2-27") + Connect("J4-3") + ) + Net("SIM_IO" "(unknown)") + ( + Connect("J2-26") + Connect("J4-7") + ) + Net("SIM_RST" "(unknown)") + ( + Connect("J2-25") + Connect("J4-2") + ) + Net("TX_IRDA" "(unknown)") + ( + Connect("J2-11") + Connect("J3-3") + ) + Net("TX_MODEM" "(unknown)") + ( + Connect("J2-18") + Connect("J3-4") + ) + Net("VBAT" "(unknown)") + ( + Connect("C1-1") + Connect("J1-1") + Connect("J2-1") + Connect("J2-2") + Connect("J2-3") + Connect("J2-4") + Connect("J2-5") + Connect("R1-1") + ) + Net("Vio" "(unknown)") + ( + Connect("J2-13") + Connect("J2-24") + Connect("Q1-1") + ) + Net("VSIM" "(unknown)") + ( + Connect("C2-1") + Connect("J2-28") + Connect("J4-1") + Connect("J4-6") + ) +)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/MCL Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,142 @@ +# Big power capacitor +C1: + hier=big_cap + manufacturer=Vishay Sprague + manufacturer_part_number=595D108X96R3R2T + # Leonardo used 20% version, but the 10% version is now cheaper at Mouser! + description=Tantalum capacitor, 1000 uF, 6.3 V, 70 mOhm ESR + footprint=file:TAN-R-59XD + npins=2 + source=Jotrin + +# VSIM bypass cap next to the SIM socket +C2: + hier=sim.C306 + value=1uF + footprint=0603 + description=Ceramic chip capacitor, X5R, 1 uF, 0603 + manufacturer=Samsung Electro-Mechanics + manufacturer_part_number=CL10A105KB8NNNC + vendor=Digi-Key + vendor_part_number=1276-1860-1-ND + npins=2 + +D1: + hier=led.led + device=SML-510MW + manufacturer=Rohm + manufacturer_part_number=SML-510MWT86 + description=SMT LED, green, 0603 + vendor=Digi-Key + vendor_part_number=511-1308-1-ND + footprint=file:SML-510MW + pinout=ipc-diode.pinout + npins=2 + +# Power input connector +J1: + hier=pwr_input_conn + manufacturer=Weidmuller + manufacturer_part_number=1510460000 + description=Power input connector, 3 pins, 5.08 mm spacing + source=Newark + source=Digi-Key + footprint=file:Weidmuller_1510460000 + npins=3 + +# FPC connector for the DUT +J2: + hier=dut_if.fpc_conn + manufacturer=Hirose + manufacturer_part_number=FH12-40S-0.5SH + description=FPC connector, 40 positions + vendor=Digi-Key + vendor_part_number=HFJ140CT-ND + footprint=FH12_40S_05SH_1R # pin 1 on the right + npins=42 # 40 + 2 mounting pads + +# Dual UART header +J3: + hier=uart_if.uart_header + footprint=HEADER10_2 + description=Header, 0.100", dual row, 10 posts + manufacturer=Molex + manufacturer_part_number=0901310125 + vendor=Digi-Key + vendor_part_number=WM50035-10-ND + npins=10 + +# SIM socket +J4: + hier=sim.socket + description=SIM socket, full size, hinged + manufacturer=Molex + manufacturer_part_number=0473882001 + vendor=Digi-Key + vendor_part_number=WM3292CT-ND + footprint=file:SIM_Socket_473882001 + pinout=SIM_Socket_473882001.pinout + npins=8 + +part header-2pin: + footprint=JUMPER2 + description=Header, 0.100", 2 posts + manufacturer=Molex + manufacturer_part_number=0901200122 + vendor=Digi-Key + vendor_part_number=WM8072-ND + npins=2 + +# Earpiece speaker +J5: + hier=J5 + part=header-2pin + +# Microphone +J6: + hier=J6 + part=header-2pin + +part pushbutton-smt-ti: + manufacturer=Omron + manufacturer_part_number=B3S-1000 + description=Tactile switch, SPNO, SMT + vendor=Digi-Key + vendor_part_number=SW415-ND + footprint=file:Omron_B3S_1000 + npins=4 + +# PWON button +K1: + hier=pwr_btn.pkg + part=pushbutton-smt-ti + +# nTESTRESET button +K2: + hier=reset_btn.pkg + part=pushbutton-smt-ti + +# MOSFET for driving the power on LED +Q1: + hier=led.Q + device=Si1032R + pinout=Si1032R.pinout + footprint=SC75A + npins=3 + description=N-channel MOSFET, 1.5V logic level gate, SC75A + manufacturer=Vishay Siliconix + manufacturer_part_number=SI1032R-T1-GE3 + vendor=Digi-Key + vendor_part_number=SI1032R-T1-GE3CT-ND + +# power on LED series resistor +R1: + hier=led.R + value=470 + footprint=0603 + description=Chip resistor, 470 ohm, 1%, 0603 + manufacturer=Yageo + manufacturer_part_number=RC0603FR-07470RL + vendor=Digi-Key + vendor_part_number=311-470HRCT-ND + npins=2
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/Makefile Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,30 @@ +VSRCS= vsrc/board.v vsrc/interface.v vsrc/led_circuit.v vsrc/pushbutton_wrap.v\ + vsrc/sim_socket_block.v vsrc/uart_bringout.v +BOMS= tallied-bom.txt tallied-bom.csv comptab.txt +NETS= sverp.unet bound.unet pcb-netlist.txt + +all: ${BOMS} ${NETS} elements.pcb + +sverp.unet: ${VSRCS} primitives Makefile + ueda-sverp -o $@ ${VSRCS} + +bound.unet: MCL sverp.unet + unet-bind -c sverp.unet $@ + +pcb-netlist.txt: bound.unet + unet2pcb bound.unet $@ + +tallied-bom.txt: MCL + ueda-mkbom -cr > $@ + +tallied-bom.csv: MCL + ueda-csvbom > $@ + +comptab.txt: MCL + ueda-shortbom > $@ + +elements.pcb: MCL + ueda-getfps -ch | ueda-runm4 > $@ + +clean: + rm -f *.unet *.txt *.csv errs elements.pcb
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/primitives Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,21 @@ +/* + * This file defines the primitives to be instantiated from the structural + * Verilog source for the board: IC package types, basic components and + * subpackages to be mapped later in the MCL binding step. + */ + +resistor numpins 2; +capacitor numpins 2; + +diode mapped_pins (A, C); +mosfet mapped_pins (G, S, D); + +/* connectors */ +header_2pin numpins 2; +conn_3pin numpins 3; +header_10pin numpins 10; +conn_40pin_plus2 numpins 42; + +/* misc peripherals */ +pkg_SIM_socket mapped_pins (C1, C2, C3, C5, C6, C7, M1, M2); +pkg_pushbutton_4pin numpins 4;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/sympath Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,1 @@ +/usr/local/eda/ifctf-part-lib/uschem-symbols
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/vsrc/board.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,84 @@ +/* + * This is the top level structural Verilog module for the MMTB1 board. + */ + +module board (); + +wire GND, VBAT, Vio; +wire PWON, nTESTRESET; + +wire TX_IRDA, RX_IRDA; +wire TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM; +wire GPIO2_DCD, GPIO3_DTR; + +wire VSIM, SIM_CLK, SIM_RST, SIM_IO; + +wire EARP, EARN, MICP, MICN; + +/* power input to the rig */ +conn_3pin pwr_input_conn (.pin_1(VBAT), + .pin_2(), + .pin_3(GND) + ); + +capacitor big_cap (VBAT, GND); + +/* DUT interface connector */ +interface dut_if (.GND(GND), + .VBAT(VBAT), + .PWON(PWON), + .nTESTRESET(nTESTRESET), + .Vio(Vio), + .TX_IRDA(TX_IRDA), + .RX_IRDA(RX_IRDA), + .TX_MODEM(TX_MODEM), + .RX_MODEM(RX_MODEM), + .RTS_MODEM(RTS_MODEM), + .CTS_MODEM(CTS_MODEM), + .GPIO2_DCD(GPIO2_DCD), + .GPIO3_DTR(GPIO3_DTR), + .VSIM(VSIM), + .SIM_IO(SIM_IO), + .SIM_CLK(SIM_CLK), + .SIM_RST(SIM_RST), + .EARP(EARP), + .EARN(EARN), + .MICP(MICP), + .MICN(MICN) + ); + +/* PWON and nTESTRESET pushbuttons */ +pushbutton_wrap pwr_btn (PWON, GND); +pushbutton_wrap reset_btn (nTESTRESET, GND); + +/* power on LED */ +led_circuit led (.GND(GND), + .VBAT(VBAT), + .Signal(Vio) + ); + +/* SIM socket */ +sim_socket_block sim (.GND(GND), + .VSIM(VSIM), + .SIM_CLK(SIM_CLK), + .SIM_RST(SIM_RST), + .SIM_IO(SIM_IO) + ); + +/* UART interfaces */ +uart_bringout uart_if (.GND(GND), + .TX_MODEM(TX_MODEM), + .RX_MODEM(RX_MODEM), + .RTS_MODEM(RTS_MODEM), + .CTS_MODEM(CTS_MODEM), + .GPIO_DCD(GPIO2_DCD), + .GPIO_DTR(GPIO3_DTR), + .TX_IRDA(TX_IRDA), + .RX_IRDA(RX_IRDA) + ); + +/* earpiece and microphone connectors */ +header_2pin J5 (EARP, EARN); +header_2pin J6 (MICP, MICN); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/vsrc/interface.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,76 @@ +/* + * This module encapsulates the FPC interface connector. + */ + +module interface (GND, VBAT, PWON, nTESTRESET, Vio, + TX_IRDA, RX_IRDA, + TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, + GPIO2_DCD, GPIO3_DTR, + VSIM, SIM_IO, SIM_CLK, SIM_RST, + EARP, EARN, MICP, MICN); + +input GND, VBAT, PWON, nTESTRESET; +output Vio; + +input GPIO3_DTR, RX_MODEM, CTS_MODEM, RX_IRDA; +output GPIO2_DCD, TX_MODEM, RTS_MODEM, TX_IRDA; + +output VSIM, SIM_CLK, SIM_RST; +inout SIM_IO; + +output EARP, EARN; +input MICP, MICN; + +/* instantiate the connector! */ + +conn_40pin_plus2 fpc_conn (.pin_1(VBAT), + .pin_2(VBAT), + .pin_3(VBAT), + .pin_4(VBAT), + .pin_5(VBAT), + .pin_6(GND), + .pin_7(GND), + .pin_8(GND), + .pin_9(GND), + .pin_10(GND), + .pin_11(TX_IRDA), + .pin_12(RX_IRDA), + .pin_13(Vio), + .pin_14(), /* no connect to ADC */ + .pin_15(PWON), + .pin_16(), /* no connect to GPIO1 */ + .pin_17(), /* no connect to GPIO0 */ + .pin_18(TX_MODEM), + .pin_19(RX_MODEM), + .pin_20(RTS_MODEM), + .pin_21(CTS_MODEM), + .pin_22(GPIO3_DTR), + .pin_23(GPIO2_DCD), + .pin_24(Vio), /* SIM_CD to Vio per TI/OM/FC */ + .pin_25(SIM_RST), + .pin_26(SIM_IO), + .pin_27(SIM_CLK), + .pin_28(VSIM), + .pin_29(GND), /* for SIM */ + .pin_30(), /* no connect to Vbackup */ + .pin_31(nTESTRESET), + /* + * Pins 32-40 differ between GTM900 and FCM40. + * We connect EARP&EARN and MICP&MICN per GTM900 + * and leave the rest unconnected on MMTB1. + */ + .pin_32(), + .pin_33(), + .pin_34(), + .pin_35(EARP), + .pin_36(EARN), + .pin_37(MICP), + .pin_38(MICN), + .pin_39(), + .pin_40(), + /* ground the two mounting pads */ + .pin_41(GND), + .pin_42(GND) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/vsrc/led_circuit.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,17 @@ +/* + * This module captures the circuit for showing the state of a digital signal + * on a LED without loading that digital signal by driving the LED from VBAT + * and using a MOSFET to control it. + */ + +module led_circuit (GND, VBAT, Signal); + +input GND, VBAT, Signal; + +wire R_to_LED, LED_to_Q; + +resistor R (VBAT, R_to_LED); +diode led (.A(R_to_LED), .C(LED_to_Q)); +mosfet Q (.G(Signal), .S(GND), .D(LED_to_Q)); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/vsrc/pushbutton_wrap.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,13 @@ +/* wrapper for the 4-pin pushbutton package */ + +module pushbutton_wrap (side1, side2); + +input side1, side2; + +pkg_pushbutton_4pin pkg (.pin_1(side1), + .pin_2(side1), + .pin_3(side2), + .pin_4(side2) + ); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/vsrc/sim_socket_block.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,23 @@ +/* This module encapsulates the SIM socket and any needed caps */ + +module sim_socket_block (GND, VSIM, SIM_CLK, SIM_RST, SIM_IO); + +input GND, VSIM; +input SIM_CLK, SIM_RST; +inout SIM_IO; + +pkg_SIM_socket socket ( .C1(VSIM), + .C2(SIM_RST), + .C3(SIM_CLK), + .C5(GND), + .C6(VSIM), + .C7(SIM_IO), + /* mounting pads */ + .M1(GND), + .M2(GND) + ); + +/* cap per Leonardo schematics */ +capacitor C306 (VSIM, GND); + +endmodule
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmtb1/schem+bom/vsrc/uart_bringout.v Mon Oct 21 00:53:38 2019 +0000 @@ -0,0 +1,26 @@ +/* + * This Verilog module encapsulates the header connector on which + * the two Calypso UARTs will be brought out. + */ + +module uart_bringout (GND, TX_MODEM, RX_MODEM, RTS_MODEM, CTS_MODEM, + GPIO_DCD, GPIO_DTR, TX_IRDA, RX_IRDA); + +input GND; + +input TX_MODEM, RTS_MODEM, TX_IRDA, GPIO_DCD; +output RX_MODEM, CTS_MODEM, RX_IRDA, GPIO_DTR; + +header_10pin uart_header (.pin_1(GND), + .pin_2(GND), + .pin_3(TX_IRDA), + .pin_4(TX_MODEM), + .pin_5(RX_IRDA), + .pin_6(RX_MODEM), + .pin_7(GPIO_DCD), + .pin_8(RTS_MODEM), + .pin_9(GPIO_DTR), + .pin_10(CTS_MODEM) + ); + +endmodule