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changeset 23:22aba3a61a4b

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duart28: vsrc passes sverp
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Jun 2020 06:38:05 +0000
parents 43097651a26d
children 9e71844f4db0
files duart28/src/Makefile duart28/src/vsrc/FT2232D_block.v duart28/src/vsrc/FT2232D_chip.v duart28/src/vsrc/USB_block.v duart28/src/vsrc/application_block.v duart28/src/vsrc/board.v duart28/src/vsrc/eeprom_93Cx6_16bit.v duart28/src/vsrc/regulator_ic.v duart28/src/vsrc/regulator_with_caps.v duart28/src/vsrc/target_if.v duart28/src/vsrc/usb_conn.v
diffstat 11 files changed, 414 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
--- a/duart28/src/Makefile	Sat Jun 13 05:28:01 2020 +0000
+++ b/duart28/src/Makefile	Sat Jun 13 06:38:05 2020 +0000
@@ -1,6 +1,11 @@
+VSRCS=	vsrc/FT2232D_block.v vsrc/FT2232D_chip.v vsrc/USB_block.v \
+	vsrc/application_block.v vsrc/board.v vsrc/eeprom_93Cx6_16bit.v \
+	vsrc/regulator_ic.v vsrc/regulator_with_caps.v vsrc/target_if.v \
+	vsrc/usb_conn.v
 BOMS=	tallied-bom.txt tallied-bom.csv comptab.txt
+NETS=	sverp.unet
 
-all:	${BOMS} elements.pcb
+all:	${BOMS} ${NETS} elements.pcb
 
 tallied-bom.txt:	MCL
 	ueda-mkbom -cr > $@
@@ -14,5 +19,8 @@
 elements.pcb:	MCL
 	ueda-getfps -ch | ueda-runm4 > $@
 
+sverp.unet:	${VSRCS} primitives Makefile
+	ueda-sverp -o $@ ${VSRCS}
+
 clean:
 	rm -f *.unet *.txt *.csv errs elements.pcb
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/FT2232D_block.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,85 @@
+/*
+ * This module encapsulates the FT2232D chip and its immediate accessories:
+ * the oscillator crystal, the EEPROM, the AVCC filter and the cap on 3V3OUT.
+ */
+
+module FT2232D_block (GND, VCC, VCCIOA, VCCIOB,
+		      USBDP, USBDM, RESET, RSTOUT, PWREN,
+		      ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB);
+
+input GND, VCC, VCCIOA, VCCIOB;
+
+inout USBDP, USBDM;
+
+input RESET;
+output RSTOUT, PWREN;
+
+inout [7:0] ADBUS, BDBUS;
+inout [3:0] ACBUS, BCBUS;
+input SI_WUA, SI_WUB;
+
+/* FT2232D pins handled within this block */
+
+wire EECS, EESK, EEDATA;
+wire XTIN, XTOUT;
+wire AVCC, FTDI_3V3;
+
+/* instantiate the FT2232D */
+
+FT2232D_chip FT2232D   (.GND(GND),
+			.AGND(GND),
+			.VCC(VCC),
+			.AVCC(AVCC),
+			.VCCIOA(VCCIOA),
+			.VCCIOB(VCCIOB),
+			.OUT_3V3(FTDI_3V3),
+			.USBDP(USBDP),
+			.USBDM(USBDM),
+			.EECS(EECS),
+			.EESK(EESK),
+			.EEDATA(EEDATA),
+			.RESET(RESET),
+			.RSTOUT(RSTOUT),
+			.TEST(GND),
+			.PWREN(PWREN),
+			.XTIN(XTIN),
+			.XTOUT(XTOUT),
+			.ADBUS(ADBUS),
+			.ACBUS(ACBUS),
+			.SI_WUA(SI_WUA),
+			.BDBUS(BDBUS),
+			.BCBUS(BCBUS),
+			.SI_WUB(SI_WUB)
+	);
+
+/* AVCC filter */
+
+resistor AVCC_filter_R (VCC, AVCC);
+capacitor AVCC_cap (AVCC, GND);
+
+/* 3V3OUT */
+
+capacitor FTDI_3V3_cap (FTDI_3V3, GND);
+
+/* crystal oscillator */
+
+xtal_2pin_pkg xtal (XTIN, XTOUT);
+capacitor XTIN_cap (XTIN, GND);
+capacitor XTOUT_cap (XTOUT, GND);
+
+/* serial EEPROM */
+
+wire EEPROM_DOUT;
+
+eeprom_93Cx6_16bit eeprom (.GND(GND),
+			   .VCC(VCC),
+			   .CS(EECS),
+			   .SK(EESK),
+			   .DIN(EEDATA),
+			   .DOUT(EEPROM_DOUT)
+	);
+
+resistor DOUT_series_R (EEPROM_DOUT, EEDATA);
+resistor DOUT_pullup_R (EEPROM_DOUT, VCC);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/FT2232D_chip.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,78 @@
+/*
+ * This module encapsulates the FT2232D chip and its pinout.
+ */
+
+module FT2232D_chip (GND, AGND, VCC, AVCC, VCCIOA, VCCIOB, OUT_3V3,
+		USBDP, USBDM, EECS, EESK, EEDATA, RESET, RSTOUT, TEST, PWREN,
+		XTIN, XTOUT, ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB);
+
+input GND, AGND, VCC, AVCC, VCCIOA, VCCIOB;
+output OUT_3V3;
+
+inout USBDP, USBDM;
+output EECS, EESK;
+inout EEDATA;
+
+input RESET, TEST;
+output RSTOUT, PWREN;
+
+input XTIN;
+output XTOUT;
+
+inout [7:0] ADBUS, BDBUS;
+inout [3:0] ACBUS, BCBUS;
+input SI_WUA, SI_WUB;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_LQFP48 pkg (.pin_1(EESK),
+		.pin_2(EEDATA),
+		.pin_3(VCC),
+		.pin_4(RESET),
+		.pin_5(RSTOUT),
+		.pin_6(OUT_3V3),
+		.pin_7(USBDP),
+		.pin_8(USBDM),
+		.pin_9(GND),
+		.pin_10(SI_WUA),
+		.pin_11(ACBUS[3]),
+		.pin_12(ACBUS[2]),
+		.pin_13(ACBUS[1]),
+		.pin_14(VCCIOA),
+		.pin_15(ACBUS[0]),
+		.pin_16(ADBUS[7]),
+		.pin_17(ADBUS[6]),
+		.pin_18(GND),
+		.pin_19(ADBUS[5]),
+		.pin_20(ADBUS[4]),
+		.pin_21(ADBUS[3]),
+		.pin_22(ADBUS[2]),
+		.pin_23(ADBUS[1]),
+		.pin_24(ADBUS[0]),
+		.pin_25(GND),
+		.pin_26(SI_WUB),
+		.pin_27(BCBUS[3]),
+		.pin_28(BCBUS[2]),
+		.pin_29(BCBUS[1]),
+		.pin_30(BCBUS[0]),
+		.pin_31(VCCIOB),
+		.pin_32(BDBUS[7]),
+		.pin_33(BDBUS[6]),
+		.pin_34(GND),
+		.pin_35(BDBUS[5]),
+		.pin_36(BDBUS[4]),
+		.pin_37(BDBUS[3]),
+		.pin_38(BDBUS[2]),
+		.pin_39(BDBUS[1]),
+		.pin_40(BDBUS[0]),
+		.pin_41(PWREN),
+		.pin_42(VCC),
+		.pin_43(XTIN),
+		.pin_44(XTOUT),
+		.pin_45(AGND),
+		.pin_46(AVCC),
+		.pin_47(TEST),
+		.pin_48(EECS)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/USB_block.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,67 @@
+/*
+ * This module encapsulates the USB connector, the FT2232D block and
+ * the glue components between them.
+ */
+
+module USB_block (GND, P_5V, VCCIOA, VCCIOB,
+		  ADBUS, ACBUS, SI_WUA, BDBUS, BCBUS, SI_WUB, PWREN);
+
+output GND, P_5V;
+
+input VCCIOA, VCCIOB;
+inout [7:0] ADBUS, BDBUS;
+inout [3:0] ACBUS, BCBUS;
+input SI_WUA, SI_WUB;
+output PWREN;
+
+/* interconnecting wires */
+
+wire VBUS;
+wire DM_connector_side, DM_chip_side;
+wire DP_connector_side, DP_chip_side;
+wire RSTOUT;
+
+usb_conn conn  (.GND(GND),
+		.VBUS(VBUS),
+		.Dminus(DM_connector_side),
+		.Dplus(DP_connector_side),
+		.ID()	/* no connect */
+	);
+
+/* ferrite bead on the power supply */
+
+inductor VBUS_ferrite (VBUS, P_5V);
+
+/* series resistors on USB data lines */
+
+resistor DM_series_R (DM_connector_side, DM_chip_side);
+resistor DP_series_R (DP_connector_side, DP_chip_side);
+
+/* we can now bring in the FT2232D block */
+
+FT2232D_block FT2232D  (.GND(GND),
+			.VCC(P_5V),
+			.VCCIOA(VCCIOA),
+			.VCCIOB(VCCIOB),
+			.USBDP(DP_chip_side),
+			.USBDM(DM_chip_side),
+			.RESET(P_5V),
+			.RSTOUT(RSTOUT),
+			.PWREN(PWREN),
+			.ADBUS(ADBUS),
+			.ACBUS(ACBUS),
+			.SI_WUA(SI_WUA),
+			.BDBUS(BDBUS),
+			.BCBUS(BCBUS),
+			.SI_WUB(SI_WUB)
+	);
+
+resistor DP_pullup_R (DP_chip_side, RSTOUT);
+
+/* power bypass caps */
+
+capacitor VBUS_in_cap (VBUS, GND);
+capacitor P_5V_cap (P_5V, GND);
+capacitor P_5V_cap2 (P_5V, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/application_block.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,41 @@
+/*
+ * This module encapsulates the application function of our board:
+ * dual UART with 2.8V outputs.
+ */
+
+module application_block (GND, P_2V8, ADBUS, BDBUS);
+
+input GND, P_2V8;
+
+inout [7:0] ADBUS, BDBUS;
+
+/* 2.8V output wires */
+
+wire TxD_2V8, RTS_2V8, DTR_2V8, TxD2_2V8;
+
+/* output buffers */
+
+buffer_ic_common output_buf_common (.Vcc(P_2V8), .GND(GND));
+capacitor output_buf_bypass_cap (P_2V8, GND);
+
+buffer_ic_slot buf_TxD  (.A(ADBUS[0]), .Y(TxD_2V8),  .nOE(GND));
+buffer_ic_slot buf_RTS  (.A(ADBUS[2]), .Y(RTS_2V8),  .nOE(GND));
+buffer_ic_slot buf_DTR  (.A(ADBUS[4]), .Y(DTR_2V8),  .nOE(GND));
+buffer_ic_slot buf_TxD2 (.A(BDBUS[0]), .Y(TxD2_2V8), .nOE(GND));
+
+/* target interface headers */
+
+target_if target_if (	.GND(GND),
+			.UART0_TxD(TxD_2V8),
+			.UART0_RxD(ADBUS[1]),
+			.UART0_RTS(RTS_2V8),
+			.UART0_CTS(ADBUS[3]),
+			.UART0_DTR(DTR_2V8),
+			.UART0_DSR(ADBUS[5]),
+			.UART0_DCD(ADBUS[6]),
+			.UART0_RI(ADBUS[7]),
+			.UART1_TxD(TxD2_2V8),
+			.UART1_RxD(BDBUS[1])
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/board.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,30 @@
+module board ();
+
+wire GND, P_5V, P_3V3, P_2V8;
+
+wire [7:0] ADBUS, BDBUS;
+wire [3:0] ACBUS, BCBUS;
+
+USB_block usb ( .GND(GND),
+		.P_5V(P_5V),
+		.VCCIOA(P_3V3),
+		.VCCIOB(P_3V3),
+		.ADBUS(ADBUS),
+		.ACBUS(ACBUS),
+		.SI_WUA(P_3V3),
+		.BDBUS(BDBUS),
+		.BCBUS(BCBUS),
+		.SI_WUB(P_3V3),
+		.PWREN()	/* no connect */
+	);
+
+regulator_with_caps reg_3V3 (.GND(GND), .IN(P_5V), .OUT(P_3V3));
+regulator_with_caps reg_2V8 (.GND(GND), .IN(P_5V), .OUT(P_2V8));
+
+application_block app ( .GND(GND),
+			.P_2V8(P_2V8),
+			.ADBUS(ADBUS),
+			.BDBUS(BDBUS)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/eeprom_93Cx6_16bit.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,19 @@
+module eeprom_93Cx6_16bit (GND, VCC, CS, SK, DIN, DOUT);
+
+input GND, VCC;
+input CS, SK, DIN;
+output DOUT;
+
+/* instantiate the package; the mapping of signals to pins is defined here */
+
+pkg_8pin pkg   (.pin_1(CS),
+		.pin_2(SK),
+		.pin_3(DIN),
+		.pin_4(DOUT),
+		.pin_5(GND),
+		.pin_6(VCC),	/* ORG input on some 93Cx6 variants */
+		.pin_7(),	/* no connect */
+		.pin_8(VCC)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/regulator_ic.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,13 @@
+module regulator_ic (IN, OUT, GND, EN);
+
+input IN, GND, EN;
+output OUT;
+
+pkg_5pin pkg (  .pin_1(IN),
+		.pin_2(GND),
+		.pin_3(EN),
+		.pin_4(),	/* no connect */
+		.pin_5(OUT)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/regulator_with_caps.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,15 @@
+module regulator_with_caps (GND, IN, OUT);
+
+input GND, IN;
+output OUT;
+
+regulator_ic reg (.IN(IN),
+		  .OUT(OUT),
+		  .GND(GND),
+		  .EN(IN)
+	);
+
+capacitor input_cap (IN, GND);
+capacitor output_cap (OUT, GND);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/target_if.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,36 @@
+/* This module captures our target interfaces. */
+
+module target_if (GND, UART0_TxD, UART0_RxD, UART0_RTS, UART0_CTS,
+		  UART0_DTR, UART0_DSR, UART0_DCD, UART0_RI,
+		  UART1_TxD, UART1_RxD);
+
+input GND;
+
+input UART0_TxD, UART0_RTS, UART0_DTR;
+output UART0_RxD, UART0_CTS, UART0_DSR, UART0_DCD, UART0_RI;
+
+input UART1_TxD;
+output UART1_RxD;
+
+/* main DUART signal set header */
+
+header_10pin main_if (  .pin_1(GND),
+			.pin_2(GND),
+			.pin_3(UART1_RxD),
+			.pin_4(UART0_RxD),
+			.pin_5(UART1_TxD),
+			.pin_6(UART0_TxD),
+			.pin_7(UART0_DCD),
+			.pin_8(UART0_CTS),
+			.pin_9(UART0_DTR),
+			.pin_10(UART0_RTS)
+	);
+
+/* auxiliary DSR and RI */
+
+header_3pin aux_if (.pin_1(GND),
+		    .pin_2(UART0_DSR),
+		    .pin_3(UART0_RI)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/duart28/src/vsrc/usb_conn.v	Sat Jun 13 06:38:05 2020 +0000
@@ -0,0 +1,21 @@
+/*
+ * This module captures the mini-USB connector.
+ */
+
+module usb_conn (GND, VBUS, Dminus, Dplus, ID);
+
+inout GND, VBUS, Dminus, Dplus, ID;
+
+conn_miniUSB_plus4 conn (.pin_1(VBUS),
+			 .pin_2(Dminus),
+			 .pin_3(Dplus),
+			 .pin_4(ID),
+			 .pin_5(GND),
+			 /* mounting pads */
+			 .pin_6(GND),
+			 .pin_7(GND),
+			 .pin_8(GND),
+			 .pin_9(GND)
+	);
+
+endmodule