--- a/duart28/design-spec	Fri Jul 24 20:21:54 2020 +0000
+++ b/duart28/design-spec	Fri Jul 24 20:22:36 2020 +0000
@@ -301,3 +301,113 @@
 The FT2232D chip's built-in 3.3V LDO won't be used: its 5 mA current limit
 seems to be too small, and our current FT2232D adapter boards made by PLDkit
 don't use it either, using an external beefier LDO instead.
+
+3. PCB layout specification
+
+3.1. Overall dimensions
+
+The generic FT2232D breakout board from PLDkit which the present DUART28 seeks
+to replace measures 39.37x46.99 mm or 1550x1850 mil.  If the present DUART28
+circuit can be squeezed into the same size, great - but such squeeze is NOT
+required.  If our DUART28 requires a larger PCB because of our greater circuit
+complexity and having more components, using a larger PCB would be perfectly
+fine - however much space is needed to get the job done.  There is no specific
+form factor requirement, i.e., this project is a free-form design.
+
+3.2. Layer count
+
+PLDkit's FT2232D adapter board appears to have a 2-layer PCB, and our competitor
+mv-uart by Sysmocom (CP2105-based) is known to have a 2-layer PCB thanks to
+published design files.  However, we shall go by the same business logic as with
+board dimensions: if the needed layout can be done in just 2 layers, great, but
+if the PCB layout engineer feels that going to 4 layers would be better or would
+make the layout job easier, it would be perfectly OK to have 4 layers.
+
+3.3. Mounting holes
+
+The PCB should have 4 mounting holes in the corners, accommodating M3 screws.
+It is OK to increase overall board dimensions slightly to make room for these
+mounting holes.
+
+3.4. Placement of connectors
+
+USB mini-B connector J1 must be placed along one of the board edges; it does not
+matter along which edge, or exactly where.
+
+Shrouded 2x5 header J2 can be placed anywhere, as long as the placement makes
+sense for cable attachment purposes.  The cable plugged into this connector will
+be a 10-wire ribbon terminated with an IDC connector, thus the body of the flat
+cable will lie parallel to the board surface.  Orientation: the body of the
+cable will face toward the even-numbered row of pins, i.e., away from the
+polarizing tab identified with a silk screen mark in the currently drawn
+footprint.
+
+Little headers J3 and J4 can be placed anywhere; they are not shrouded and the
+only things that can be connected to them are either individual jumper wires or
+crimped assemblies with wires rising up, perpendicular to the board.
+
+3.5. Connector silk screen labels
+
+All three user connection headers J2, J3 and J4 shall have silk screen labels
+identifying every pin.  J2 pins shall be labeled as follows, numbers in the
+middle indicate physical pins and shall NOT be placed on the silk screen
+themselves:
+
+GND  1  2 GND
+RxD2 3  4 RxD
+TxD2 5  6 TxD
+DCD  7  8 CTS
+DTR  9 10 RTS
+
+J3 pins shall be labeled as follows, numbers on the left indicate physical pins
+and shall NOT be placed on the silk screen themselves:
+
+1 GND
+2 DSR
+3 RI
+
+J4 pins shall be labeled as follows, same deal with pin numbers:
+
+1 +5V
+2 GND
+
+3.6. 74LVC541A slot assignment
+
+74LVC541A is an octal buffer IC that can be seen as a bundle of 8 single buffers
+with common output enables; the latter are always enabled in our present
+circuit.  The present design uses two of these octal buffer ICs (see section
+2.4): one with 4 signals and 4 unused slots (grounded A inputs, unconnected Y
+outputs) and one with 6 signals and 2 unused slots.  The mapping of which signal
+should go to which An/Yn slot is arbitrary from the standpoint of circuit
+functionality, thus this mapping should be made at the time of PCB layout for
+physical layout optimization.
+
+The mapping of signals to U5 and U6 slots is defined in U5.slotmap and
+U6.slotmap text files; to change these mappings, edit the two files to define
+the desired mapping, then recompile the netlist by running 'make', producing an
+updated pcb-netlist.txt generated file.
+
+The preliminary slot mapping that exists in the present netlist was created as
+a placeholder to pass compilation, and is NOT expected to be anywhere close to
+optimal for layout!  Therefore, the PCB layout engineer is expected to review
+this slot mapping and optimize it for layout.
+
+3.7. Power bypass capacitors
+
+By the very nature of power bypass capacitors, a netlist gives absolutely no
+indication as to where they need to be placed - yet their physical placement is
+essential to their circuit function.  Because the design of this board is
+captured in ueda language instead of graphical schematics, it is possible that
+the PCB layout engineer may have some difficulty with reading our ueda design
+source to understand the design intent as to where each bypass capacitor should
+be placed.  The following listing is intended to resolve this ambiguity:
+
+* C4 and C7 need to be placed at the output of L1 on the P_5V net;
+* C8 needs to be placed at the input of LDO regulator U3;
+* C9 needs to be placed at the output of LDO regulator U3;
+* C10 needs to be placed at the input of LDO regulator U4;
+* C11 needs to be placed at the output of LDO regulator U4;
+* C12 needs to be placed near pin 20 (Vcc) of U5;
+* C13 needs to be placed near pin 20 (Vcc) of U6;
+* C14 needs to be placed near pin 14 (VCCIOA) of U1;
+* C15 needs to be placed near pin 31 (VCCIOB) of U1.