FreeCalypso > hg > fc-small-hw
changeset 82:803667312307
sim-fpc-pasv: schem+BOM design complete
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Tue, 25 Oct 2022 06:13:01 +0000 |
| parents | 6feb6db2c0bf |
| children | 9efa98ea62e5 |
| files | .hgignore sim-fpc-pasv/src/MCL sim-fpc-pasv/src/Makefile sim-fpc-pasv/src/primitives sim-fpc-pasv/src/schem.v |
| diffstat | 5 files changed, 80 insertions(+), 0 deletions(-) [+] |
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--- a/.hgignore Tue Oct 25 05:13:55 2022 +0000 +++ b/.hgignore Tue Oct 25 06:13:01 2022 +0000 @@ -33,3 +33,5 @@ ^mmtb1/pcb/gerbers\. ^mmtb1/schem\+bom/elements\.pcb$ + +^sim-fpc-pasv/src/elements\.pcb$
--- a/sim-fpc-pasv/src/MCL Tue Oct 25 05:13:55 2022 +0000 +++ b/sim-fpc-pasv/src/MCL Tue Oct 25 06:13:01 2022 +0000 @@ -1,4 +1,5 @@ C1: + hier=C1 value=100n footprint=0603 description=Ceramic chip capacitor, X7R, 0.1 uF, 0603 @@ -9,6 +10,7 @@ npins=2 J1: + hier=fpc manufacturer=Wurth Elektronik manufacturer_part_number=686106148922 description=FPC connector, 1 mm pitch, 6 pins, flip lock @@ -18,6 +20,7 @@ npins=8 # 6 actual pins + 2 mounting pads J2: + hier=sim manufacturer=C&K Components manufacturer_part_number=CCM03-3009LFT description=SIM socket, full size, with latch @@ -36,7 +39,9 @@ npins=4 J3: + hier=tap_C1_C3 part=header-4pin J4: + hier=tap_C5_C7 part=header-4pin
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/sim-fpc-pasv/src/Makefile Tue Oct 25 06:13:01 2022 +0000 @@ -0,0 +1,28 @@ +BOMS= tallied-bom.txt tallied-bom.csv comptab.txt +NETS= sverp.unet bound.unet pcb-netlist.txt + +all: ${BOMS} ${NETS} elements.pcb + +sverp.unet: schem.v primitives + ueda-sverp -o $@ schem.v + +bound.unet: MCL sverp.unet + unet-bind -c sverp.unet $@ + +pcb-netlist.txt: bound.unet + unet2pcb bound.unet $@ + +tallied-bom.txt: MCL + ueda-mkbom -cr > $@ + +tallied-bom.csv: MCL + ueda-csvbom > $@ + +comptab.txt: MCL + ueda-shortbom > $@ + +elements.pcb: MCL + ueda-getfps -ch | ueda-runm4 > $@ + +clean: + rm -f *.unet *.txt *.csv errs elements.pcb
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/sim-fpc-pasv/src/primitives Tue Oct 25 06:13:01 2022 +0000 @@ -0,0 +1,5 @@ +capacitor numpins 2; + +header_4pin numpins 4; +conn_6pin_plus2 numpins 8; +pkg_SIM_socket numpins 8;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/sim-fpc-pasv/src/schem.v Tue Oct 25 06:13:01 2022 +0000 @@ -0,0 +1,40 @@ +module board (); + +wire GND, VCC, VPP, RST, CLK, IO; + +conn_6pin_plus2 fpc (.pin_1(VCC), + .pin_2(RST), + .pin_3(CLK), + .pin_4(IO), + .pin_5(VPP), + .pin_6(GND), + /* mounting pads */ + .pin_7(GND), + .pin_8(GND) + ); + +pkg_SIM_socket sim (.pin_1(VCC), + .pin_2(RST), + .pin_3(CLK), + .pin_4(), /* gap in footprint pin numbering */ + .pin_5(GND), + .pin_6(VPP), + .pin_7(IO), + .pin_8() /* gap in footprint pin numbering */ + ); + +capacitor C1 (VCC, GND); + +header_4pin tap_C1_C3 ( .pin_1(GND), + .pin_2(VCC), /* C1 */ + .pin_3(RST), /* C2 */ + .pin_4(CLK) /* C3 */ + ); + +header_4pin tap_C5_C7 ( .pin_1(GND), + .pin_2(GND), /* C5 */ + .pin_3(VPP), /* C6 */ + .pin_4(IO) /* C7 */ + ); + +endmodule