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changeset 5:839e9b527e69

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lunalcd1 board project started
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 22 Mar 2020 03:19:38 +0000
parents 070b11b83958
children 572cbae1f246
files .hgignore lunalcd1/src/MCL lunalcd1/src/Makefile lunalcd1/src/primitives lunalcd1/src/regulator.v lunalcd1/src/schem.v
diffstat 6 files changed, 266 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/.hgignore	Tue Dec 10 06:56:59 2019 +0000
+++ b/.hgignore	Sun Mar 22 03:19:38 2020 +0000
@@ -15,5 +15,7 @@
 ^lcdtest1/pcb/gerbers\.
 ^lcdtest1/schem\+bom/elements\.pcb$
 
+^lunalcd1/src/elements\.pcb$
+
 ^mmtb1/pcb/gerbers\.
 ^mmtb1/schem\+bom/elements\.pcb$
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd1/src/MCL	Sun Mar 22 03:19:38 2020 +0000
@@ -0,0 +1,105 @@
+# Capacitors
+
+part 0603C-X5R-1uF:
+ value=1uF
+ footprint=0603
+ description=Ceramic chip capacitor, X5R, 1 uF, 0603
+ manufacturer=Samsung Electro-Mechanics
+ manufacturer_part_number=CL10A105KB8NNNC
+ vendor=Digi-Key
+ vendor_part_number=1276-1860-1-ND
+ npins=2
+
+part 0603C-X7R-100nF:
+ value=100nF
+ footprint=0603
+ description=Ceramic chip capacitor, X7R, 0.1 uF, 0603
+ manufacturer=Yageo
+ manufacturer_part_number=CC0603KRX7R9BB104
+ vendor=Digi-Key
+ vendor_part_number=311-1344-1-ND
+ npins=2
+
+# VBAT input bypass cap
+C1:
+ hier=VBAT_bypass_cap
+ part=0603C-X5R-1uF
+
+# 3.5V LDO regulator output bypass cap
+C2:
+ hier=reg_out_cap
+ part=0603C-X5R-1uF
+
+# LCD module bypass cap
+C3:
+ hier=LCD_bypass_cap
+ part=0603C-X7R-100nF
+
+# Connectors
+
+J1:
+ hier=fpc
+ manufacturer=Hirose
+ manufacturer_part_number=FH12-36S-0.5SH
+ description=FPC connector, 36 positions
+ vendor=Digi-Key
+ vendor_part_number=HFJ136CT-ND
+ footprint=FH12_36S_05SH_1L	# pin 1 on the left
+ npins=38			# 36 + 2 mounting pads
+
+J2:
+ hier=main_if
+ footprint=HEADER26_2
+ description=Header, 0.100", dual row, 26 posts
+ manufacturer=Molex
+ manufacturer_part_number=0901310133
+ vendor=Digi-Key
+ vendor_part_number=WM50035-26-ND
+ npins=26
+
+J3:
+ hier=VBAT_conn
+ footprint=JUMPER2
+ description=Header, 0.100", 2 posts
+ manufacturer=Molex
+ manufacturer_part_number=0901200122
+ vendor=Digi-Key
+ vendor_part_number=WM8072-ND
+ npins=2
+
+# Resistors
+
+part led-series-resistor:
+ footprint=0603
+ value=20R
+ description=Chip resistor, 20 ohm, 1%, 0603
+ manufacturer=Yageo
+ manufacturer_part_number=RC0603FR-0720RL
+ vendor=Digi-Key
+ vendor_part_number=311-20.0HRCT-ND
+ npins=2
+
+R1:
+ hier=R1
+ part=led-series-resistor
+
+R2:
+ hier=R2
+ part=led-series-resistor
+
+R3:
+ hier=R3
+ part=led-series-resistor
+
+# LDO regulator IC
+
+U1:
+ hier=reg.pkg
+ manufacturer=TI
+ device=TLV70235DBV
+ part=yes
+ description=LDO regulator, 3.5 V output, SOT23-5
+ vendor=Digi-Key
+ vendor_part_number=296-34811-1-ND
+ footprint=file:TLV700xxDDC
+ npins=5
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd1/src/Makefile	Sun Mar 22 03:19:38 2020 +0000
@@ -0,0 +1,28 @@
+BOMS=	tallied-bom.txt tallied-bom.csv comptab.txt
+NETS=	sverp.unet bound.unet pcb-netlist.txt
+
+all:	${BOMS} ${NETS} elements.pcb
+
+sverp.unet:	schem.v regulator.v primitives
+	ueda-sverp -o $@ schem.v regulator.v
+
+bound.unet:	MCL sverp.unet
+	unet-bind -c sverp.unet $@
+
+pcb-netlist.txt:	bound.unet
+	unet2pcb bound.unet $@
+
+tallied-bom.txt:	MCL
+	ueda-mkbom -cr > $@
+
+tallied-bom.csv:	MCL
+	ueda-csvbom > $@
+
+comptab.txt:	MCL
+	ueda-shortbom > $@
+
+elements.pcb:	MCL
+	ueda-getfps -ch | ueda-runm4 > $@
+
+clean:
+	rm -f *.unet *.txt *.csv errs elements.pcb
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd1/src/primitives	Sun Mar 22 03:19:38 2020 +0000
@@ -0,0 +1,12 @@
+/* passives */
+resistor	numpins 2;
+capacitor	numpins 2;
+
+/* LDO regulator IC */
+pkg_5pin	numpins 5;
+
+/* connectors */
+header_2pin		numpins 2;
+header_26pin		numpins 26;
+conn_36pin		numpins 36;
+conn_36pin_plus2	numpins 38;
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd1/src/regulator.v	Sun Mar 22 03:19:38 2020 +0000
@@ -0,0 +1,13 @@
+module regulator (IN, OUT, GND, EN);
+
+input IN, GND, EN;
+output OUT;
+
+pkg_5pin pkg (  .pin_1(IN),
+		.pin_2(GND),
+		.pin_3(EN),
+		.pin_4(),	/* no connect */
+		.pin_5(OUT)
+	);
+
+endmodule
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/lunalcd1/src/schem.v	Sun Mar 22 03:19:38 2020 +0000
@@ -0,0 +1,106 @@
+module board ();
+
+wire GND, VBAT, Vio;
+wire [15:0] DB;
+wire RD, WR, RS, CS, RESET;
+wire BL_EN, Vbacklight;
+wire [1:3] LEDK;
+
+/* LCD module connector */
+
+conn_36pin_plus2 fpc (  .pin_1(DB[15]),
+			.pin_2(DB[14]),
+			.pin_3(DB[13]),
+			.pin_4(DB[12]),
+			.pin_5(DB[11]),
+			.pin_6(DB[10]),
+			.pin_7(DB[9]),
+			.pin_8(DB[8]),
+			.pin_9(GND),
+			.pin_10(DB[7]),
+			.pin_11(DB[6]),
+			.pin_12(DB[5]),
+			.pin_13(DB[4]),
+			.pin_14(DB[3]),
+			.pin_15(DB[2]),
+			.pin_16(DB[1]),
+			.pin_17(DB[0]),
+			.pin_18(Vio),	/* IOVCC */
+			.pin_19(Vio),	/* VCI */
+			.pin_20(RD),
+			.pin_21(WR),
+			.pin_22(RS),
+			.pin_23(CS),
+			.pin_24(RESET),
+			.pin_25(GND),	/* IM0 tied low */
+			.pin_26(GND),
+			.pin_27(Vbacklight),	/* LEDA */
+			.pin_28(LEDK[1]),
+			.pin_29(LEDK[2]),
+			.pin_30(LEDK[3]),
+			/* the remaining pins are NC */
+			.pin_31(),
+			.pin_32(),
+			.pin_33(),
+			.pin_34(),
+			.pin_35(),
+			.pin_36(),
+			/* ground the two mounting pads */
+			.pin_37(GND),
+			.pin_38(GND)
+	);
+
+/* bypass cap for LCD module core */
+capacitor LCD_bypass_cap (Vio, GND);
+
+/* main interface connector */
+
+header_26pin main_if (  .pin_1(DB[15]),
+			.pin_2(DB[14]),
+			.pin_3(DB[13]),
+			.pin_4(DB[12]),
+			.pin_5(DB[11]),
+			.pin_6(DB[10]),
+			.pin_7(DB[9]),
+			.pin_8(DB[8]),
+			.pin_9(DB[7]),
+			.pin_10(DB[6]),
+			.pin_11(DB[5]),
+			.pin_12(DB[4]),
+			.pin_13(DB[3]),
+			.pin_14(DB[2]),
+			.pin_15(DB[1]),
+			.pin_16(DB[0]),
+			.pin_17(CS),
+			.pin_18(RD),
+			.pin_19(WR),
+			.pin_20(RS),
+			.pin_21(GND),
+			.pin_22(GND),
+			.pin_23(RESET),
+			.pin_24(Vio),
+			.pin_25(BL_EN),
+			.pin_26(GND)
+	);
+
+/* backlight circuit */
+
+header_2pin VBAT_conn ( .pin_1(VBAT),
+			.pin_2(GND)
+	);
+
+capacitor VBAT_bypass_cap (VBAT, GND);
+
+regulator reg ( .IN(VBAT),
+		.OUT(Vbacklight),
+		.GND(GND),
+		.EN(BL_EN)
+	);
+
+capacitor reg_out_cap (Vbacklight, GND);
+
+resistor R1 (LEDK[1], GND);
+resistor R2 (LEDK[2], GND);
+resistor R3 (LEDK[3], GND);
+
+endmodule