--- a/duart28/design-spec	Tue Jul 14 07:40:42 2020 +0000
+++ b/duart28/design-spec	Tue Jul 14 19:01:29 2020 +0000
@@ -130,7 +130,7 @@
 
 * When the Calypso+Iota chipset enters superdeep sleep (our shorthand term for
 Calypso deep sleep combined with Iota ABB sleep mode), the chipset's VRIO
-regulator (the one that produces the 2.8V V-IO raill) switches into sleep mode,
+regulator (the one that produces the 2.8V V-IO rail) switches into sleep mode,
 which has much looser regulation than in the regular Active mode.  In this
 condition external 3.3V can feed into the V-IO rail through pull-up resistors
 and pull the rail itself a little higher than where the chipset's own regulators
@@ -170,10 +170,10 @@
 
 2) When a Calypso device is connected to the USB DUART adapter, the Calypso
 device is up and running (VRPC Active state), but there is no USB host
-connected, current can flow from Calypso outputs into a powered-down FT2232D or
-other chips in the USB DUART adapter.  With our current raw FT2232D-to-Calypso
-arrangement we have about 5 mA of current flowing per pin under the described
-condition, which is a little too much.
+connected, current can flow from Calypso outputs into a powered-down FT2232D
+(or other front-end chips) in the USB DUART adapter.  With our current raw
+FT2232D-to-Calypso arrangement we have about 5 mA of current flowing per pin
+under the described condition, which is a little too much.
 
 If we replace the generic FT2232D breakout with our own custom adapter board
 design, we can solve the second partial power-down problem (the case of Calypso