| Sat, 26 Jun 2021 21:16:48 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate BOM outputs
|
| Sat, 26 Jun 2021 21:16:08 +0000 |
Mychaela Falconia |
lunalcd2/src/MCL: resistor parts nailed down
|
| Sat, 26 Jun 2021 20:40:29 +0000 |
Mychaela Falconia |
lunalcd2/src/MCL: different part for two-post VBAT supply header
|
| Fri, 25 Jun 2021 23:08:00 +0000 |
Mychaela Falconia |
lunalcd2/pcb: add Makefile
|
| Fri, 25 Jun 2021 22:59:37 +0000 |
Mychaela Falconia |
lunalcd2.pcb: manual DRC fixes
|
| Fri, 25 Jun 2021 22:52:20 +0000 |
Mychaela Falconia |
lunalcd2.pcb complete except for DRC
|
| Fri, 25 Jun 2021 22:31:24 +0000 |
Mychaela Falconia |
lunalcd2.pcb almost complete
|
| Fri, 25 Jun 2021 20:29:36 +0000 |
Mychaela Falconia |
lunalcd2.pcb started
|
| Fri, 25 Jun 2021 19:11:21 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate elements.pcb
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| Fri, 25 Jun 2021 19:08:13 +0000 |
Mychaela Falconia |
lunalcd2/src/Makefile: generate pcb-netlist.txt
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| Fri, 25 Jun 2021 19:01:35 +0000 |
Mychaela Falconia |
lunalcd2: MCL binding complete
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| Fri, 25 Jun 2021 18:44:11 +0000 |
Mychaela Falconia |
lunalcd2: structural Verilog source captured
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| Fri, 25 Jun 2021 17:12:02 +0000 |
Mychaela Falconia |
lunalcd2: footprint for the DIP switch pack
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| Wed, 23 Jun 2021 23:53:15 +0000 |
Mychaela Falconia |
lunalcd2 project started with MCL
|
