log

age author description
Sun, 05 Jul 2020 00:10:45 +0000 Mychaela Falconia duart28/src/Makefile: netlist MCL binding added
Sat, 04 Jul 2020 23:37:47 +0000 Mychaela Falconia duart28 MCL: resistors captured
Sat, 04 Jul 2020 22:02:49 +0000 Mychaela Falconia duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
Sat, 04 Jul 2020 21:50:10 +0000 Mychaela Falconia duart28 MCL: capacitors captured
Mon, 29 Jun 2020 03:15:08 +0000 Mychaela Falconia duart28: U5 & U6 preliminary slotmaps
Sun, 28 Jun 2020 22:06:24 +0000 Mychaela Falconia duart28: new design ideas
Sat, 13 Jun 2020 18:12:28 +0000 Mychaela Falconia duart28 MCL: ferrite bead defined
Sat, 13 Jun 2020 17:46:18 +0000 Mychaela Falconia duart28 MCL: crystal defined
Sat, 13 Jun 2020 06:57:04 +0000 Mychaela Falconia duart28 MCL: beginning of hier= mapping
Sat, 13 Jun 2020 06:46:05 +0000 Mychaela Falconia duart28/src/vsrc/board.v: aux_5V added
Sat, 13 Jun 2020 06:38:05 +0000 Mychaela Falconia duart28: vsrc passes sverp
Sat, 13 Jun 2020 05:28:01 +0000 Mychaela Falconia duart28/src/primitives: adapted from fc-uja
Sat, 13 Jun 2020 05:18:55 +0000 Mychaela Falconia duart28 MCL: added 2-pin header for misc-use 5V
Sat, 13 Jun 2020 05:12:39 +0000 Mychaela Falconia duart28 project started
Sat, 09 May 2020 08:13:26 +0000 Mychaela Falconia lunakpd1/pcb/Makefile added