log

age author description
2021-06-25 Mychaela Falconia lunalcd2.pcb: manual DRC fixes
2021-06-25 Mychaela Falconia lunalcd2.pcb complete except for DRC
2021-06-25 Mychaela Falconia lunalcd2.pcb almost complete
2021-06-25 Mychaela Falconia lunalcd2.pcb started
2021-06-25 Mychaela Falconia lunalcd2/src/Makefile: generate elements.pcb
2021-06-25 Mychaela Falconia lunalcd2/src/Makefile: generate pcb-netlist.txt
2021-06-25 Mychaela Falconia lunalcd2: MCL binding complete
2021-06-25 Mychaela Falconia lunalcd2: structural Verilog source captured
2021-06-25 Mychaela Falconia lunalcd2: footprint for the DIP switch pack
2021-06-23 Mychaela Falconia lunalcd2 project started with MCL
2021-06-23 Mychaela Falconia lunakpd1/README added
2021-06-23 Mychaela Falconia lunalcd[12]/README written
2021-06-22 Mychaela Falconia lcr0402: add Makefile
2021-06-22 Mychaela Falconia lcr0402 project started
2020-08-02 Mychaela Falconia duart28c/src/MCL: update for Digi-Key parts actually on order
2020-07-29 Mychaela Falconia duart28c/src/Makefile: U7.slotmap dependency was missed