| Wed, 29 Jul 2020 07:21:04 +0000 |
Mychaela Falconia |
duart28c MCL: new components added
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| Wed, 29 Jul 2020 07:08:28 +0000 |
Mychaela Falconia |
duart28c: started with a copy from duart28
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| Tue, 28 Jul 2020 17:54:56 +0000 |
Mychaela Falconia |
duart28: another U5 slot change
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| Tue, 28 Jul 2020 17:01:37 +0000 |
Mychaela Falconia |
duart28: U5 & U6 slot change by PCB layout engineer
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| Fri, 24 Jul 2020 23:27:57 +0000 |
Mychaela Falconia |
duart28/how-to-compile added
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| Fri, 24 Jul 2020 23:23:42 +0000 |
Mychaela Falconia |
duart28/pcb: starting point for layout job
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| Fri, 24 Jul 2020 20:22:36 +0000 |
Mychaela Falconia |
duart28/design-spec: layout instructions added
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| Fri, 24 Jul 2020 20:21:54 +0000 |
Mychaela Falconia |
duart28/src/Makefile: added dependency on U[56].slotmap
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| Fri, 24 Jul 2020 20:20:55 +0000 |
Mychaela Falconia |
duart28/src/MCL: value attribute was wrong on the tantalum cap
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| Thu, 23 Jul 2020 19:49:00 +0000 |
Mychaela Falconia |
duart28/design-spec: circuit description should be complete
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| Thu, 23 Jul 2020 18:14:16 +0000 |
Mychaela Falconia |
duart28/design-spec: re-measured partial power-down current
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| Thu, 23 Jul 2020 06:59:32 +0000 |
Mychaela Falconia |
duart28/design-spec: coming along
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| Tue, 14 Jul 2020 19:01:29 +0000 |
Mychaela Falconia |
duart28/design-spec: minor fixes in the so-far-written section
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| Tue, 14 Jul 2020 07:40:42 +0000 |
Mychaela Falconia |
duart28/design-spec started
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| Sun, 05 Jul 2020 00:10:45 +0000 |
Mychaela Falconia |
duart28/src/Makefile: netlist MCL binding added
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| Sat, 04 Jul 2020 23:37:47 +0000 |
Mychaela Falconia |
duart28 MCL: resistors captured
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| Sat, 04 Jul 2020 22:02:49 +0000 |
Mychaela Falconia |
duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
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| Sat, 04 Jul 2020 21:50:10 +0000 |
Mychaela Falconia |
duart28 MCL: capacitors captured
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| Mon, 29 Jun 2020 03:15:08 +0000 |
Mychaela Falconia |
duart28: U5 & U6 preliminary slotmaps
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| Sun, 28 Jun 2020 22:06:24 +0000 |
Mychaela Falconia |
duart28: new design ideas
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| Sat, 13 Jun 2020 18:12:28 +0000 |
Mychaela Falconia |
duart28 MCL: ferrite bead defined
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| Sat, 13 Jun 2020 17:46:18 +0000 |
Mychaela Falconia |
duart28 MCL: crystal defined
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| Sat, 13 Jun 2020 06:57:04 +0000 |
Mychaela Falconia |
duart28 MCL: beginning of hier= mapping
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| Sat, 13 Jun 2020 06:46:05 +0000 |
Mychaela Falconia |
duart28/src/vsrc/board.v: aux_5V added
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| Sat, 13 Jun 2020 06:38:05 +0000 |
Mychaela Falconia |
duart28: vsrc passes sverp
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| Sat, 13 Jun 2020 05:28:01 +0000 |
Mychaela Falconia |
duart28/src/primitives: adapted from fc-uja
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| Sat, 13 Jun 2020 05:18:55 +0000 |
Mychaela Falconia |
duart28 MCL: added 2-pin header for misc-use 5V
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| Sat, 13 Jun 2020 05:12:39 +0000 |
Mychaela Falconia |
duart28 project started
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| Sat, 09 May 2020 08:13:26 +0000 |
Mychaela Falconia |
lunakpd1/pcb/Makefile added
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| Sat, 09 May 2020 08:08:42 +0000 |
Mychaela Falconia |
lunakpd1.pcb complete
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| Sat, 09 May 2020 06:40:15 +0000 |
Mychaela Falconia |
lunakpd1.pcb: keypad layout complete
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| Sat, 09 May 2020 06:08:40 +0000 |
Mychaela Falconia |
lunakpd1: beginning of sensible layout
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| Sat, 09 May 2020 05:11:54 +0000 |
Mychaela Falconia |
lunakpd1 placetool written
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| Sat, 09 May 2020 04:00:24 +0000 |
Mychaela Falconia |
lunakpd1.pcb started
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| Sat, 09 May 2020 00:38:07 +0000 |
Mychaela Falconia |
lunakpd1 project started
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| Fri, 03 Apr 2020 00:02:03 +0000 |
Mychaela Falconia |
lunalcd1/pcb/Makefile added
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| Thu, 02 Apr 2020 23:26:47 +0000 |
Mychaela Falconia |
lunalcd1.pcb: should be complete
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| Thu, 02 Apr 2020 22:41:19 +0000 |
Mychaela Falconia |
lunalcd1.pcb: layout started, close to complete
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| Thu, 02 Apr 2020 18:25:19 +0000 |
Mychaela Falconia |
lunalcd1: added pull-down resistor on BL_EN line
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| Wed, 01 Apr 2020 21:14:56 +0000 |
Mychaela Falconia |
lunalcd1: updated footprint for LDO regulator
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| Wed, 01 Apr 2020 21:13:21 +0000 |
Mychaela Falconia |
lunalcd1: backlight resistors changed to 38.3R
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| Wed, 01 Apr 2020 16:52:34 +0000 |
Mychaela Falconia |
lunalcd1/src/MCL: use new FPC connector + LCD module footprint
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| Sun, 22 Mar 2020 03:19:38 +0000 |
Mychaela Falconia |
lunalcd1 board project started
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| Tue, 10 Dec 2019 06:56:59 +0000 |
Mychaela Falconia |
mmtb1/pcb: added Makefile for fab output generation
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| Tue, 10 Dec 2019 06:51:02 +0000 |
Mychaela Falconia |
mmtb1.pcb: silk text markings added
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| Tue, 10 Dec 2019 06:12:04 +0000 |
Mychaela Falconia |
mmtb1.pcb: DRC fixed to pass
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| Mon, 21 Oct 2019 01:02:20 +0000 |
Mychaela Falconia |
.hgignore added, based on freecalypso-schem version
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| Mon, 21 Oct 2019 00:53:38 +0000 |
Mychaela Falconia |
fc-small-hw separated from old freecalypso-schem repo
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