log

age author description
Thu, 23 Jul 2020 19:49:00 +0000 Mychaela Falconia duart28/design-spec: circuit description should be complete
Thu, 23 Jul 2020 18:14:16 +0000 Mychaela Falconia duart28/design-spec: re-measured partial power-down current
Thu, 23 Jul 2020 06:59:32 +0000 Mychaela Falconia duart28/design-spec: coming along
Tue, 14 Jul 2020 19:01:29 +0000 Mychaela Falconia duart28/design-spec: minor fixes in the so-far-written section
Tue, 14 Jul 2020 07:40:42 +0000 Mychaela Falconia duart28/design-spec started
Sun, 05 Jul 2020 00:10:45 +0000 Mychaela Falconia duart28/src/Makefile: netlist MCL binding added
Sat, 04 Jul 2020 23:37:47 +0000 Mychaela Falconia duart28 MCL: resistors captured
Sat, 04 Jul 2020 22:02:49 +0000 Mychaela Falconia duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
Sat, 04 Jul 2020 21:50:10 +0000 Mychaela Falconia duart28 MCL: capacitors captured
Mon, 29 Jun 2020 03:15:08 +0000 Mychaela Falconia duart28: U5 & U6 preliminary slotmaps
Sun, 28 Jun 2020 22:06:24 +0000 Mychaela Falconia duart28: new design ideas
Sat, 13 Jun 2020 18:12:28 +0000 Mychaela Falconia duart28 MCL: ferrite bead defined
Sat, 13 Jun 2020 17:46:18 +0000 Mychaela Falconia duart28 MCL: crystal defined
Sat, 13 Jun 2020 06:57:04 +0000 Mychaela Falconia duart28 MCL: beginning of hier= mapping
Sat, 13 Jun 2020 06:46:05 +0000 Mychaela Falconia duart28/src/vsrc/board.v: aux_5V added