| Fri, 25 Jun 2021 18:44:11 +0000 |
Mychaela Falconia |
lunalcd2: structural Verilog source captured
|
| Fri, 25 Jun 2021 17:12:02 +0000 |
Mychaela Falconia |
lunalcd2: footprint for the DIP switch pack
|
| Wed, 23 Jun 2021 23:53:15 +0000 |
Mychaela Falconia |
lunalcd2 project started with MCL
|
| Wed, 23 Jun 2021 08:44:43 +0000 |
Mychaela Falconia |
lunakpd1/README added
|
| Wed, 23 Jun 2021 08:23:10 +0000 |
Mychaela Falconia |
lunalcd[12]/README written
|
| Tue, 22 Jun 2021 05:27:16 +0000 |
Mychaela Falconia |
lcr0402: add Makefile
|
| Tue, 22 Jun 2021 05:20:42 +0000 |
Mychaela Falconia |
lcr0402 project started
|
| Sun, 02 Aug 2020 20:51:27 +0000 |
Mychaela Falconia |
duart28c/src/MCL: update for Digi-Key parts actually on order
|
| Wed, 29 Jul 2020 15:53:57 +0000 |
Mychaela Falconia |
duart28c/src/Makefile: U7.slotmap dependency was missed
|
| Wed, 29 Jul 2020 07:59:20 +0000 |
Mychaela Falconia |
duart28c: new parts added to netlist
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| Wed, 29 Jul 2020 07:30:45 +0000 |
Mychaela Falconia |
duart28c/src/primitives: OD buffer pieces added
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| Wed, 29 Jul 2020 07:27:14 +0000 |
Mychaela Falconia |
duart28c: 74LVC2G07 pinout captured
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| Wed, 29 Jul 2020 07:21:04 +0000 |
Mychaela Falconia |
duart28c MCL: new components added
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| Wed, 29 Jul 2020 07:08:28 +0000 |
Mychaela Falconia |
duart28c: started with a copy from duart28
|
| Tue, 28 Jul 2020 17:54:56 +0000 |
Mychaela Falconia |
duart28: another U5 slot change
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| Tue, 28 Jul 2020 17:01:37 +0000 |
Mychaela Falconia |
duart28: U5 & U6 slot change by PCB layout engineer
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| Fri, 24 Jul 2020 23:27:57 +0000 |
Mychaela Falconia |
duart28/how-to-compile added
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| Fri, 24 Jul 2020 23:23:42 +0000 |
Mychaela Falconia |
duart28/pcb: starting point for layout job
|
| Fri, 24 Jul 2020 20:22:36 +0000 |
Mychaela Falconia |
duart28/design-spec: layout instructions added
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| Fri, 24 Jul 2020 20:21:54 +0000 |
Mychaela Falconia |
duart28/src/Makefile: added dependency on U[56].slotmap
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| Fri, 24 Jul 2020 20:20:55 +0000 |
Mychaela Falconia |
duart28/src/MCL: value attribute was wrong on the tantalum cap
|
| Thu, 23 Jul 2020 19:49:00 +0000 |
Mychaela Falconia |
duart28/design-spec: circuit description should be complete
|
| Thu, 23 Jul 2020 18:14:16 +0000 |
Mychaela Falconia |
duart28/design-spec: re-measured partial power-down current
|
| Thu, 23 Jul 2020 06:59:32 +0000 |
Mychaela Falconia |
duart28/design-spec: coming along
|
| Tue, 14 Jul 2020 19:01:29 +0000 |
Mychaela Falconia |
duart28/design-spec: minor fixes in the so-far-written section
|
| Tue, 14 Jul 2020 07:40:42 +0000 |
Mychaela Falconia |
duart28/design-spec started
|
| Sun, 05 Jul 2020 00:10:45 +0000 |
Mychaela Falconia |
duart28/src/Makefile: netlist MCL binding added
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| Sat, 04 Jul 2020 23:37:47 +0000 |
Mychaela Falconia |
duart28 MCL: resistors captured
|
| Sat, 04 Jul 2020 22:02:49 +0000 |
Mychaela Falconia |
duart28: added bypass caps on FT2232D VCCIOA & VCCIOB
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| Sat, 04 Jul 2020 21:50:10 +0000 |
Mychaela Falconia |
duart28 MCL: capacitors captured
|
