log

age author description
Fri, 25 Jun 2021 19:08:13 +0000 Mychaela Falconia lunalcd2/src/Makefile: generate pcb-netlist.txt
Fri, 25 Jun 2021 19:01:35 +0000 Mychaela Falconia lunalcd2: MCL binding complete
Fri, 25 Jun 2021 18:44:11 +0000 Mychaela Falconia lunalcd2: structural Verilog source captured