log

age author description
2021-06-25 Mychaela Falconia lunalcd2/src/Makefile: generate pcb-netlist.txt
2021-06-25 Mychaela Falconia lunalcd2: MCL binding complete
2021-06-25 Mychaela Falconia lunalcd2: structural Verilog source captured
2021-06-25 Mychaela Falconia lunalcd2: footprint for the DIP switch pack
2021-06-23 Mychaela Falconia lunalcd2 project started with MCL
2021-06-23 Mychaela Falconia lunakpd1/README added
2021-06-23 Mychaela Falconia lunalcd[12]/README written
2021-06-22 Mychaela Falconia lcr0402: add Makefile
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