FreeCalypso > hg > fc-tourmaline
annotate src/cs/layer1/tpu_drivers/source0/tpudrv8.h @ 220:0ed36de51973
ABB semaphore protection overhaul
The ABB semaphone protection logic that came with TCS211 from TI
was broken in several ways:
* Some semaphore-protected functions were called from Application_Initialize()
context. NU_Obtain_Semaphore() called with NU_SUSPEND fails with
NU_INVALID_SUSPEND in this context, but the return value wasn't checked,
and NU_Release_Semaphore() would be called unconditionally at the end.
The latter call would increment the semaphore count past 1, making the
semaphore no longer binary and thus no longer effective for resource
protection. The fix is to check the return value from NU_Obtain_Semaphore()
and skip the NU_Release_Semaphore() call if the semaphore wasn't properly
obtained.
* Some SPI hardware manipulation was being done before entering the semaphore-
protected critical section. The fix is to reorder the code: first obtain
the semaphore, then do everything else.
* In the corner case of L1/DSP recovery, l1_abb_power_on() would call some
non-semaphore-protected ABB & SPI init functions. The fix is to skip those
calls in the case of recovery.
* A few additional corner cases existed, all of which are fixed by making
ABB semaphore protection 100% consistent for all ABB functions and code paths.
There is still one remaining problem of priority inversion: suppose a low-
priority task calls an ABB function, and some medium-priority task just happens
to preempt right in the middle of that semaphore-protected ABB operation. Then
the high-priority SPI task is locked out for a non-deterministic time until
that medium-priority task finishes its work and goes back to sleep. This
priority inversion problem remains outstanding for now.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Mon, 26 Apr 2021 20:55:25 +0000 |
parents | 4e78acac3d88 |
children |
rev | line source |
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0
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src/{condat,cs,gpf,nucleus}: import from Selenite
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parents:
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1 /****************** Revision Controle System Header *********************** |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 * GSM Layer 1 software |
4e78acac3d88
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3 * Copyright (c) Texas Instruments 1998 |
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4 * |
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5 * Filename tpudrv8.h |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 * Copyright 2003 (C) Texas Instruments |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 * |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 ****************** Revision Controle System Header ***********************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 //SI4133 definitions |
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Mychaela Falconia <falcon@freecalypso.org>
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11 #define WordAdd0000 0x000000 //Main Configuration |
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12 #define AutoPDB 0x000080 //Auto Power Down - Uses PWDNB pin |
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13 #define AuxSel 0x030000 //Auxiliary output pin use = LOCK Detect |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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14 #define WordAdd0011 0x000003 //RF1 N Divider |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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15 #define WordAdd0100 0x000004 //RF2 N Divider |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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16 #define WordAdd0101 0x000005 //IF N Divider |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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17 #define RFPWR 0x000020 //RF LO high power |
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18 #define XPDM 0x000100 //Reference amplifier ON when PWDNB pin = 0 |
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Mychaela Falconia <falcon@freecalypso.org>
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19 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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20 //TRF6053 definitions |
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Mychaela Falconia <falcon@freecalypso.org>
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21 #define Mode0 0x000000 |
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22 #define Mode1 0x000001 |
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23 #define Mode2 0x000003 |
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24 #define Mode3 0x000005 |
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25 #define Mode4 0x000007 |
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26 #define LNAMixPwrOn 0x000080 //Mode0 |
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Mychaela Falconia <falcon@freecalypso.org>
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27 #define VCODiv2PwrOn 0x000040 //Mode0 |
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Mychaela Falconia <falcon@freecalypso.org>
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28 #define RXBBIFStgPwrOn 0x000020 //Mode0 |
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Mychaela Falconia <falcon@freecalypso.org>
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29 #define OFFStrCalOn 0x000010 //Mode0 |
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Mychaela Falconia <falcon@freecalypso.org>
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30 #define VCORDivPwrOn 0x000008 //Mode0 |
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31 #define MixLOBuffPwrOn 0x000004 //Mode0 |
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32 #define TXStagesPwrOn 0x000002 //Mode0 |
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Mychaela Falconia <falcon@freecalypso.org>
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33 #define FreqDetDis 0x000400 //Mode4 |
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Mychaela Falconia <falcon@freecalypso.org>
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34 #define IFVCOExternal 0x000200 //Mode4 |
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Mychaela Falconia <falcon@freecalypso.org>
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35 #define IFPLLBuffDis 0x000100 //Mode4 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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36 #define LBandLNAExt 0x000080 //Mode4 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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37 #define HBandLNAExt 0x000040 //Mode4 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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38 #define Div2ToRXStgs 0x000020 //Mode4 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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39 #define DivRToTXStgs 0x000010 //Mode4 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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40 #define ChgPPLBNeg 0x000010 //Mode2 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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41 #define ChgPPHBNeg 0x000010 //Mode3 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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42 #define PreCCLBDis 0x000008 //Mode2 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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43 #define PreCCHBDis 0x000008 //Mode3 |
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Mychaela Falconia <falcon@freecalypso.org>
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44 #define LNAGainLow 0x000010 //Mode2 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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45 #define BandHigh 0x000008 //Mode1 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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46 #define LowBIF610 0x000020 //Mode2 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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47 #define HighBIF412 0x000020 //Mode3 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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48 #define HighBIF25 0x000040 //Mode3 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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49 #define HighBIF410 0x000060 //Mode3 |
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50 |
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51 /*------------------------------------------*/ |
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Mychaela Falconia <falcon@freecalypso.org>
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52 /* Download delay values */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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53 /*------------------------------------------*/ |
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Mychaela Falconia <falcon@freecalypso.org>
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54 #define TRF6053_DOWNLOAD_TIME 15 |
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Mychaela Falconia <falcon@freecalypso.org>
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55 #define SYNTH_DOWNLOAD_TIME 20 |
4e78acac3d88
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56 |
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57 //-------------------------------------------- |
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Mychaela Falconia <falcon@freecalypso.org>
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58 // internal tpu timing |
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59 //-------------------------------------------- |
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60 |
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61 #define DLT_1 1 // 1 tpu instruction = 1 qbit |
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62 #define DLT_2 2 |
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Mychaela Falconia <falcon@freecalypso.org>
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63 #define DLT_3 3 |
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Mychaela Falconia <falcon@freecalypso.org>
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64 #define DLT_4 4 |
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65 |
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66 #define DLT_1B 4 // 3*move + 1*byte (download) |
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67 #define DLT_2B 6 // 4*move + 2*byte |
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68 #define DLT_3B 8 // 5*move + 3*byte |
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69 |
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70 #define SL_SU_DELAY1 4 // No. bits to send + load data to shift + send write cmd + 1 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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71 #define SL_SU_DELAY2 3 // load data to shift + send write cmd + 1 |
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72 #define SL_SU_DELAY3 5 // SL_SU_DELAY1 + serialization |
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73 |
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74 /*------------------------------------------*/ |
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75 /* Download delay values */ |
4e78acac3d88
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76 /*------------------------------------------*/ |
4e78acac3d88
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77 // 0.9230769 usec ~ 1 qbit i.e. 200 usec is ~ 217 qbit |
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78 |
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79 #define T TPU_CLOCK_RANGE // TODO: should be a define from L1. |
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80 |
4e78acac3d88
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81 // time below are offset to when BDLENA goes low |
4e78acac3d88
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82 #define TRF_R11 ( 0 - DLT_1B) // disable BDLON & BDLENA |
4e78acac3d88
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83 #define TRF_R10 ( - 5 - DLT_1B) // disable TRF6053 |
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84 |
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85 // burst data comes here |
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Mychaela Falconia <falcon@freecalypso.org>
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86 // time below are offset to when BDLENA goes high |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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87 #define TRF_R9 (PROVISION_TIME - 0 - DLT_1B) // enable BDLENA, disable BDLCAL |
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Mychaela Falconia <falcon@freecalypso.org>
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88 #define TRF_R8 (PROVISION_TIME - 11 - DLT_1B) // power on RX front end, DC cal. off |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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89 #define TRF_R7 (PROVISION_TIME - 65 - DLT_1B) // enable BDLCAL |
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Mychaela Falconia <falcon@freecalypso.org>
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90 #define TRF_R6 (PROVISION_TIME - 72 - DLT_1B) // enable BDLON |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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91 #define TRF_R5 (PROVISION_TIME - 76 - DLT_1B) // power on receiver, start DC cal. |
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Mychaela Falconia <falcon@freecalypso.org>
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92 #define TRF_R4 (PROVISION_TIME - 80 - DLT_2B) // set RX gain & band. |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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93 // ADC read, uses min 11 qbit due to 5 wait |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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94 #define TRF_R3 (PROVISION_TIME - 196 - DLT_1B) // power up TRF2253 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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95 #define TRF_R1 (PROVISION_TIME - 205 - DLT_3B) // set RF PLL N counter = r1 and IF PLL N counter in TRF2253 = r2 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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96 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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97 // time below are offset to when BULENA goes low |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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98 #define TRF_T13 ( 32 - DLT_1B) // disable PA_ON, BULON, TRF6053 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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99 #define TRF_T12 ( 18 - DLT_1 ) // disable TSPACT01 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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100 #define TRF_T11 ( 0 - DLT_1B) // disable BULENA |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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101 #define TRF_T10_1 (- 40 - DLT_1B) // ADC read |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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102 // burst data comes here |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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103 // time below are offset to when BULENA goes high |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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104 #define TRF_T10 (+ 15 - DLT_3) // enable PA_ON + 2*rfswitch |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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105 #define TRF_T9 (- 0 - DLT_1B) // enable BULENA |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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106 #define TRF_T8 (- 109 - DLT_2B) // power on transceiver |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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107 #define TRF_T7 (- 115 - DLT_1B) // disable BULCAL |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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108 #define TRF_T6 (- 230 - DLT_1B) // power up TRF2253 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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109 #define TRF_T5 (- 233 - DLT_2B) // set TX band in TRF6053 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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110 #define TRF_T3 (- 249 - DLT_3B) // set RF PLL N counter = t3 and IF PLL N counter in TRF2253 = t4 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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111 #define TRF_T2 (- 260 - DLT_1B) // enable BULCAL |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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112 #define TRF_T1 (- 278 - DLT_1B) // enable BULON |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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113 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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114 #if (BOARD == 7) || (BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45) |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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115 #define PA_ON 0x20 // act5 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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116 #define TSPACT01 0x02 // act1 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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117 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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118 // RF signals connected to TSPACTX |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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119 #define RX900 0x04 // act10 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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120 #define RX1800 0x08 // act11 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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121 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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122 #define TC1_DEVICE_ABB TC1_DEVICE0 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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123 #define TC1_DEVICE_RF TC1_DEVICE1 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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124 #define TC1_DEVICE_PLL TC1_DEVICE2 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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125 #endif |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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126 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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127 #if (BOARD == 6) |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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128 #define PA_ON 0x10 // act4 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
129 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
130 // RF signals connected to TSPACTX |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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131 #define RX900 0x08 // act11 => needs to be connected to act12 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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132 #define RX1800 0x04 // act10 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
133 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
134 #define TC1_DEVICE_ABB TC1_DEVICE0 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
135 #define TC1_DEVICE_PLL TC1_DEVICE1 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
136 #define TC1_DEVICE_RF TC1_DEVICE2 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
137 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
138 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
139 #ifdef TPUDRV8_C |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
140 // Function prototypes |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 SYS_UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq); |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 |
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src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
143 #endif |