FreeCalypso > hg > fc-tourmaline
annotate src/cs/layer1/include/l1_rtt_macro.h @ 155:1de0238e3223
mmiMelody_data.c: header comment formatting fixes
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 16 Nov 2020 19:59:46 +0000 |
parents | 4e78acac3d88 |
children |
rev | line source |
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0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1_RTT_MACRO.H |
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4 * |
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5 * Filename %M% |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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parents:
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9 |
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10 #if (defined RVM_RTT_SWE || (OP_L1_STANDALONE == 1)) |
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11 |
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12 #include "rvt_gen.h" |
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13 #include "rtt_gen.h" |
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14 |
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15 extern T_TRACE_INFO_STRUCT trace_info; |
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16 |
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17 /***********************************************************************************************************/ |
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18 /* Macro for cell enabling checking */ |
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19 /***********************************************************************************************************/ |
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20 |
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21 #define SELECTED_BITMAP(enable_bit) \ |
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22 enable_bit < 32 ? (0x0001 << (enable_bit - 0)) & trace_info.current_config->rttl1_cell_enable[0] : \ |
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23 enable_bit < 64 ? (0x0001 << (enable_bit - 32)) & trace_info.current_config->rttl1_cell_enable[1] : \ |
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24 enable_bit < 96 ? (0x0001 << (enable_bit - 64)) & trace_info.current_config->rttl1_cell_enable[2] : \ |
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25 enable_bit < 128 ? (0x0001 << (enable_bit - 96)) & trace_info.current_config->rttl1_cell_enable[3] : \ |
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26 enable_bit < 160 ? (0x0001 << (enable_bit - 128)) & trace_info.current_config->rttl1_cell_enable[4] : \ |
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27 enable_bit < 192 ? (0x0001 << (enable_bit - 160)) & trace_info.current_config->rttl1_cell_enable[5] : \ |
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28 enable_bit < 224 ? (0x0001 << (enable_bit - 192)) & trace_info.current_config->rttl1_cell_enable[6] : \ |
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29 (0x0001 << (enable_bit - 224)) & trace_info.current_config->rttl1_cell_enable[7] |
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30 |
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31 /***********************************************************************************************************/ |
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32 /* Macros for buffer filling */ |
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33 /***********************************************************************************************************/ |
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34 |
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35 //----------------------------------------------------------------------------------------------------------- |
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36 // L1 RTT cell filling: FN |
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37 |
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38 #define RTTL1_FILL_FN(param1) \ |
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39 if(SELECTED_BITMAP(RTTL1_ENABLE_FN)) \ |
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40 { \ |
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41 T_RTT_PTR ptr; \ |
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42 \ |
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43 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_FN))) != NULL) \ |
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44 { \ |
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45 ((T_RTTL1_FN *)ptr)->fn = param1; \ |
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46 ((T_RTTL1_FN *)ptr)->cell_id = RTTL1_ENABLE_FN; \ |
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47 } \ |
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48 } |
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49 |
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50 //----------------------------------------------------------------------------------------------------------- |
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51 // L1 RTT cell filling: Downlink burst |
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52 |
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53 #define RTTL1_FILL_DL_BURST(param1,param2,param3,param4,param5,param6,param7) \ |
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54 if(SELECTED_BITMAP(RTTL1_ENABLE_DL_BURST)) \ |
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55 { \ |
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56 T_RTT_PTR ptr; \ |
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57 \ |
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58 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_BURST))) != NULL) \ |
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59 { \ |
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60 ((T_RTTL1_DL_BURST *)ptr)->angle = param1; \ |
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61 ((T_RTTL1_DL_BURST *)ptr)->snr = param2; \ |
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62 ((T_RTTL1_DL_BURST *)ptr)->afc = param3; \ |
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63 ((T_RTTL1_DL_BURST *)ptr)->task = param4; \ |
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64 ((T_RTTL1_DL_BURST *)ptr)->pm = param5; \ |
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65 ((T_RTTL1_DL_BURST *)ptr)->toa = param6; \ |
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66 ((T_RTTL1_DL_BURST *)ptr)->input_level = param7; \ |
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67 ((T_RTTL1_DL_BURST *)ptr)->cell_id = RTTL1_ENABLE_DL_BURST; \ |
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68 } \ |
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69 } |
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70 |
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71 //----------------------------------------------------------------------------------------------------------- |
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72 // L1 RTT cell filling: Uplink Normal Burst |
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73 |
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74 #define RTTL1_FILL_UL_NB(param1, param2, param3) \ |
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75 if(SELECTED_BITMAP(RTTL1_ENABLE_UL_NB)) \ |
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76 { \ |
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77 T_RTT_PTR ptr; \ |
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78 \ |
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79 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_NB))) != NULL) \ |
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80 { \ |
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81 ((T_RTTL1_UL_NB *)ptr)->task = param1; \ |
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82 ((T_RTTL1_UL_NB *)ptr)->ta = param2; \ |
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83 ((T_RTTL1_UL_NB *)ptr)->txpwr = param3; \ |
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84 ((T_RTTL1_UL_NB *)ptr)->cell_id = RTTL1_ENABLE_UL_NB; \ |
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85 } \ |
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86 } |
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87 |
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88 //----------------------------------------------------------------------------------------------------------- |
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89 // L1 RTT cell filling: Uplink Access Burst |
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90 |
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91 #define RTTL1_FILL_UL_AB(param1, param2) \ |
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92 if(SELECTED_BITMAP(RTTL1_ENABLE_UL_AB)) \ |
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93 { \ |
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94 T_RTT_PTR ptr; \ |
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95 \ |
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96 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_AB))) != NULL) \ |
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97 { \ |
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98 ((T_RTTL1_UL_AB *)ptr)->task = param1; \ |
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99 ((T_RTTL1_UL_AB *)ptr)->txpwr = param2; \ |
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changeset
|
100 ((T_RTTL1_UL_AB *)ptr)->cell_id = RTTL1_ENABLE_UL_AB; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
101 } \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
102 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
103 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
104 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
105 // L1 RTT cell filling: Full list measurement |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
106 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
107 #define RTTL1_FILL_FULL_LIST_MEAS(param1, param2, param3, param4) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
108 if(SELECTED_BITMAP(RTTL1_ENABLE_FULL_LIST_MEAS)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
109 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
110 T_RTT_PTR ptr; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
111 \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
112 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_FULL_LIST_MEAS))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
113 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
114 ((T_RTTL1_FULL_LIST_MEAS *)ptr)->pm = param1; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
115 ((T_RTTL1_FULL_LIST_MEAS *)ptr)->input_level = param2; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
116 ((T_RTTL1_FULL_LIST_MEAS *)ptr)->task = param3; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
117 ((T_RTTL1_FULL_LIST_MEAS *)ptr)->radio_freq = param4; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
118 ((T_RTTL1_FULL_LIST_MEAS *)ptr)->cell_id = RTTL1_ENABLE_FULL_LIST_MEAS; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
119 } \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
120 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
121 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
122 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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123 // L1 RTT cell filling: Full list measurement |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
124 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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125 #define RTTL1_FILL_MON_MEAS(param1, param2, param3, param4) \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
126 if(SELECTED_BITMAP(RTTL1_ENABLE_MON_MEAS)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
127 { \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
128 T_RTT_PTR ptr; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
129 \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
130 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MON_MEAS))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
131 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
132 ((T_RTTL1_MON_MEAS *)ptr)->pm = param1; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
133 ((T_RTTL1_MON_MEAS *)ptr)->input_level = param2; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
134 ((T_RTTL1_MON_MEAS *)ptr)->task = param3; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
135 ((T_RTTL1_MON_MEAS *)ptr)->radio_freq = param4; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
136 ((T_RTTL1_MON_MEAS *)ptr)->cell_id = RTTL1_ENABLE_MON_MEAS; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
137 } \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
138 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
139 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
140 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 // L1 RTT cell filling: Downlink DCCH block |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
143 #define RTTL1_FILL_DL_DCCH(param1, param2) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
144 if(SELECTED_BITMAP(RTTL1_ENABLE_DL_DCCH)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
145 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 T_RTT_PTR ptr; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
148 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_DCCH))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
149 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
150 ((T_RTTL1_DL_DCCH *)ptr)->valid_flag = param1; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
151 ((T_RTTL1_DL_DCCH *)ptr)->physical_info = param2; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
152 ((T_RTTL1_DL_DCCH *)ptr)->cell_id = RTTL1_ENABLE_DL_DCCH; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
153 } \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
154 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 // L1 RTT cell filling: Downlink PTCCH block |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 #define RTTL1_FILL_DL_PTCCH(param1, param2) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 if(SELECTED_BITMAP(RTTL1_ENABLE_DL_PTCCH)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 T_RTT_PTR ptr; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
163 \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_PTCCH))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 ((T_RTTL1_DL_PTCCH *)ptr)->crc = param1; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 ((T_RTTL1_DL_PTCCH *)ptr)->ordered_ta = param2; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 ((T_RTTL1_DL_PTCCH *)ptr)->cell_id = RTTL1_ENABLE_DL_PTCCH; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 } \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 // L1 RTT cell filling: Uplink DCCH block |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 #define RTTL1_FILL_UL_DCCH \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 if(SELECTED_BITMAP(RTTL1_ENABLE_UL_DCCH)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 T_RTT_PTR ptr; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_DCCH))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 ((T_RTTL1_UL_DCCH *)ptr)->cell_id = RTTL1_ENABLE_UL_DCCH; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 } \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 // L1 RTT cell filling: Uplink SACCH block |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
189 #define RTTL1_FILL_UL_SACCH(param1, param2, param3) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
190 if(SELECTED_BITMAP(RTTL1_ENABLE_UL_SACCH)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 T_RTT_PTR ptr; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
193 \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
194 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_SACCH))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
195 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
196 ((T_RTTL1_UL_SACCH *)ptr)->data_present = param1; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
197 ((T_RTTL1_UL_SACCH *)ptr)->reported_ta = param2; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
198 ((T_RTTL1_UL_SACCH *)ptr)->reported_txpwr = param3; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
199 ((T_RTTL1_UL_SACCH *)ptr)->cell_id = RTTL1_ENABLE_UL_SACCH; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
200 } \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
201 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
202 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
203 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
204 // L1 RTT cell filling: Downlink PDTCH block |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
205 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
206 #define RTTL1_FILL_DL_PDTCH(param1, param2, param3, param4, param5) \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
207 if(SELECTED_BITMAP(RTTL1_ENABLE_DL_PDTCH)) \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
208 { \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
209 T_RTT_PTR ptr; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
210 \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
211 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_PDTCH))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
212 { \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
213 ((T_RTTL1_DL_PDTCH *)ptr)->mac_header = param1; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
214 ((T_RTTL1_DL_PDTCH *)ptr)->tfi_result = param2; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
215 ((T_RTTL1_DL_PDTCH *)ptr)->crc = param3; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
216 ((T_RTTL1_DL_PDTCH *)ptr)->cs_type = param4; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
217 ((T_RTTL1_DL_PDTCH *)ptr)->timeslot = param5; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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218 ((T_RTTL1_DL_PDTCH *)ptr)->cell_id = RTTL1_ENABLE_DL_PDTCH; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
219 } \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
220 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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221 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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222 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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223 // L1 RTT cell filling: Uplink PDTCH block |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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224 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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225 #define RTTL1_FILL_UL_PDTCH(param1, param2, param3) \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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226 if(SELECTED_BITMAP(RTTL1_ENABLE_UL_PDTCH)) \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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227 { \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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228 T_RTT_PTR ptr; \ |
4e78acac3d88
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parents:
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229 \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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230 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_PDTCH))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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231 { \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
232 ((T_RTTL1_UL_PDTCH *)ptr)->cs_type = param1; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
233 ((T_RTTL1_UL_PDTCH *)ptr)->data_allowed = param2; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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234 ((T_RTTL1_UL_PDTCH *)ptr)->timeslot = param3; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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235 ((T_RTTL1_UL_PDTCH *)ptr)->cell_id = RTTL1_ENABLE_UL_PDTCH; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
236 } \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
237 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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238 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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239 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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240 // L1 RTT cell filling: MAC-S error |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
241 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
242 #define RTTL1_FILL_MACS_STATUS(param1, param2) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
243 if(SELECTED_BITMAP(RTTL1_ENABLE_MACS_STATUS)) \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
244 { \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
245 T_RTT_PTR ptr; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
246 \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
247 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MACS_STATUS))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
248 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
249 ((T_RTTL1_MACS_STATUS *)ptr)->status = param1; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
250 ((T_RTTL1_MACS_STATUS *)ptr)->timeslot = param2; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
251 ((T_RTTL1_MACS_STATUS *)ptr)->cell_id = RTTL1_ENABLE_MACS_STATUS; \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
252 } \ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
253 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
254 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
255 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
256 // L1 RTT cell filling: L1S task enable |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
257 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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258 #define RTTL1_FILL_L1S_TASK_ENABLE(param1, param2) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
259 if(SELECTED_BITMAP(RTTL1_ENABLE_L1S_TASK_ENABLE)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
260 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
261 T_RTT_PTR ptr; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
262 \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
263 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_L1S_TASK_ENABLE))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
264 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
265 ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->bitmap1 = param1; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
266 ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->bitmap2 = param2; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
267 ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->cell_id = RTTL1_ENABLE_L1S_TASK_ENABLE; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
268 } \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
269 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
270 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
271 //----------------------------------------------------------------------------------------------------------- |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
272 // L1 RTT cell filling: MFTAB trace |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
273 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
274 #define RTTL1_FILL_MFTAB(param1) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
275 if(SELECTED_BITMAP(RTTL1_ENABLE_MFTAB)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
276 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
277 T_RTT_PTR ptr; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
278 \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
279 if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MFTAB))) != NULL) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
280 { \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
281 ((T_RTTL1_MFTAB *)ptr)->func = param1; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
282 ((T_RTTL1_MFTAB *)ptr)->cell_id = RTTL1_ENABLE_MFTAB; \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
283 } \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
284 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
285 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
286 /***********************************************************************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
287 /* Macro for events */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
288 /***********************************************************************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
289 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
290 #define RTTL1_EVENT(id,size) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
291 if (trace_info.current_config->rttl1_event_enable & (0x1 << id)) \ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
292 trace_info.l1s_rtt_func.rtt_dump_buffer(trace_info.l1s_trace_user_id, size); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
293 #else // RVM_RTT_SWE || OP_L1_STANDALONE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
294 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
295 // No RTT: all macros are empty |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
296 #define SELECTED_BITMAP(enable_bit) (0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
297 #define RTTL1_FILL_FN(param1) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
298 #define RTTL1_FILL_DL_BURST(param1,param2,param3,param4,param5,param6,param7) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
299 #define RTTL1_FILL_UL_NB(param1, param2, param3) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
300 #define RTTL1_FILL_UL_AB(param1, param2) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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301 #define RTTL1_FILL_FULL_LIST_MEAS(param1, param2, param3, param4) |
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302 #define RTTL1_FILL_MON_MEAS(param1, param2, param3, param4) |
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303 #define RTTL1_FILL_DL_DCCH(param1, param2) |
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304 #define RTTL1_FILL_DL_PTCCH(param1, param2) |
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305 #define RTTL1_FILL_UL_DCCH |
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306 #define RTTL1_FILL_UL_SACCH(param1, param2, param3) |
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307 #define RTTL1_FILL_DL_PDTCH(param1, param2, param3, param4, param5) |
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308 #define RTTL1_FILL_UL_PDTCH(param1, param2, param3) |
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309 #define RTTL1_FILL_MACS_STATUS(param1, param2) |
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310 #define RTTL1_FILL_L1S_TASK_ENABLE(param1, param2) |
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311 #define RTTL1_FILL_MFTAB(param1) |
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312 #define RTTL1_EVENT(id,size) |
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313 |
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314 #endif // RVM_RTT_SWE || OP_L1_STANDALONE |