annotate cdg-hybrid/cdginc/p_ra.val @ 223:740a8e8fc9d7

startup sync logic rework for the new PWON button boot scheme Previously we added logic to the MMI task to hold off PEI init until R2D is running, and then extended that condition to wait for FCHG init too. However, the dependencies of MMI upon R2D and FCHG don't start until mmiInit(), and that call is driven by Switch_ON() code, hence the wait for R2D and FCHG init can be made in that code path instead of the MMI task. Furthermore, with our new way of signaling PWON button boot to MMI, we need a new wait to ensure that the MMI task is up - previously this assurance was provided by the wait for Kp pointers to be set. Solution: revert our previous PEI init hold-off additions to MMI, add a new flag indicating MMI task init done, and put the combined wait for all needed conditions into our new PWON button boot code in power.c.
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 27 Apr 2021 06:24:52 +0000
parents 35f7a1dc9f7d
children
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14
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1 /*
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2 +--------------------------------------------------------------------------+
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3 | PROJECT : PROTOCOL STACK |
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4 | FILE : p_ra.val |
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5 | SOURCE : "sap\ra.pdf" |
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6 | LastModified : "2002-04-26" |
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7 | IdAndVersion : "8411.102.98.204" |
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8 | SrcFileTime : "Thu Nov 29 09:51:34 2007" |
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9 | Generated by CCDGEN_2.5.5A on Fri Oct 14 21:41:52 2016 |
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10 | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! |
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11 +--------------------------------------------------------------------------+
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12 */
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13
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14 /* PRAGMAS
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15 * PREFIX : NONE
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16 * COMPATIBILITY_DEFINES : NO (require PREFIX)
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17 * ALWAYS_ENUM_IN_VAL_FILE: NO
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18 * ENABLE_GROUP: NO
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19 * CAPITALIZE_TYPENAME: NO
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20 */
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21
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22
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23 #ifndef P_RA_VAL
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24 #define P_RA_VAL
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25
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26
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27 #define CDG_ENTER__P_RA_VAL
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28
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29 #define CDG_ENTER__FILENAME _P_RA_VAL
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30 #define CDG_ENTER__P_RA_VAL__FILE_TYPE CDGINC
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31 #define CDG_ENTER__P_RA_VAL__LAST_MODIFIED _2002_04_26
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32 #define CDG_ENTER__P_RA_VAL__ID_AND_VERSION _8411_102_98_204
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33
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34 #define CDG_ENTER__P_RA_VAL__SRC_FILE_TIME _Thu_Nov_29_09_51_34_2007
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35
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36 #include "CDG_ENTER.h"
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37
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38 #undef CDG_ENTER__P_RA_VAL
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39
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40 #undef CDG_ENTER__FILENAME
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41
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42
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43 /*
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44 * Value constants for VAL_model
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45 */
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46 #define RA_MODEL_SPEECH (0x0) /* model speech */
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47 #define RA_MODEL_TRANS (0x1) /* model 1b async transparent */
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48 #define RA_MODEL_RLP (0x2) /* model 3b async nontransparent */
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49 #define RA_MODEL_FAX (0x3) /* model 5b fax 3.45 */
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50
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51 /*
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52 * Value constants for VAL_tra_rate
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53 */
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54 #define TRA_FULLRATE_2400 (0x0) /* fullrate 2,4/3,6 kBit */
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55 #define TRA_HALFRATE_2400 (0x1) /* halfrate 2,4/3,6 kBit */
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56 #define TRA_FULLRATE_4800 (0x2) /* fullrate 4,8/6 kBit */
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57 #define TRA_HALFRATE_4800 (0x3) /* halfrate 4,8/6 kBit */
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58 #define TRA_FULLRATE_9600 (0x4) /* fullrate 9,6/12 kBit */
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59 #define TRA_FULLRATE_14400 (0x5) /* fullrate 13,4/14,4 kBit */
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60
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61 /*
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62 * Value constants for VAL_user_rate
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63 */
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64 #define URA_300 (0x0) /* user rate 300bps */
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65 #define URA_1200 (0x1) /* user rate 1200bps */
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66 #define URA_2400 (0x2) /* user rate 2400bps */
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67 #define URA_4800 (0x3) /* user rate 4800bps */
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68 #define URA_9600 (0x4) /* user rate 9600bps */
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69 #define URA_1200_75 (0x5) /* user rate 1200/75bps */
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70 #define URA_14400 (0x6) /* user rate 14400bps */
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71
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72 /*
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73 * Value constants for VAL_dtx_flg
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74 */
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75 #define DTX_DIS (0x0) /* Disable DTX */
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76 #define DTX_EN (0x1) /* Enable DTX */
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77
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78 /*
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79 * Value constants for VAL_fr_type
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80 */
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81 #define FR_T4DATA (0x0) /* GSM 3.45 Data frame */
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82 #define FR_STATUS (0x1) /* GSM 3.45 Status (BCS) frame */
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83 #define FR_SYNC (0x2) /* GSM 3.45 Sync frame */
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84 #define FR_TRAIN (0x3) /* GSM 3.45 Status (TRAIN) frame */
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85 #define FR_TRANS (0x4) /* Transparent Data frame */
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86 #define FR_RLP (0x5) /* Valid RLP frame */
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87 #define FR_INVALID (0xf) /* Invalid frame or FCS error detected in RLP mode */
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88
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89 /*
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90 * Value constants for VAL_status
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91 */
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92 #define ST_SA (0x1) /* Status SA */
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93 #define ST_SB (0x2) /* Status SB */
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94 #define ST_X (0x4) /* Status X */
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95 #define ST_OVER (0x8) /* Overspeed flag */
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96
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97 /*
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98 * Value constants for VAL_ack_flg
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99 */
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100 #define RA_ACK (0x0) /* acknowledged */
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101 #define RA_NAK (0x1) /* not acknowledged */
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102
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103 /*
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104 * Value constants for VAL_detect
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105 */
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106 #define DET_NO_STATUS (0x0) /* do not detect status frames */
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107 #define DET_STATUS (0x1) /* detect status frames */
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108
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109 /*
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110 * Value constants for VAL_tick_dir
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111 */
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112 #define TICK_UL (0x1) /* tick uplink */
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113 #define TICK_DL (0x2) /* tick downlink */
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114 #define TICK_UL_DL (0x3) /* tick uplink & downlink */
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115
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116 /*
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117 * Value constants for VAL_offset
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118 */
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119 #define ra_conf (0x0) /* Configurations */
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120 #define ra_act (0x1) /* Activities */
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121 #define ra_test (0x2) /* Test */
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122 #define ra_statu (0x3) /* Uplink status */
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123 #define ra_statd (0x4) /* Downlink status */
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124 #define fax_status_det (0x5) /* Fax status detection */
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125 #define rau (0x6) /* Buffer for uplink characters */
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126 #define rad (0x7) /* Buffer for downlink characters */
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127 #define ntu (0x8) /* Buffer for uplink RLP frames */
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128 #define ntd (0x9) /* Buffer for downlink RLP frames */
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129 #define faxu (0xa) /* Buffer for uplink fax data */
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130 #define faxd (0xb) /* Buffer for downlink fax data */
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131
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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132 /*
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Mychaela Falconia <falcon@freecalypso.org>
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133 * user defined constants
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Mychaela Falconia <falcon@freecalypso.org>
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134 */
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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135 #define DUMMY_RA (0x0)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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136
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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137 #include "CDG_LEAVE.h"
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138
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139
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140 #endif