FreeCalypso > hg > fc-tourmaline
annotate src/cs/layer1/hmacs/macs_cst.h @ 223:740a8e8fc9d7
startup sync logic rework for the new PWON button boot scheme
Previously we added logic to the MMI task to hold off PEI init until
R2D is running, and then extended that condition to wait for FCHG
init too. However, the dependencies of MMI upon R2D and FCHG don't
start until mmiInit(), and that call is driven by Switch_ON() code,
hence the wait for R2D and FCHG init can be made in that code path
instead of the MMI task. Furthermore, with our new way of signaling
PWON button boot to MMI, we need a new wait to ensure that the MMI
task is up - previously this assurance was provided by the wait for
Kp pointers to be set.
Solution: revert our previous PEI init hold-off additions to MMI,
add a new flag indicating MMI task init done, and put the combined
wait for all needed conditions into our new PWON button boot code
in power.c.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Tue, 27 Apr 2021 06:24:52 +0000 |
parents | 4e78acac3d88 |
children |
rev | line source |
---|---|
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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1 /************* Revision Control System Header ************* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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2 * GSM Layer 1 software |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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3 * MACS_CST.H |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 * Filename macs_cst.h |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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6 * Copyright 2003 (C) Texas Instruments |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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7 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 ************* Revision Control System Header *************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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9 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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10 /*********************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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11 /* Copyright 2003 (C) Texas Instruments */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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12 /*********************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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14 //#define MACS_VERSION 0x01 // MAC-S validated version for 1 Rx - 1 Tx (no polling) - Power measurements in Dynamic mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 //#define MACS_VERSION 0x02 // MAC-S validated version for multi-slot - poll responses in dynamic mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 //#define MACS_VERSION 0x03 // TFI filtering, fixed allocation mode for 1 Rx - 1 Tx (no PDCH release, no repeat allocation) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 //#define MACS_VERSION 0x04 // Problem of MAC-S Read phase during Idle frames corrected - new MCU/DSP and new RLC/MAC interfaces (S921_bis v 0.7) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 //#define MACS_VERSION 0x05 // Fixed allocation mode in multi-slot, control timeslot monitoring, PDCH release |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 //#define MACS_VERSION 0x06 // Tra parameter always respected -> no power between Rx and Tx |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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20 //#define MACS_VERSION 0x07 // PR field extracting in downlink blocks |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 //#define MACS_VERSION 0x08 // Fixed mode: Repeat allocation and allocation bitmap exhaustion management - BSIC setting in PRACH polling uplink blocks |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 #define MACS_VERSION 0x09 // Dynamic mode / USF granularity = 4 blocks rework |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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23 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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24 /*********************************************************/ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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25 /* Constants used by MAC-S */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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26 /*********************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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27 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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28 /* Data processing */ |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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29 /*-----------------*/ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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30 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
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parents:
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31 /* Invalid value */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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32 #define INVALID 0xFF // Non-significative value |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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33 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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34 /* No received DL blocks */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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35 #define NO_DL_BLK 0xFFFFFFFF |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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36 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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37 /* USF management */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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38 #define MASK_2SLOTS 0x3 // Mask used to read the d_usf_updated_gprs value |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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39 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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40 /* Timeslot test mask */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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41 #define MASK_SLOT0 128 // Mask used to isolate slot 0 in a 8 bit word |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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42 #define MASK_ALL_SLOTS 0xFF // Mask used to remove several timeslots |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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43 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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44 /* Multi-slot */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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45 /*------------*/ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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46 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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47 /* Number of timeslot */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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48 #define TS_NUMBER 8 // Number of timeslots |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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49 #define MAX_TS_NB 7 // Highest timeslot number |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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50 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
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51 /* USF granularity */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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52 #define FOUR_BLOCKS 1 // USF monitored on blocks B0, B4, B8 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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53 #define BLOCK 0 // USF monitored on each block |
4e78acac3d88
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54 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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55 /* RX - TX delay */ |
4e78acac3d88
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56 #define RXTX_DELAY 3 // 3 timeslot dealy between downlink and uplink transfer window |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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57 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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58 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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59 /* RLC/MAC header */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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60 /*----------------*/ |
4e78acac3d88
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61 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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62 /* Payload and AC field reading */ |
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63 #define PAYLOAD_SHIFT 6 // Shift number used to isolate the payload type in the RLC/MAC header |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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64 #define PAYLOAD_MASK 0x0003 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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65 #define AC_MASK 0x0100 // Mask used to isolate the AC value in the RLC/MAC control block header |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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66 |
4e78acac3d88
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67 /* Payload type values for downlink RLC/MAC blocks */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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68 //TABLE/ PAYLOAD |
4e78acac3d88
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69 #define DATA_BLOCK 0 //NAME/ DATA |
4e78acac3d88
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70 #define CTRL_NO_OPTIONAL 1 //NAME/ CTRL OPT |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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71 #define CTRL_OPTIONAL 2 //NAME/ CTRL NO OPT |
4e78acac3d88
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72 #define RESERVED 3 //NAME/ RESERVED |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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73 //END_TABLE/ |
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Mychaela Falconia <falcon@freecalypso.org>
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74 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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75 /* TFI field in data blocks */ |
4e78acac3d88
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76 #define DATA_TFI_MASK 0x3e00 // Mask used to isolate the TFI field in downlink data block after one right shift |
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77 #define DATA_TFI_SHIFT 9 // Shift number used to isolate the TFI field in downlink data block header |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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78 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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79 /* TFI field in control blocks */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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80 #define CTRL_TFI_MASK 0x003e // Mask used to isolate the TFI and D fields |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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81 #define CTRL_TFI_SHIFT 1 // Shift number used to isolate the TFI field in downlink control block header |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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82 #define MASK_D 0x0001 // Mask used to isolated the D bit |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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83 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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84 /* PR field extracting */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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85 #define DATA_PR_SHIFT 14 // Data blocks |
4e78acac3d88
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86 #define CTRL_PR_SHIFT 6 // Control blocks |
4e78acac3d88
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87 #define PR_MASK 3 // PR <-> 2 bits |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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88 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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89 /* TFI filtering result */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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90 /*----------------------*/ |
4e78acac3d88
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91 |
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92 #define TFI_BIT_MASK 0xf9ff |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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93 #define TFI_BIT_SHIFT 9 // Shift number used to access the TFI filter bit in the block header stored in the NDB |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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94 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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95 //TABLE/ TFI RESULT |
4e78acac3d88
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96 #define TFI_NOT_FILTERED 0 //NAME/ NO FILTERING |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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97 #define TFI_NOT_PRESENT 1 //NAME/ NO TFI |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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98 #define TFI_GOOD 2 //NAME/ MS |
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99 #define TFI_BAD 3 //NAME/ NOT MS |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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100 //END_TABLE/ |
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101 |
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102 /* "time" values used when processing the power measurement gap */ |
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103 #define RX_SLOT 0xF0 |
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104 #define TX_SLOT 0xF1 |
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105 |
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106 #define MAX_CLASS 12 |
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107 |
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108 /*********************************************************/ |
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109 /* Tables */ |
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110 /*********************************************************/ |
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111 |
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112 #ifdef L1P_ASYN_C |
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113 |
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114 /* Multi-slot class parameters */ |
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115 /*-----------------------------*/ |
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116 const T_MSCLASS_PARAMETERS MS_CLASS[MAX_CLASS+1] = |
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117 { |
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118 /*-------------------------------------------------------------*/ |
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119 /* RX TX SUM TTA TTB TRA TRB */ |
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120 /*-------------------------------------------------------------*/ |
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121 {0 , 0 , 0 , 0 , 0 , 0 , 0}, /* Unused */ |
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122 {1 , 1 , 2 , 3 , 2 , 4 , 2}, /* MS Class 1 */ |
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123 {2 , 1 , 3 , 3 , 2 , 3 , 1}, /* MS Class 2 */ |
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124 {2 , 2 , 3 , 3 , 2 , 3 , 1}, /* MS Class 3 */ |
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125 {3 , 1 , 4 , 3 , 1 , 3 , 1}, /* MS Class 4 */ |
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126 {2 , 2 , 4 , 3 , 1 , 3 , 1}, /* MS Class 5 */ |
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127 {3 , 2 , 4 , 3 , 1 , 3 , 1}, /* MS Class 6 */ |
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128 {3 , 3 , 4 , 3 , 1 , 3 , 1}, /* MS Class 7 */ |
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129 {4 , 1 , 5 , 3 , 1 , 2 , 1}, /* MS Class 8 */ |
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130 {3 , 2 , 5 , 3 , 1 , 2 , 1}, /* MS Class 9 */ |
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131 {4 , 2 , 5 , 3 , 1 , 2 , 1}, /* MS Class 10 */ |
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132 {4 , 3 , 5 , 3 , 1 , 2 , 1}, /* MS Class 11 */ |
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133 {4 , 4 , 5 , 2 , 1 , 2 , 1} /* MS Class 12 */ |
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134 }; |
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135 |
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136 const UWORD8 PR_CONVERSION[2][4] = |
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137 { |
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138 /*-----------------------------------------------*/ |
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139 /* PR field 00 01 10 11 */ |
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140 /*-----------------------------------------------*/ |
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141 /* BTS_PWR_CTL_MODE A */ { 1 , 5 , 9 , 0 }, |
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142 /* BTS_PWR_CTL_MODE B */ { 3 , 11 , 19 , 27 } |
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143 }; |
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144 |
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145 const UWORD8 USF_BLOCK_GRANULARITY[2] = |
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146 { |
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147 1, // One block granularity (granularity = 0) |
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148 4 // Four blocks granularity (granularity = 1) |
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149 }; |
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150 |
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151 #else |
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152 extern T_MSCLASS_PARAMETERS MS_CLASS[MAX_CLASS+1]; |
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153 extern UWORD8 PR_CONVERSION[2][4]; |
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154 extern UWORD8 USF_BLOCK_GRANULARITY[2]; |
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155 #endif |
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156 |
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157 /* Error type */ |
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158 /*------------*/ |
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159 |
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160 #if MACS_STATUS |
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161 #define NEW_SET_NOT_ON_TDMA3 1 // The new_set have been setted to 1 by Layer 1 during a |
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162 // TDMA frame that isn't situated just before a new block period |
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163 |
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164 #define MS_CLASS_TIME_ERROR 2 // Allocated resources doesn't respect the Trb or Ttb |
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165 // MS Class parameter |
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166 #define MS_CLASS_SUM_ERROR 3 // Allocated resources doesn't respect the Sum, Rx or |
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Mychaela Falconia <falcon@freecalypso.org>
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167 // Tx MS Class parameter |
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168 #define NO_MEAS_MAPPED 4 // No mesurement gap has been found |
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169 #define POLL_ERROR_MS_CLASS 5 // A poll response isn't transmitted because of a MS |
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170 // class parameter not respected or measurement gap |
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Mychaela Falconia <falcon@freecalypso.org>
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171 // not mapped |
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172 #define POLL_ERROR_DISCONTINUITY 6 // The poll responses have not been transmitted because |
4e78acac3d88
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173 // of BCCH monitoring / SYNCHRO. change done by Layer 1 |
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174 #define NO_RX_MONITORED 7 // NO timeslot can be monitored according to MS Class and |
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175 // power measurements |
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176 #endif |
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177 |