FreeCalypso > hg > fc-tourmaline
annotate src/cs/drivers/drv_app/ffs/board/intelsbdrv.c @ 275:79cfefc1e2b4
audio mode load: gracefully handle mode files of wrong AEC version
Unfortunately our change of enabling L1_NEW_AEC (which is necessary
in order to bring our Calypso ARM fw into match with the underlying
DSP reality) brings along a change in the audio mode file binary
format and file size - all those new tunable AEC parameters do need
to be stored somewhere, after all. But we already have existing
mode files in the old format, and setting AEC config to garbage when
loading old audio modes (which is what would happen without the
present change) is not an appealing proposition.
The solution implemented in the present change is as follows: the
audio mode loading code checks the file size, and if it differs
from the active version of T_AUDIO_MODE, the T_AUDIO_AEC_CFG structure
is cleared - set to the default (disabled AEC) for the compiled type
of AEC. We got lucky in that this varying T_AUDIO_AEC_CFG structure
sits at the end of T_AUDIO_MODE!
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Fri, 30 Jul 2021 02:55:48 +0000 |
parents | 4e78acac3d88 |
children |
rev | line source |
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0
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1 /****************************************************************************** |
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2 * Flash File System (ffs) |
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com |
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4 * |
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5 * FFS AMD single bank low level flash driver RAM code |
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6 * |
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7 * $Id: intelsbdrv.c 1.13 Thu, 08 Jan 2004 15:05:23 +0100 tsj $ |
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8 * |
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9 ******************************************************************************/ |
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10 |
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11 #include "ffs.cfg" |
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12 |
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13 #include "ffs/ffs.h" |
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14 #include "ffs/board/drv.h" |
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15 #include "ffs/board/ffstrace.h" |
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16 |
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17 |
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18 #define INTEL_UNLOCK_SLOW 1 |
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19 |
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20 |
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21 #undef tlw |
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22 #define tlw(contents) |
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23 #undef ttw |
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24 #define ttw(contents) |
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25 |
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26 // Status bits for Intel flash memory devices |
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27 #define INTEL_STATE_MACHINE_DONE (1<<7) |
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28 #define FLASH_READ(addr) (*(volatile uint16 *) (addr)) |
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29 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data |
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30 |
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31 #ifdef __GNUC__ |
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32 asm(".globl ffsdrv_ram_intel_begin"); |
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33 asm("ffsdrv_ram_intel_begin:"); |
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34 #else |
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35 asm(" .label _ffsdrv_ram_intel_begin"); |
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36 asm(" .def _ffsdrv_ram_intel_begin"); |
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37 #endif |
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38 |
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39 uint32 intel_int_disable(void); |
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40 void intel_int_enable(uint32 tmp); |
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41 |
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42 /****************************************************************************** |
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43 * INTEL Single Bank Driver Functions |
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44 ******************************************************************************/ |
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45 // Actually we should have disabled and enable the interrupts in this |
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46 // function, but when the interrupt functions are used Target don't run! |
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47 // Anyway, currently the interrupts are already disabled at this point thus |
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48 // it does not cause any problems. |
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49 int ffsdrv_ram_intel_sb_init(void) |
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50 { |
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51 uint32 cpsr, i; |
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52 volatile char *addr; |
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53 uint16 status; |
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54 |
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55 for (i = 0; i < dev.numblocks; i++) |
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56 { |
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57 addr = block2addr(i); |
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58 |
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59 *addr = 0x50; // Intel Clear Status Register |
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60 *addr = 0xFF; // Intel read array |
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61 |
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62 *addr = 0x60; // Intel Config Setup |
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63 *addr = 0xD0; // Intel Unlock Block |
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64 |
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65 // Wait for unlock to finish |
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66 do { |
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67 status = FLASH_READ(addr); |
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68 } while (!(status & INTEL_STATE_MACHINE_DONE)); |
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69 |
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70 *addr = 0x70; // Intel Read Status Register |
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71 status = FLASH_READ(addr); |
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72 |
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73 // Is there an erase suspended? |
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74 if ((status & 0x40) != 0) { |
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75 *addr = 0xD0; // Intel erase resume |
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76 |
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77 *addr = 0x70; // Intel Read Status Register |
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78 // wait for erase to finish |
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79 do { |
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80 status = FLASH_READ(addr); |
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81 } while (!(status & INTEL_STATE_MACHINE_DONE)); |
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82 } |
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83 |
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84 *addr = 0xFF; // Intel Read Array |
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85 } |
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86 |
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87 return 0; |
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88 } |
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89 |
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90 void ffsdrv_ram_intel_sb_write_halfword(volatile uint16 *addr, uint16 value) |
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91 { |
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92 uint32 cpsr; |
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93 |
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94 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value)); |
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95 |
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96 if (~*addr & value) { |
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97 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value)); |
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98 return; |
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99 } |
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100 |
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101 cpsr = intel_int_disable(); |
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102 tlw(led_on(LED_WRITE)); |
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103 |
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104 #if (INTEL_UNLOCK_SLOW == 1) |
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105 *addr = 0x60; // Intel Config Setup |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
106 *addr = 0xD0; // Intel Unlock Block |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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107 #endif |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
108 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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109 *addr = 0x50; // Intel Clear Status Register |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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110 *addr = 0x40; // Intel program byte/word |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
111 *addr = value; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
112 while ((*addr & 0x80) == 0) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
113 ; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
114 *addr = 0xFF; // Intel read array |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
115 tlw(led_off(LED_WRITE)); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
116 intel_int_enable(cpsr); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
117 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
118 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
119 void ffsdrv_ram_intel_sb_erase(uint8 block) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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120 { |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
121 volatile char *addr; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
122 uint32 cpsr; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
123 uint16 poll; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
124 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
125 ttw(ttr(TTrDrvEra, "e(%d)" NL, block)); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
126 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
127 addr = block2addr(block); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
128 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
129 cpsr = intel_int_disable(); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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130 tlw(led_on(LED_ERASE)); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
131 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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132 #if (INTEL_UNLOCK_SLOW == 1) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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133 *addr = 0x60; // Intel Config Setup |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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134 *addr = 0xD0; // Intel Unlock Block |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
135 #endif |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
136 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
137 *addr = 0x50; // Intel Clear Status Register |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
138 *addr = 0x20; // Intel Erase Setup |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
139 *addr = 0xD0; // Intel Erase Confirm |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
140 *addr = 0x70; // Intel Read Status Register |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 // Wait for erase to finish. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
143 while ((*addr & 0x80) == 0) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
144 tlw(led_toggle(LED_ERASE)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
145 // Poll interrupts, taking interrupt mask into account. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 if (INT_REQUESTED) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
148 // 1. suspend erase |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
149 // 2. enable interrupts |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
150 // .. now the interrupt code executes |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
151 // 3. disable interrupts |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
152 // 4. resume erase |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
153 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
154 tlw(led_on(LED_ERASE_SUSPEND)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 *addr = 0xB0; // Intel Erase Suspend |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 *addr = 0x70; // Intel Read Status Register |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 while (((poll = *addr) & 0x80) == 0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 ; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 // If erase is complete, exit immediately |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 if ((poll & 0x40) == 0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
163 break; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 *addr = 0xFF; // Intel read array |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 tlw(led_off(LED_ERASE_SUSPEND)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 intel_int_enable(cpsr); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 // Other interrupts and tasks run now... |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 cpsr = intel_int_disable(); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 tlw(led_on(LED_ERASE_SUSPEND)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 *addr = 0xD0; // Intel erase resume |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 // The following "extra" Read Status command is required because Intel has |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 // changed the specification of the W30 flash! (See "1.8 Volt Intel® |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 // Specification Update") |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 *addr = 0x70; // Intel Read Status Register |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 tlw(led_off(LED_ERASE_SUSPEND)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 *addr = 0xFF; // Intel read array |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 tlw(led_on(LED_ERASE)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 tlw(led_off(LED_ERASE)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
189 intel_int_enable(cpsr); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
190 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 // TODO: remove below function, not in use anymore. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
193 void ffsdrv_ram_intel_erase(uint8 block) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
194 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
195 uint32 cpsr; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
196 uint16 status; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
197 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
198 ttw(ttr(TTrDrvErase, "e(%d)" NL, block)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
199 tlw(led_on(LED_ERASE)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
200 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
201 dev.addr = (uint16 *) block2addr(block); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
202 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
203 cpsr = intel_int_disable(); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
204 dev.state = DEV_ERASE; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
205 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
206 *dev.addr = 0x60; // Intel Config setup |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
207 *dev.addr = 0xD0; // Intel Unlock block |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
208 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
209 *dev.addr = 0x50; // Intel clear status register (not really necessary) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
210 *dev.addr = 0x20; // Intel erase setup |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
211 *dev.addr = 0xD0; // Intel erase confirm |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
212 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
213 intel_int_enable(cpsr); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
214 |
4e78acac3d88
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215 while ((*dev.addr & 0x80) == 0) |
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216 ; |
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217 |
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218 *dev.addr = 0xFF; // Intel read array |
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219 dev.state = DEV_READ; |
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220 tlw(led_off(LED_WRITE)); |
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221 } |
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222 |
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223 |
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224 /****************************************************************************** |
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225 * Interrupt Enable/Disable |
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226 ******************************************************************************/ |
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227 |
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228 #ifdef __GNUC__ |
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229 #define NOINLINE __attribute__ ((noinline)) |
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230 #else |
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231 #define NOINLINE |
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232 #endif |
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233 |
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234 uint32 NOINLINE intel_int_disable(void) |
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235 { |
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236 #ifdef __GNUC__ |
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237 asm(" .code 16"); |
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238 #else |
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239 asm(" .state16"); |
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240 #endif |
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241 asm(" mov A1, #0xC0"); |
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242 asm(" ldr A2, tct_intel_disable"); |
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243 asm(" bx A2 "); |
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244 |
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245 #ifdef __GNUC__ |
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246 asm(".balign 4"); |
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247 asm("tct_intel_disable:"); |
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248 asm(" .word TCT_Control_Interrupts"); |
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249 #else |
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250 asm("tct_intel_disable .field _TCT_Control_Interrupts+0,32"); |
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251 asm(" .global _TCT_Control_Interrupts"); |
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252 #endif |
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253 } |
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254 |
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255 void NOINLINE intel_int_enable(uint32 cpsr) |
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256 { |
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257 #ifdef __GNUC__ |
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258 asm(" .code 16"); |
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259 #else |
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260 asm(" .state16"); |
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261 #endif |
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262 asm(" ldr A2, tct_intel_enable"); |
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263 asm(" bx A2 "); |
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264 |
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265 #ifdef __GNUC__ |
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266 asm(".balign 4"); |
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267 asm("tct_intel_enable:"); |
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268 asm(" .word TCT_Control_Interrupts"); |
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269 #else |
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270 asm("tct_intel_enable .field _TCT_Control_Interrupts+0,32"); |
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271 asm(" .global _TCT_Control_Interrupts"); |
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272 #endif |
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273 } |
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274 |
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275 // Even though we have this end label, we cannot determine the number of |
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276 // constant/PC-relative data following the code! |
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277 #ifdef __GNUC__ |
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278 asm(".globl ffsdrv_ram_intel_end"); |
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279 asm("ffsdrv_ram_intel_end:"); |
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280 #else |
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281 asm(" .state32"); |
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282 asm(" .label _ffsdrv_ram_intel_end"); |
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283 asm(" .def _ffsdrv_ram_intel_end"); |
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284 #endif |