FreeCalypso > hg > fc-tourmaline
annotate src/cs/drivers/drv_app/r2d/board/uwire.c @ 275:79cfefc1e2b4
audio mode load: gracefully handle mode files of wrong AEC version
Unfortunately our change of enabling L1_NEW_AEC (which is necessary
in order to bring our Calypso ARM fw into match with the underlying
DSP reality) brings along a change in the audio mode file binary
format and file size - all those new tunable AEC parameters do need
to be stored somewhere, after all. But we already have existing
mode files in the old format, and setting AEC config to garbage when
loading old audio modes (which is what would happen without the
present change) is not an appealing proposition.
The solution implemented in the present change is as follows: the
audio mode loading code checks the file size, and if it differs
from the active version of T_AUDIO_MODE, the T_AUDIO_AEC_CFG structure
is cleared - set to the default (disabled AEC) for the compiled type
of AEC. We got lucky in that this varying T_AUDIO_AEC_CFG structure
sits at the end of T_AUDIO_MODE!
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 30 Jul 2021 02:55:48 +0000 |
parents | 4e78acac3d88 |
children |
rev | line source |
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0
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1 /************************************************************************************ |
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2 * uwire.c : contains driver for the uwire HD module * |
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3 * * |
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4 * * |
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5 * Author: Davide Carpegna * |
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6 * * |
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7 * version: 1.0 * |
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8 * * |
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9 * Date: 22/09/2000 * |
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10 * (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved * |
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11 ************************************************************************************/ |
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12 |
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13 #include "rv/general.h" |
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14 #include "r2d/uwire.h" |
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15 #include "rvf/rvf_api.h" |
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16 |
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17 /********************************************************************/ |
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18 /* set the DC input to low for command transmission */ |
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19 /* */ |
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20 /********************************************************************/ |
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21 void set_DC_low(void) |
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22 { |
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23 * (volatile UINT16 *) GPIO_OUT &= ~(0x02); //gpio(1) ->0 |
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24 } |
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25 |
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26 /********************************************************************/ |
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27 /* set the DC input to high for data transmission */ |
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28 /* */ |
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29 /********************************************************************/ |
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30 void set_DC_high(void) |
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31 { |
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32 * (volatile UINT16 *) GPIO_OUT |= 0x02; //gpio(1) ->1 |
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33 } |
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34 |
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35 /********************************************************************/ |
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36 /* transmit commands to the lcd */ |
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37 /* */ |
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38 /********************************************************************/ |
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39 void lcd_transmit_cmd(UINT8 cmd) |
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40 { |
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41 set_DC_low(); |
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42 * (volatile UINT16 *) TDR = cmd <<8; |
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43 * (volatile UINT16 *) CSR |= NB_BITS_WR_8 + CS_CMD + START ; // transmit command data |
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44 while (((* (volatile UINT16 *) CSR) & CSRB) != 0 ); // wait for end of WRITE |
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45 * (volatile UINT16 *) CSR &= ~CS_CMD; // clears Chip Select |
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46 } |
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47 |
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48 /********************************************************************/ |
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49 /* transmit data to the lcd */ |
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50 /* */ |
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51 /********************************************************************/ |
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52 void lcd_transmit_data(UINT8 data) |
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53 { |
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54 set_DC_high(); |
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55 * (volatile UINT16 *) TDR = data <<8; |
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56 * (volatile UINT16 *) CSR |= NB_BITS_WR_8 + CS_CMD + START ; // transmit data |
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57 //while (((* (volatile UINT16 *) CSR) & CSRB) != 0 ); // wait for end of WRITE |
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58 //* (volatile UINT16 *) CSR &= ~CS_CMD; // clears Chip Select |
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59 } |
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60 |
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61 extern BOOLEAN lcd_polling(void) |
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62 { |
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63 if (((* (volatile UINT16 *) CSR) & CSRB) == 0 ) |
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64 { |
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65 * (volatile UINT16 *) CSR &= ~CS_CMD; // clears Chip Select |
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66 return(TRUE); |
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67 } |
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68 else |
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69 return(FALSE); |
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70 } |
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71 |
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72 /********************************************************************/ |
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73 /* initialize the uwire parameters for the lcd */ |
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74 /* */ |
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75 /********************************************************************/ |
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76 void uwire_init_lcd() |
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77 { |
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78 * ( UINT16 *) GPIO_INOUT &= ~(0x0002); // configures gpio(1) in output mode |
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79 |
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80 * ( UINT16 *) CNTL_RST &= ~(0x04); // releases reset_out |
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81 * ( UINT16 *) CNTL_RST |= (0x04); // set reset_out to 0 |
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82 rvf_delay(RVF_MS_TO_TICKS(1)); // waits for 5 ms |
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83 * ( UINT16 *) CNTL_RST &= ~(0x04); // releases reset_out |
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84 |
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85 |
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86 * (volatile UINT16 *) SR1 = CS1_FRQ_FINT_4 ; // F_INT/4 -> 13M/4 = 3.25 Mhz |
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87 * (volatile UINT16 *) SR3 = SR3_CLK_EN; // enables the uwire clock |
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88 * (volatile UINT16 *) CSR = INDEX_CS1; // selects CS1 |
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89 } |
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90 |
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91 |
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92 |