FreeCalypso > hg > fc-tourmaline
annotate src/cs/drivers/drv_core/sys_map.h @ 275:79cfefc1e2b4
audio mode load: gracefully handle mode files of wrong AEC version
Unfortunately our change of enabling L1_NEW_AEC (which is necessary
in order to bring our Calypso ARM fw into match with the underlying
DSP reality) brings along a change in the audio mode file binary
format and file size - all those new tunable AEC parameters do need
to be stored somewhere, after all. But we already have existing
mode files in the old format, and setting AEC config to garbage when
loading old audio modes (which is what would happen without the
present change) is not an appealing proposition.
The solution implemented in the present change is as follows: the
audio mode loading code checks the file size, and if it differs
from the active version of T_AUDIO_MODE, the T_AUDIO_AEC_CFG structure
is cleared - set to the default (disabled AEC) for the compiled type
of AEC. We got lucky in that this varying T_AUDIO_AEC_CFG structure
sits at the end of T_AUDIO_MODE!
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Fri, 30 Jul 2021 02:55:48 +0000 |
parents | 4e78acac3d88 |
children |
rev | line source |
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0
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1 /* @(#) nom : sys_map.h SID: 1.2 date : 05/23/03 */ |
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2 /* Filename: sys_map.h */ |
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3 /* Version: 1.2 */ |
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4 /****************************************************************************** |
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5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT |
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6 * |
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7 * (C) 2002 Texas Instruments France. All rights reserved |
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8 * |
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9 * Author : Francois AMAND |
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10 * |
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11 * |
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12 * Important Note |
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13 * -------------- |
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14 * |
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15 * This S/W is a preliminary version. It contains information on a product |
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16 * under development and is issued for evaluation purposes only. Features |
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17 * characteristics, data and other information are subject to change. |
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18 * |
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19 * The S/W is furnished under Non Disclosure Agreement and may be used or |
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20 * copied only in accordance with the terms of the agreement. It is an offence |
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21 * to copy the software in any way except as specifically set out in the |
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22 * agreement. No part of this document may be reproduced or transmitted in any |
4e78acac3d88
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23 * form or by any means, electronic or mechanical, including photocopying and |
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24 * recording, for any purpose without the express written permission of Texas |
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25 * Instruments Inc. |
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26 * |
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27 ****************************************************************************** |
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28 * |
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29 * FILE NAME: sys_map.h |
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30 * |
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31 * |
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32 * PURPOSE: Memory mapping of the CALYPSO PLUS chip. |
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33 * |
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34 * |
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35 * FILE REFERENCES: |
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36 * |
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37 * Name IO Description |
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38 * ------------- -- --------------------------------------------- |
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39 * |
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40 * |
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41 * |
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42 * EXTERNAL VARIABLES: |
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43 * |
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44 * Source: |
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45 * |
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46 * Name Type IO Description |
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47 * ------------- --------------- -- ------------------------------ |
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48 * |
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49 * |
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50 * |
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51 * EXTERNAL REFERENCES: |
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52 * |
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53 * Name Description |
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54 * ------------------ ------------------------------------------------------- |
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55 * |
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56 * |
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57 * |
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58 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES: |
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59 * |
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60 * |
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61 * |
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62 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS: |
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63 * |
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64 * |
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65 * |
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66 * NOTES: |
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67 * |
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68 * |
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69 * |
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70 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES: |
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71 * |
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72 * |
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73 * |
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74 * |
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75 * DEVELOPMENT HISTORY: |
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76 * |
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77 * Date Name(s) Version Description |
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78 * ----------- -------------- ------- ------------------------------------- |
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79 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation |
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80 * |
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81 * ALGORITHM: |
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82 * |
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83 * |
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84 *****************************************************************************/ |
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85 |
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86 #include "chipset.cfg" |
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87 |
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88 #if (CHIPSET == 12) |
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89 |
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90 #ifndef __SYS_MAP_H__ |
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91 #define __SYS_MAP_H__ |
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92 |
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93 /**************************************************************************** |
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94 * STROBE 0 MAPPING |
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95 ***************************************************************************/ |
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96 |
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97 #define C_MAP_TPU_BASE 0xFFFF1000L // CS2 : TPU registers |
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98 #define C_MAP_I2C_BASE 0xFFFF2800L // CS5 : I2C registers |
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99 #define C_MAP_UWIRE_BASE 0xFFFF4000L // CS8 : UWIRE registers |
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100 #define C_MAP_UART_IRDA_BASE 0xFFFF5000L // CS10 : UART IRDA registers |
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101 #define C_MAP_UART_MODEM1_BASE 0xFFFF5800L // CS11 : UART MODEM 1 registers |
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102 #define C_MAP_UART_UIR_BASE 0xFFFF6000L // CS12 : UART UIR register |
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103 #define C_MAP_RIF_BASE 0xFFFF7000L // CS14 : RIF registers |
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104 #define C_MAP_TPU_RAM_BASE 0xFFFF9000L // CS18 : TPU RAM |
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105 #define C_MAP_DPLL_BASE 0xFFFF9800L // CS19 : DPLL register |
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106 #define C_MAP_LCD_IF_BASE 0xFFFFA000L // CS20 : LCD registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
107 #define C_MAP_USIM_BASE 0xFFFFA800L // CS21 : USIM registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
108 #define C_MAP_USB_BASE 0xFFFFB000L // CS22 : USB registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
109 #define C_MAP_GEA_BASE 0xFFFFC000L // CS24 : GEA registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
110 #define C_MAP_MMC_SD_BASE 0xFFFFC800L // CS25 : MMC/SD registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
111 #define C_MAP_MS_BASE 0xFFFFD000L // CS26 : Memory Stick registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
112 #define C_MAP_CPORT_BASE 0xFFFFD800L // CS27 : C-Port registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
113 #define C_MAP_UART_MODEM2_BASE 0xFFFFE000L // CS28 : UART MODEM 2 registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
114 #define C_MAP_DMA_BASE 0xFFFFE800L // CS29 : DMA registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
115 #define C_MAP_WD_TIMER_BASE 0xFFFFF800L // CS31 : Watchdog TIMER registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
116 #define C_MAP_WD_TIMER_SEC_BASE 0xFFFFF880L // CS31 : Secure Watchdog TIMER registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
117 #define C_MAP_RHEA_BASE 0xFFFFF900L // CS31 : RHEA bridge registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
118 #define C_MAP_INTH_BASE 0xFFFFFA00L // CS31 : INTH registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
119 #define C_MAP_INTH_SEC_BASE 0xFFFFFA80L // CS31 : Secure INTH registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
120 #define C_MAP_MEMIF_BASE 0xFFFFFB00L // CS31 : MEMIF registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
121 #define C_MAP_PRRM_BASE 0xFFFFFC00L // CS31 : PRRM (Protected Ressource Reset Management) registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
122 #define C_MAP_CLKM_BASE 0xFFFFFD00L // CS31 : CLOCKM registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
123 #define C_MAP_JTAG_ID_CODE_BASE 0xFFFFFE00L // CS31 : JTAG ID code registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
124 #define C_MAP_EMPU_BASE 0xFFFFFF00L // CS31 : EMPU registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
125 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
126 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
127 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
128 /**************************************************************************** |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
129 * STROBE 1 MAPPING |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
130 ***************************************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
131 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
132 #define C_MAP_SIM_BASE 0xFFFE0000L // CS0 : SIM registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
133 #define C_MAP_TSP_BASE 0xFFFE0800L // CS1 : TSP registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
134 #define C_MAP_RTC_BASE 0xFFFE1800L // CS3 : RTC registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
135 #define C_MAP_ULPD_BASE 0xFFFE2000L // CS4 : ULPD registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
136 #define C_MAP_SPI_BASE 0xFFFE3000L // CS6 : SPI registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
137 #define C_MAP_TIMER1_BASE 0xFFFE3800L // CS7 : TIMER1 registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
138 #define C_MAP_GPIO_BASE 0xFFFE4800L // CS9 : GPIO registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
139 #define C_MAP_TIMER2_BASE 0xFFFE6800L // CS13 : TIMER2 registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
140 #define C_MAP_LPG_BASE 0xFFFE7800L // CS15 : LPG registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 #define C_MAP_PWL_BASE 0xFFFE8000L // CS16 : PWL registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 #define C_MAP_PWT_BASE 0xFFFE8800L // CS17 : PWT registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
143 #define C_MAP_KEYBOARD_BASE 0xFFFEB800L // CS23 : KEYBOARD registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
144 #define C_MAP_JTAG_ID_BASE 0xFFFEF000L // CS30 : JTAG ID register |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
145 #define C_MAP_JTAG_VERSION_BASE 0xFFFEF002L // CS30 : JTAG Version register |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 #define C_MAP_DIE_ID_CODE_BASE 0xFFFEF004L // CS30 : DIE IDENTIFICATION code registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 #define C_MAP_HASH_MAN_PUB_KEY_BASE 0xFFFEF00CL // CS30 : Hash of the Manufacturer Public Key registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
148 #define C_MAP_CORE_CONF_BASE 0xFFFEF01CL // CS30 : Core configuration registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
149 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
150 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
151 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
152 /**************************************************************************** |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
153 * INTERNAL MEMORY MAPPING |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
154 ***************************************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 #define C_MAP_CS6_4MBITS_BASE 0x08000000L // Main 4Mbits of Internal SRAM |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 #define C_MAP_CS6_SHD_RAM0_BASE 0x08080000L // Shared 0.5Mbits of Internal SRAM |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 #define C_MAP_CS6_SHD_RAM1_BASE 0x08090000L // Shared 0.5Mbits of Internal SRAM |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 #define C_MAP_CS6_SHD_RAM2_BASE 0x080A0000L // Shared 0.5Mbits of Internal SRAM |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
163 /**************************************************************************** |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 * INTERNAL PERIPHERAL MAPPING |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 ***************************************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 #define C_MAP_SHA1MD5_BASE 0x09800000L // SHA1/MD5 registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 #define C_MAP_DES_BASE 0x09900000L // DES/3DES registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 #define C_MAP_RNG_BASE 0x09A00000L // RNG registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 #define C_MAP_NAND_FLASH_BASE 0x09D00000L // Nand Flash Conroller registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 #define C_MAP_PATCH_UNIT_BASE 0x09E00000L // Patch Unit registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 #define C_MAP_DEBUG_UNIT_BASE 0x09F00000L // Debug Unit registers |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 /**************************************************************************** |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 * API MAPPING |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 ***************************************************************************/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 #define C_MAP_API_RAM_BASE 0xFFD00000L // API RAM address on MCU side |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 #define C_MAP_DSP_API_RAM_BASE 0xE000 // API RAM address on DSP side |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 #define C_MAP_APIC_BASE 0xFFE00000L // APIC register |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 #endif /* __SYS_MAP_H__ */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 #endif /* (CHIPSET == 12) */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 |