FreeCalypso > hg > fc-tourmaline
annotate src/cs/drivers/drv_core/inth/sys_inth32.c @ 210:7e225a4cd537
ETM KPD_PWR testing: add separate pressed & released calls
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 22 Apr 2021 07:30:26 +0000 |
parents | 4e78acac3d88 |
children |
rev | line source |
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0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
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1 /* @(#) nom : sys_inth32.c SID: 1.2 date : 05/23/03 */ |
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2 /* Filename: sys_inth32.c */ |
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3 /* Version: 1.2 */ |
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4 /****************************************************************************** |
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5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT |
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6 * |
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7 * (C) 2002 Texas Instruments France. All rights reserved |
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8 * |
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9 * Author : Francois AMAND |
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10 * |
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11 * |
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12 * Important Note |
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13 * -------------- |
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14 * |
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15 * This S/W is a preliminary version. It contains information on a product |
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16 * under development and is issued for evaluation purposes only. Features |
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17 * characteristics, data and other information are subject to change. |
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18 * |
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19 * The S/W is furnished under Non Disclosure Agreement and may be used or |
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20 * copied only in accordance with the terms of the agreement. It is an offence |
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21 * to copy the software in any way except as specifically set out in the |
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22 * agreement. No part of this document may be reproduced or transmitted in any |
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23 * form or by any means, electronic or mechanical, including photocopying and |
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24 * recording, for any purpose without the express written permission of Texas |
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25 * Instruments Inc. |
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26 * |
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27 ****************************************************************************** |
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28 * |
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29 * FILE NAME: sys_inth32.c |
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30 * |
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31 * |
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32 * PURPOSE: Interrupt Handler driver compiled in 32-bits mode. |
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33 * |
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34 * |
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35 * FILE REFERENCES: |
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36 * |
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37 * Name IO Description |
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38 * ------------- -- --------------------------------------------- |
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39 * |
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40 * |
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41 * |
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42 * EXTERNAL VARIABLES: |
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43 * |
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44 * Source: |
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45 * |
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46 * Name Type IO Description |
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47 * ------------- --------------- -- ------------------------------ |
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48 * |
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49 * |
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50 * |
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51 * EXTERNAL REFERENCES: |
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52 * |
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53 * Name Description |
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54 * ------------------ ------------------------------------------------------- |
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55 * |
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56 * |
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57 * |
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58 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES: |
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59 * |
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60 * |
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61 * |
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62 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS: |
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63 * |
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64 * |
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65 * |
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66 * NOTES: |
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67 * |
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68 * |
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69 * |
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70 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES: |
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71 * |
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72 * |
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73 * |
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74 * |
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75 * DEVELOPMENT HISTORY: |
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76 * |
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77 * Date Name(s) Version Description |
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78 * ----------- -------------- ------- ------------------------------------- |
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79 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation |
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80 * |
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81 * ALGORITHM: |
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82 * |
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83 * |
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84 *****************************************************************************/ |
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85 |
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86 #include "l1sw.cfg" |
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87 #include "chipset.cfg" |
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88 |
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89 #if (CHIPSET == 12) |
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90 #if (OP_L1_STANDALONE == 0) |
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91 #include "main/sys_types.h" |
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92 #else |
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93 #include "sys_types.h" |
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94 #endif |
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95 #include "sys_map.h" |
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96 #include "sys_inth.h" |
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97 |
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98 /* GLOBAL CONSTANT VARIABLES: |
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99 * |
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100 * Variables Type Description |
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101 * --------------- ------- ----------------------------------------------- |
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102 * |
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103 */ |
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104 void f_inth_dummy(void); |
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105 |
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106 |
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107 /* GLOBAL CONSTANT VARIABLES: |
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108 * |
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109 * Variables Type Description |
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110 * --------------- ------- ----------------------------------------------- |
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111 * |
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112 */ |
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113 |
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114 |
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115 |
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116 |
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117 /* GLOBAL VARIABLES: |
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118 * |
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119 * Variables Type Description |
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120 * -------------------- ----------- -------------------------------------- |
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121 * a_inth_it_handlers SYS_FUNC ** Indirect function address for IRQ and |
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122 * FIQ on main interrupt handler. |
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123 * a_inth2_irq_handlers SYS_FUNC * Indirect function address for IRQ on |
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124 * 2nd level interrupt handler. |
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125 * d_inth_dummy SYS_UWORD32 Count the number of unwanted interrupts |
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126 */ |
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127 |
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128 SYS_FUNC a_inth_it_handlers[C_INTH_NUM_INT][2] = |
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129 { // IRQ FIQ |
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130 { f_inth_dummy, f_inth_dummy }, // 0 : WATCHDOG TIMER |
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131 { f_inth_dummy, f_inth_dummy }, // 1 : TIMER 1 |
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132 { f_inth_dummy, f_inth_dummy }, // 2 : TIMER 2 |
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133 { f_inth_dummy, f_inth_dummy }, // 3 : TSP RECEIVE |
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134 { f_inth_dummy, f_inth_dummy }, // 4 : TPU FRAME |
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135 { f_inth_dummy, f_inth_dummy }, // 5 : TPU PAGE |
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136 { f_inth_dummy, f_inth_dummy }, // 6 : SIM |
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137 { f_inth_dummy, f_inth_dummy }, // 7 : UART_MODEM1 |
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138 { f_inth_dummy, f_inth_dummy }, // 8 : KEYBOARD |
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139 { f_inth_dummy, f_inth_dummy }, // 9 : RTC_TIMER |
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140 { f_inth_dummy, f_inth_dummy }, // 10 : RTC_ALARM |
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141 { f_inth_dummy, f_inth_dummy }, // 11 : ULPD_GAUGING |
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142 { f_inth_dummy, f_inth_dummy }, // 12 : ABB_IRQ |
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143 { f_inth_dummy, f_inth_dummy }, // 13 : SPI |
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144 { f_inth_dummy, f_inth_dummy }, // 14 : DMA |
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145 { f_inth_dummy, f_inth_dummy }, // 15 : API |
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146 { f_inth_dummy, f_inth_dummy }, // 16 : GPIO |
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147 { f_inth_dummy, f_inth_dummy }, // 17 : ABB_FIQ |
4e78acac3d88
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148 { f_inth_dummy, f_inth_dummy }, // 18 : UART_IRDA |
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149 { f_inth_dummy, f_inth_dummy }, // 19 : ULPD GSM TIMER |
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150 { f_inth_dummy, f_inth_dummy }, // 20 : GEA |
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151 { f_inth_dummy, f_inth_dummy }, // 21 : EXTERNAL IRQ 1 |
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152 { f_inth_dummy, f_inth_dummy }, // 22 : EXTERNAL IRQ 2 |
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153 { f_inth_dummy, f_inth_dummy }, // 23 : USIM Card Detect |
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154 { f_inth_dummy, f_inth_dummy }, // 24 : USIM |
4e78acac3d88
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155 { f_inth_dummy, f_inth_dummy }, // 25 : LCD |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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156 { f_inth_dummy, f_inth_dummy }, // 26 : USB |
4e78acac3d88
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157 { f_inth_dummy, f_inth_dummy }, // 27 : MMC/SD/MS |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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158 { f_inth_dummy, f_inth_dummy }, // 28 : UART_MODEM2 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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159 { f_inth_2nd_level_handler, f_inth_dummy }, // 29 : 2nd Interrupt Handler |
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Mychaela Falconia <falcon@freecalypso.org>
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160 { f_inth_dummy, f_inth_dummy }, // 30 : I2C |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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161 { f_inth_dummy, f_inth_dummy } // 31 : NAND FLASH |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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162 }; |
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163 |
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164 SYS_FUNC a_inth2_irq_handlers[C_INTH_2ND_NUM_INT] = |
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165 { |
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166 f_inth_dummy, // 0 : RNG |
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167 f_inth_dummy, // 1 : SHA1/MD5 |
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168 f_inth_dummy, // 2 : EMPU |
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169 f_inth_dummy, // 3 : Secure DMA |
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170 f_inth_dummy // 4 : Secure TIMER |
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171 }; |
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172 |
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173 SYS_UWORD32 d_inth_dummy = 0L; |
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174 |
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175 |
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176 /****************************************************************************** |
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177 * |
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178 * FUNCTION NAME: f_inth_dummy |
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179 * Handle dummy interrupts. Call of this function should never occurs |
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180 * |
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181 * |
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182 * ARGUMENT LIST: |
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183 * |
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184 * Argument Type IO Description |
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185 * ------------ ------------------- -- --------------------------------- |
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186 * chip-select. |
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187 * |
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188 * RETURN VALUE: None |
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189 * |
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190 *****************************************************************************/ |
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191 |
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192 void f_inth_dummy(void) { |
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193 d_inth_dummy++; |
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194 } /* f_inth_dummy() */ |
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195 |
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196 |
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197 |
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198 /****************************************************************************** |
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199 * |
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200 * FUNCTION NAME: f_inth_irq_handler |
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201 * Entry point of ARM IRQ sub-routine. |
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202 * |
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203 * |
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204 * ARGUMENT LIST: |
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205 * |
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206 * Argument Type IO Description |
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207 * ------------ ------------------- -- --------------------------------- |
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Mychaela Falconia <falcon@freecalypso.org>
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208 * |
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209 * RETURN VALUE: None |
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210 * |
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Mychaela Falconia <falcon@freecalypso.org>
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211 *****************************************************************************/ |
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212 |
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213 void f_inth_irq_handler(void) { |
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214 |
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215 a_inth_it_handlers[F_INTH_GET_IRQ][C_INTH_IRQ](); /* ACK IT */ |
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Mychaela Falconia <falcon@freecalypso.org>
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216 F_INTH_VALID_NEXT(C_INTH_IRQ); /* valid next IRQ */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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217 |
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218 } /* f_inth_irq_handler() */ |
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219 |
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220 |
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221 |
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222 /****************************************************************************** |
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223 * |
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224 * FUNCTION NAME: f_inth_fiq_handler |
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225 * Entry point of ARM FIQ sub-routine. |
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226 * |
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227 * |
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228 * ARGUMENT LIST: |
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229 * |
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230 * Argument Type IO Description |
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231 * ------------ ------------------- -- --------------------------------- |
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232 * |
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233 * RETURN VALUE: None |
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234 * |
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235 *****************************************************************************/ |
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236 |
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237 void f_inth_fiq_handler(void) { |
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238 |
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239 a_inth_it_handlers[F_INTH_GET_FIQ][C_INTH_FIQ](); /* ACK IT */ |
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240 F_INTH_VALID_NEXT(C_INTH_FIQ); /* valid next FIQ */ |
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241 |
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242 } /* f_inth_fiq_handler() */ |
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243 |
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244 |
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245 |
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246 /****************************************************************************** |
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247 * |
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248 * FUNCTION NAME: f_inth_2nd_level_handler |
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249 * Sub-routine to manage 2nd level interrupt handler. |
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250 * |
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251 * |
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252 * ARGUMENT LIST: |
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253 * |
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254 * Argument Type IO Description |
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255 * ------------ ------------------- -- --------------------------------- |
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256 * |
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257 * RETURN VALUE: None |
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258 * |
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259 *****************************************************************************/ |
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260 |
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261 void f_inth_2nd_level_handler(void) { |
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262 |
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263 a_inth2_irq_handlers[F_INTH2_GET_IRQ](); /* ACK IT */ |
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264 F_INTH2_VALID_NEXT(C_INTH_IRQ); /* Valid next IRQ */ |
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265 |
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266 } /* f_inth_2nd_level_handler() */ |
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267 |
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268 |
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269 #endif /* (CHIPSET == 12) */ |