fc-tourmaline: src/cs/layer1/tpu_drivers/source0/tpudrv12.h annotate

annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 157:7eee5ad6ae86

mmiMmi.c: misc formatting fixes

author	Mychaela Falconia <falcon@freecalypso.org>
date	Mon, 16 Nov 2020 20:17:50 +0000
parents	4e78acac3d88
children	10b3a6876273

rev	line source
0 4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /**************** Revision Controle System Header *********************
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * GSM Layer 1 software
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 * Copyright (c) Texas Instruments 1998
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * Filename tpudrv12.h
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * Copyright 2003 (C) Texas Instruments
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 **************** Revision Controle System Header *********************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 //--- Configuration values
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 #define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 #define RF_VERSION 1 // 1 or V1, 5 for V5, etc
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 #define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 // TeST - Enable Main VCO buffer for test
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 #define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #include "rf.cfg"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 #include "fc-target.h"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 //--- RITA PG declaration
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 #define R_PG_10 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 #define R_PG_13 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 #define R_PG_20 2 // For RFPG 2.2, use 2.0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 #define R_PG_23 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 //--- PA declaration
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 #define PA_MGF9009 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 #define PA_RF3146 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 #define PA_RF3133 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 #define PA_PF08123B 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 #define PA_AWT6108 4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 #if (RF_PA == PA_MGF9009 \|\| RF_PA == PA_PF08123B)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #define PA_CTRL_INT 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #define PA_CTRL_INT 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 // AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 // This is also used in l1_rf12.h to select the SWAP_IQ
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 #if (RF_PG >= R_PG_20)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around")
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #elif (RF_PG == R_PG_13)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 //- Bit definitions for TST register programings, etc
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #define BIT_0 0x000001
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #define BIT_1 0x000002
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 #define BIT_2 0x000004
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #define BIT_3 0x000008
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define BIT_4 0x000010
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #define BIT_5 0x000020
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #define BIT_6 0x000040
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 #define BIT_7 0x000080
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #define BIT_8 0x000100
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #define BIT_9 0x000200
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #define BIT_10 0x000400
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #define BIT_11 0x000800
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 #define BIT_12 0x001000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #define BIT_13 0x002000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #define BIT_14 0x004000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 #define BIT_15 0x008000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 #define BIT_16 0x010000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #define BIT_17 0x020000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 #define BIT_18 0x040000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #define BIT_19 0x080000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 #define BIT_20 0x100000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 #define BIT_21 0x200000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 #define BIT_22 0x400000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 #define BIT_23 0x800000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 //--- TRF6151 definitions ------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 //- BASE REGISTER definitions
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #define REG_RX 0x000000 // MODE0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #define REG_PLL 0x000001 // MODE1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 #define REG_PWR 0x000002 // MODE2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #define REG_CFG 0x000003 // MODE3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 //- TeST REGISTER definitions => Used for WA only
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 // TeST - PLL2 WA => Define PLL2 TEST register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define TST_PLL2 0x00001E // MODE 14
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 // TeST - Enable Main VCO buffer for test => Define TST_VCO3 register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 #define TST_VCO3 0x00000F // MODE 15 (016+151)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 #define TST_VCO4 0x000024 // MODE 36 (216+41)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 // Alpha RF7 WA TeST registers
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #define TST_LDO 0x000027 // MODE 39 (216+71)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #define TST_PLL1 0x00001D // MODE 29 (116+131)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 #define TST_TX2 0x000037 // MODE 55 (316+71)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 // More Alpha RF7 WA TeST registers
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 #define TST_TX3 0x00003C // MODE 61 (316+121)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #define TST_TX4 0x00003D // MODE 61 (316+131)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 // PG 2.1 WA TeST registers
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 #define TST_PLL3 0x00001F // MODE 31 (116+151)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 // #define TST_PLL4 0x00002C // MODE 44 (216+121)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 #define TST_MISC 0x00003E // MODE 62 (316+141) => Used for setting the VCXO current
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112 #define TST_LO 0x00001C // MODE 28 (116+121)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 // Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 // UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that,
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 // when accessed, triggers the copy of the serial registers.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 // This is necessary to switch into "manual operation mode"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #define UPDATE_SERIAL_INTERFACE_COPY 0x000007
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 #define TX_LOOP_MANUAL BIT_3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 //- REG_RX - MODE0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #define BLOCK_DETECT_0 BIT_3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 #define BLOCK_DETECT_1 BIT_4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #define RST_BLOCK_DETECT_0 BIT_5
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 #define RST_BLOCK_DETECT_1 BIT_6
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 #define READ_EN BIT_7
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 #define RX_CAL_MODE BIT_8
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 #define RF_GAIN (BIT_10 \| BIT_9)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 //- REG_PLL - MODE1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 //PLL_REGB
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 //PLL_REGA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 //- REG_PWR - MODE2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 #define BANDGAP_MODE_OFF 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 #define BANDGAP_MODE_ON_ENA BIT_4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 #define BANDGAP_MODE_ON_DIS (BIT_4 \| BIT_3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 #define REGUL_MODE_ON BIT_5
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 // BIT[8..6] band
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 #define BAND_SELECT_GSM BIT_6
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 #define BAND_SELECT_DCS BIT_7
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 #define BAND_SELECT_850_LO BIT_8
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 #define BAND_SELECT_850_HI (BIT_8 \| BIT_6)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 #define BAND_SELECT_PCS (BIT_8 \| BIT_7)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 #define SYNTHE_MODE_OFF 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 #define SYNTHE_MODE_RX BIT_9
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #define SYNTHE_MODE_TX BIT_10
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 #define RX_MODE_OFF 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 #define RX_MODE_A BIT_11
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #define RX_MODE_B1 BIT_12
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 #define RX_MODE_B2 (BIT_12 \| BIT_11)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 #define TX_MODE_OFF 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 #define TX_MODE_ON BIT_13
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 #define PACTRL_APC_OFF 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #define PACTRL_APC_ON BIT_14
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 #define PACTRL_APC_DIS 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #define PACTRL_APC_ENA BIT_15
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 //- REG_CFG - MODE3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 // Common PA controller settings:
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 #define PACTRL_TYPE_PWR 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 #define PACTRL_TYPE_CUR BIT_3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 #define PACTRL_IDIOD_30_UA 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define PACTRL_IDIOD_300_UA BIT_4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 // PA controller Clara-like (Power Sensing) settings:
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #define PACTRL_VHOME_610_MV (BIT_7 \| BIT_5)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 #define PACTRL_VHOME_839_MV (BIT_7 \| BIT_5)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 #define PACTRL_VHOME_1000_MV (BIT_6 \| BIT_9)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 #define PACTRL_VHOME_1600_MV (BIT_8 \| BIT_5)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 #define PACTRL_RES_OPEN 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 #define PACTRL_RES_150_K BIT_10
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 #define PACTRL_RES_300_K BIT_11
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 #define PACTRL_RES_NU (BIT_10 \| BIT_11)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 #define PACTRL_CAP_0_PF 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 #define PACTRL_CAP_12_5_PF BIT_12
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 #define PACTRL_CAP_25_PF (BIT_13 \| BIT_12)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #define PACTRL_CAP_50_PF BIT_13
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 // PACTRL_CFG contains the configuration of the PACTRL that will
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 // be put into the REG_CFG register at initialization time
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 // in this #define!!!
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 #if (RF_PA == 0) // MGF9009 (LCPA)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 #define PACTRL_CFG \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 PACTRL_IDIOD_300_UA \| \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 PACTRL_CAP_25_PF \| \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 PACTRL_VHOME_1000_MV \| \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 PACTRL_RES_300_K
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 #elif (RF_PA == 1) // 3146
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #define PACTRL_CFG 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 #elif (RF_PA == 2) // 3133
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 #define PACTRL_CFG 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 #elif (RF_PA == 3) // PF08123B
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 #define PACTRL_CFG \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 PACTRL_TYPE_PWR \| \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 PACTRL_CAP_50_PF \| \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 PACTRL_RES_300_K \| \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 PACTRL_VHOME_610_MV
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 #elif (RF_PA == 4) // AWT6108
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 #define PACTRL_CFG 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 #error Unknown PA specifiec!
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 // Temperature sensor
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 #define TEMP_SENSOR_OFF 0x0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214 #define TEMP_SENSOR_ON BIT_14
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 // Internal Logic Init Disable
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 #define ILOGIC_INIT_DIS BIT_15
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 // ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 // It was introduced in PG 1.2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 // For previous PGs this BIT was unused, so it can be safelly programmed
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 // for all PGs
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 // RF signals connected to TSPACT [0..7]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 #ifdef CONFIG_TARGET_PIRELLI
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 #define RF_RESET_LINE BIT_5
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228 #define RF_RESET_LINE BIT_0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 #define RF_SER_ON RF_RESET_LINE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 #define RF_SER_OFF 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 #define TEST_TX_ON 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 #define TEST_RX_ON 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 #if defined(CONFIG_TARGET_LEONARDO) \|\| defined(CONFIG_TARGET_ESAMPLE) \|\| \
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 defined(CONFIG_TARGET_TANGO)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 // 4-band config (E-sample, P2, Leonardo)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 #define FEM_7 BIT_2 // act2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 #define FEM_8 BIT_1 // act1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 #define FEM_9 BIT_4 // act4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 #define PA_HI_BAND BIT_3 // act3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246 #define PA_LO_BAND 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 #define PA_OFF 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249 #define FEM_PINS (FEM_7 \| FEM_8 \| FEM_9)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 #define FEM_OFF ( FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 #define FEM_SLEEP ( 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 // This configuration is always inverted.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 // RX_UP/DOWN and TX_UP/DOWN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_7 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 #define RU_850 ( PA_OFF \| FEM_PINS ^ FEM_9 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_7 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_8 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_8 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278 #elif defined(CONFIG_TARGET_GTAMODEM) \|\| defined(CONFIG_TARGET_FCDEV3B)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 // Openmoko's triband configuration is a bastardized version
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281 // of TI's quadband one from Leonardo/E-Sample
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 #define FEM_7 BIT_2 // act2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 #define FEM_8 BIT_1 // act1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 #define FEM_9 BIT_4 // act4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 #define PA_HI_BAND BIT_3 // act3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 #define PA_LO_BAND 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 #define PA_OFF 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 #define FEM_PINS (FEM_7 \| FEM_8 \| FEM_9)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293 #define FEM_OFF ( FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 #define FEM_SLEEP ( 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297 // This configuration is always inverted.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 // RX_UP/DOWN and TX_UP/DOWN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_9 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_9 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_7 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 #define RU_1900 ( PA_OFF \| FEM_PINS ^ FEM_8 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_7 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 #elif defined(CONFIG_TARGET_MGC2GSMT)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323 * The common MGC2GSMT version of Huawei GTM900-B is very closely based
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 * on Leonardo (2-band version), but the two FEM Tx control signals
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 * are reversed.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 #define FEM_TX_LOW BIT_1 // act1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 #define FEM_TX_HIGH BIT_2 // act2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 #define PA_HI_BAND BIT_3 // act3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 #define PA_LO_BAND 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 #define PA_OFF 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 #define FEM_PINS (FEM_TX_LOW \| FEM_TX_HIGH)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 #define FEM_OFF ( FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 #define FEM_SLEEP ( 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 // This configuration is always inverted.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343 // RX_UP/DOWN and TX_UP/DOWN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 #elif defined(CONFIG_TARGET_PIRELLI)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 #define ANTSW_RX_PCS BIT_4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 #define ANTSW_TX_HIGH BIT_10
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368 #define ANTSW_TX_LOW BIT_11
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 #define PA_HI_BAND BIT_3 // act3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 #define PA_LO_BAND 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372 #define PA_OFF 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 #define PA_ENABLE BIT_0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376 // Pirelli uses a non-inverting buffer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378 #define FEM_OFF ( 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 #define FEM_SLEEP ( 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 // RX_UP/DOWN and TX_UP/DOWN (triband)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 #define RU_900 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384 #define RD_900 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 #define TU_900 ( PA_LO_BAND \| ANTSW_TX_LOW )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 #define TD_900 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 #define RU_850 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 #define RD_850 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390 #define TU_850 ( PA_LO_BAND \| ANTSW_TX_LOW )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 #define TD_850 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 #define RU_1800 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 #define RD_1800 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 #define TU_1800 ( PA_HI_BAND \| ANTSW_TX_HIGH )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 #define TD_1800 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398 #define RU_1900 ( PA_OFF \| ANTSW_RX_PCS )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 #define RD_1900 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400 #define TU_1900 ( PA_HI_BAND \| ANTSW_TX_HIGH )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 #define TD_1900 ( PA_OFF \| 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 #elif defined(CONFIG_TARGET_COMPAL)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405 #define PA_HI_BAND BIT_8 // act8
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 #define PA_LO_BAND 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 #define PA_OFF 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409 #define PA_ENABLE BIT_1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 // FEM control signals are active low
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412 #define FEM_PINS (BIT_6 \| BIT_2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 #define FEM_OFF ( FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 #define FEM_SLEEP ( 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 #define FEM_TX_HIGH BIT_6
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419 #if USE_TSPACT2_FOR_TXLOW
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 #define FEM_TX_LOW BIT_2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 #define FEM_TX_LOW BIT_6
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 // RX_UP/DOWN and TX_UP/DOWN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446 #endif // FreeCalypso target selection
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 #define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 #ifdef CONFIG_TARGET_PIRELLI
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 #define TC1_DEVICE_RF TC1_DEVICE1 // TSPEN1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 #define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 //--- TIMINGS ----------------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 /------------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 /* Download delay values */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 /------------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463 #define T TPU_CLOCK_RANGE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466 // - TPU instruction into TSP timings ---
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467 // 1 tpu instruction = 1 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 #define DLT_1 1 // 1 tpu instruction = 1 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469 #define DLT_2 2 // 2 tpu instruction = 2 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 #define DLT_3 3 // 3 tpu instruction = 3 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 #define DLT_4 4 // 4 tpu instruction = 4 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 #define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 // - Serialization timings ---
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 // The following values where calculated with Katrin Matthes...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 //#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed,
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 // // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478 //#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed,
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 // // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 // ... while the following values are based on the HYP004.doc document
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481 #define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed,
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 // i.e. 12 / 6 qbit = 2 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 #define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed,
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 // - TPU command execution + serialization length ---
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 #define DLT_1B 4 // 3*move + serialization of 7 bits
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 #define DLT_2B 7 // 4*move + serialization of 2 bytes
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 //#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490 //#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 // - INIT (delta or DLT) timings ---
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495 #define DLT_I2 8 // Time required to set RF_SER_OFF
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496 #define DLT_I3 5 // Time required to set RF_SER_ON
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 #define DLT_I4 110 // Regulator Turn-ON time
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500 // - tdt & rdt ---
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501 // MAX GSM (not GPRS) rdt and tdt values are...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 //#define rdt 380 // MAX GSM rx delta timing
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 //#define tdt 400 // MAX GSM tx delta timing
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504 // but current rdt and tdt values are...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 #define rdt 0 // rx delta timing
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 #define tdt 0 // tx delta timing
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508 // - RX timings ---
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509 // - RX down:
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 // The times below are offsets to when BDLENA goes down
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 #define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 #define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 // - RX up:
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 // The times below are offsets to when BDLENA goes high
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 // Burst data comes here
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 #define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518 #define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519 #define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 #define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 #define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 #define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 #define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 #define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527 // - TX timings ---
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528 // - TX down:
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 // The times below are offsets to when BULENA goes down
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 #if (PA_CTRL_INT == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 #define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 #define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 #if (PA_CTRL_INT == 0)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539 #define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 #define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 #define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 #define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546 // - TX up:
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 // The times below are offsets to when BULENA goes high
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 //burst data comes here
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549 #define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 #define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552 #if (PA_CTRL_INT == 0)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553 #define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 #define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 #define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 #define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 #define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 #define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561 // TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 #define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 #define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 #define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 #define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 #define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567 #define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568

FreeCalypso > hg > fc-tourmaline

annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 157:7eee5ad6ae86