FreeCalypso > hg > fc-tourmaline
annotate src/cs/drivers/drv_app/sim/sim.c @ 281:a75eefbf8be4
Phone boot with PWON: weed out short button presses
Every standard end user phone has a design provision, most naturally
implemented in firmware, whereby the PWON button effects a boot only
if it is held down long enough - short presses of this PWON button
are detected, assumed to be spurious and cause the fw to power back off
instead of proceeding with boot. The present change introduces this
standard function in FreeCalypso.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Fri, 24 Sep 2021 02:03:08 +0000 |
parents | c1205c437943 |
children |
rev | line source |
---|---|
0
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1 /* |
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2 * SIM.C |
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3 * |
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4 * Pole Star SIM |
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5 * |
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6 * Target : ARM |
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7 * |
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8 * |
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9 * SIM card driver. This module contents all functions |
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10 * included in specifications GSM 11.11 V4.10 |
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11 * |
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12 * |
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13 * Copyright (c) Texas Instruments 1995-1997 |
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14 * |
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15 */ |
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16 |
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17 #define SIM_C 1 |
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18 |
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19 #ifndef _WINDOWS |
189
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20 #include "l1sw.cfg" |
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21 #include "chipset.cfg" |
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22 #endif |
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23 |
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24 #include "main/sys_types.h" |
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25 |
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26 #include "memif/mem.h" |
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27 |
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28 //#include "assert.h" |
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29 #if (CHIPSET == 12) |
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30 #include "inth/sys_inth.h" |
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31 #else |
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32 #include "inth/iq.h" |
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33 #endif |
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34 #include "sim.h" |
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35 #include <string.h> |
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36 #include "armio/armio.h" |
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37 #include "ind_os.h" |
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38 #include "abb/abb.h" //controls level shifter of ABB |
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39 #include "ffs/ffs_api.h" /* FreeCalypso addition */ |
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40 |
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41 |
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42 //current voltage mode 3V or 5V, or 1.8V |
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43 SYS_UWORD8 CurrentVolt; |
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44 |
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45 /* FreeCalypso addition */ |
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46 SYS_UWORD8 SIM_allow_speed_enhancement = 1; |
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47 |
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48 |
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49 #ifdef SIM_DEBUG_TRACE |
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50 |
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51 #ifdef SIM_RETRY |
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52 /* one byte more to trace the number of retry for each functions */ |
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53 #define SIM_DBG_NULL 5 |
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54 #else |
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55 /* size of buffer tracing the reception of NULL byte */ |
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56 #define SIM_DBG_NULL 4 |
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57 #endif |
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58 |
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59 /* working buffer for NULL BYTE and number of RETRY */ |
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60 SYS_UWORD8 SIM_dbg_null[SIM_DBG_NULL]; |
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61 /* size of buffer tracing the chronology of calls */ |
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62 #define SIM_DBG_CMD 7500 |
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63 /* working buffer for chronology calls */ |
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64 SYS_UWORD8 SIM_dbg_cmd[SIM_DBG_CMD]; |
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65 /* index for positionning in working buffer for chronology calls */ |
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66 SYS_UWORD16 SIM_dbg_cmd_cmpt; |
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67 /* working variable to calculate the TDMA ecart */ |
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68 SYS_UWORD16 SIM_dbg_tdma_diff; |
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69 /* working variable to store the maximum TDMA frame between two characters */ |
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70 SYS_UWORD16 SIM_dbg_max_interchardelay; |
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71 /* working variable used in each L2/L3 access function */ |
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72 SYS_UWORD8 SIM_dbg_tmp[10]; |
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73 /* internal function due to factorization of use of traces */ |
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74 void SIM_dbg_write_trace(SYS_UWORD8 *ptr, SYS_UWORD16 len); |
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75 |
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76 #endif |
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77 |
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78 #ifdef SIM_RETRY |
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79 /* number of retry */ |
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80 #define NUM_SIM_RETRIES 10 |
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81 /* Add variables to support sim retry */ |
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82 SYS_UWORD8 SimRetries; |
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83 #endif |
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84 |
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85 |
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86 /* |
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87 * Low level routines : mapped to hardware |
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88 * SIM_WriteBuffer |
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89 * SIM_Command |
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90 * SIM_Reset |
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91 * |
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92 */ |
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93 |
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94 |
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95 /* |
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96 * SIM_WriteBuffer |
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97 * |
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98 * Write n bytes to SIM card in interrupt mode: |
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99 * return the line, write first byte and let interrupt handler do the rest |
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100 * return the line, write first byte and let interrupt handler do the rest |
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101 * |
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102 * Parameters : |
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103 * SIM_PORT *p : buffer for received chars |
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104 * offset : starting point for reading data. |
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105 * n : number of chars to read. |
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106 */ |
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107 void SIM_WriteBuffer(SIM_PORT *p, SYS_UWORD16 offset, SYS_UWORD16 n) |
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108 { |
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|
109 unsigned volatile i; |
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parents:
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110 |
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parents:
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111 // Set write direction |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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112 p->conf1 |= SIM_CONF1_TXRX; |
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113 p->c->conf1 = p->conf1; |
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114 |
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115 p->SWcount = 0; |
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116 p->rx_index = 0; |
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117 p->expected_data = 0; |
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118 |
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119 p->xOut = p->xbuf + offset; |
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120 p->xIn = p->xbuf + offset + n; |
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121 |
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122 if ((p->xIn - p->xOut) == 1) //if only one char is transmitted |
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123 { //need to wait a minimum of 1 ETU |
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Mychaela Falconia <falcon@freecalypso.org>
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124 ind_os_sleep (1); //for IO line to stay in TX mode |
189
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125 } |
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126 // Write first byte |
0
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127 p->c->tx = *(p->xOut); // transmit |
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128 |
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129 if ((p->xIn - p->xOut) == 1) //if only one char to transmit |
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130 { // return the direction to rx |
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131 p->conf1 &= ~SIM_CONF1_TXRX; //to be able to receive ACK char |
189
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132 p->c->conf1 = p->conf1; |
0
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133 |
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134 } |
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135 } |
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136 |
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137 /* |
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138 * SIM_Result |
189
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139 * |
0
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140 * Parameters : SIM port, buffer for received chars, pointer to receive size |
189
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141 * |
0
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142 * Return the result code (SW1/SW2) at the end of the string |
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143 */ |
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Mychaela Falconia <falcon@freecalypso.org>
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144 SYS_UWORD16 SIM_Result(SIM_PORT *p, SYS_UWORD8 *rP, SYS_UWORD16 *lenP, SYS_UWORD8 offset) |
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145 { |
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146 SYS_UWORD8 sw1, sw2; |
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147 SYS_UWORD8 verdict; |
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148 SYS_UWORD16 len; |
189
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149 |
0
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Mychaela Falconia <falcon@freecalypso.org>
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150 // Check if all characters were transmitted |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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151 if (p->xIn - 1 != p->xOut) |
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152 return (SIM_ERR_XMIT); |
189
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153 |
0
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
154 len = p->rx_index; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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155 *lenP = len - offset; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
156 if ((*lenP == 0) && (p->apdu_ans_length == 256)) |
191
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189
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157 *lenP = 256; |
0
4e78acac3d88
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158 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
159 if (p->expected_data == 256) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
160 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
161 verdict = SIM_Memcpy(rP, ((p->rbuf) + offset), 256 - offset); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
162 if (verdict != 0) |
189
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|
163 { |
0
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
164 return (verdict); |
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Mychaela Falconia <falcon@freecalypso.org>
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|
165 } |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
166 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
167 else if ((len != 0) && (len >= offset)) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
168 { |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
169 verdict = SIM_Memcpy(rP, ((p->rbuf) + offset), len - offset); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
170 if (verdict != 0) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
171 { |
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Mychaela Falconia <falcon@freecalypso.org>
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|
172 return (verdict); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
173 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
174 } |
189
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diff
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|
175 |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
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|
176 // change to remove SW1 and SW2 bytes from the receive buffer of data |
0
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
177 sw1 = p->rSW12[0]; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
178 sw2 = p->rSW12[1]; |
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|
179 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
180 return((sw1 << 8) | sw2); |
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Mychaela Falconia <falcon@freecalypso.org>
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|
181 } |
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Mychaela Falconia <falcon@freecalypso.org>
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|
182 |
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|
183 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
184 /* |
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Mychaela Falconia <falcon@freecalypso.org>
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|
185 * SIM_Command_base |
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parents:
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|
186 * |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
187 * Perform a command with the SIM T=0 protocol |
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Mychaela Falconia <falcon@freecalypso.org>
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|
188 * |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
189 * Arguments : pointer to SIM port structure |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
190 * number of characters above 5 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
191 * expected command time in TDMA |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
192 * |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
193 * Returns an error code : |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
194 * SIM_ERR_READ : no answer from the card to a command |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
195 * SIM_ERR_LEN : the answer is not corresponding to a |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
196 * correct answer of T=0 protocol |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
197 * 06/11/2002 JYT |
191
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189
diff
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|
198 * Modified to be base command function. New SIM_Command() created to call it |
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Mychaela Falconia <falcon@freecalypso.org>
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189
diff
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|
199 * with wrapper. Created to manage retries on Internals errors of the driver. |
0
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
200 */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
201 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
202 SYS_UWORD16 SIM_Command_Base(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *dP, SYS_UWORD16 *lP) |
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parents:
diff
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|
203 { |
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Mychaela Falconia <falcon@freecalypso.org>
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|
204 SYS_UWORD16 res; |
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Mychaela Falconia <falcon@freecalypso.org>
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|
205 SYS_UWORD8 err; |
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Mychaela Falconia <falcon@freecalypso.org>
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|
206 SYS_UWORD8 ins; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
207 SYS_UWORD8 nack; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
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|
208 SYS_UWORD8 nack1; |
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Mychaela Falconia <falcon@freecalypso.org>
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|
209 SYS_UWORD16 offset; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
210 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
211 if (SIM_sleep_status == SIM_SLEEP_DESACT) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
212 { //freeze the timer |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
213 status_os_sim = NU_Control_Timer (&SIM_timer, NU_DISABLE_TIMER); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
214 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
215 else if (SIM_sleep_status == SIM_SLEEP_ACT) |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
216 { //get out sleep mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
217 status_os_sim = NU_Control_Timer (&SIM_timer, NU_DISABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
218 SIM_SleepMode_Out (p); //get up SIM card of sleep mode before executing the command |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
219 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
220 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
221 SIM_WriteBuffer(p, 0, 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
222 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
223 //adaptative driver |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
224 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
225 if (n > 0) //need to send data to the card, TX mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
226 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
227 offset = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
228 // protocol T=0 returns a acknowledge char which is |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
229 // ins or (ins+1) : transmit the rest of the command in one time |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
230 // ~ins or ~(ins+1) : transmit the rest of the command char by char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
231 ins = p->xbuf[1] & p->hw_mask; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
232 nack = (~p->xbuf[1]) & p->hw_mask;; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
233 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
234 p->moderx = 6; //mode of wait for ACK char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
235 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
236 NEXT_CHAR_PROC: |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
237 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
238 if (err = SIM_Waitforchars(p, p->etu9600)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
239 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
240 if ((SIM_sleep_status == SIM_SLEEP_DESACT) || (SIM_sleep_status == SIM_SLEEP_ACT)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
241 { //enable to count 2.5s before entering in sleep mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
242 status_os_sim = NU_Reset_Timer (&SIM_timer, SIM_SleepMode_In, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
243 SIM_SLEEP_WAITING_TIME, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
244 0, NU_ENABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
245 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
246 return (err); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
247 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
248 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
249 if (p->moderx == 5) //return SW1/SW2 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
250 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
251 res = SIM_Result(p, dP, lP, 0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
252 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
253 if ((SIM_sleep_status == SIM_SLEEP_DESACT) || (SIM_sleep_status == SIM_SLEEP_ACT)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
254 { //enable to count 2.5s before entering in sleep mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
255 status_os_sim = NU_Reset_Timer (&SIM_timer, SIM_SleepMode_In, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
256 SIM_SLEEP_WAITING_TIME, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
257 0, NU_ENABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
258 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
259 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
260 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
261 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
262 else if ((p->ack & p->hw_mask) == ins) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
263 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
264 // Write the rest of the command if needed |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
265 // if more than 5 characters, the ack character will disappear |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
266 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
267 SIM_WriteBuffer(p, 5 + offset, n - offset); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
268 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
269 // special transmission mode if ACK = ~INS or ~(INS + 1). |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
270 // refer to ISO/CEI 7816-3 [8.2.2] |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
271 // need to send char by char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
272 else if ((p->ack & p->hw_mask) == nack) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
273 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
274 SIM_WriteBuffer(p, 5 + offset, 1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
275 offset++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
276 goto NEXT_CHAR_PROC; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
277 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
278 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
279 p->moderx = 5; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
280 if (err = SIM_Waitforchars (p, p->etu9600)) //wait SW1 / SW2 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
281 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
282 if ((SIM_sleep_status == SIM_SLEEP_DESACT) || (SIM_sleep_status == SIM_SLEEP_ACT)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
283 { //enable to count 2.5s before entering in sleep mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
284 status_os_sim = NU_Reset_Timer (&SIM_timer, SIM_SleepMode_In, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
285 SIM_SLEEP_WAITING_TIME, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
286 0, NU_ENABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
287 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
288 return (err); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
289 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
290 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
291 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
292 else //receive mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
293 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
294 if (err = SIM_WaitReception(p)) //wait for next procedure character |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
295 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
296 if ((SIM_sleep_status == SIM_SLEEP_DESACT) || (SIM_sleep_status == SIM_SLEEP_ACT)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
297 { //enable to count 2.5s before entering in sleep mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
298 status_os_sim = NU_Reset_Timer (&SIM_timer, SIM_SleepMode_In, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
299 SIM_SLEEP_WAITING_TIME, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
300 0, NU_ENABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
301 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
302 return (err); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
303 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
304 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
305 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
306 res = SIM_Result(p, dP, lP, 0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
307 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
308 if ((SIM_sleep_status == SIM_SLEEP_DESACT) || (SIM_sleep_status == SIM_SLEEP_ACT)) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
309 { //enable to count 2.5s before entering in sleep mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
310 status_os_sim = NU_Reset_Timer (&SIM_timer, SIM_SleepMode_In, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
311 SIM_SLEEP_WAITING_TIME, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
312 0, NU_ENABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
313 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
314 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
315 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
316 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
317 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
318 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
319 /* Main function to manage the retry mechanism */ |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
320 SYS_UWORD16 SIM_Command(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *dP, SYS_UWORD16 *lP) |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
321 { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
322 int res; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
323 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
324 #ifdef SIM_DEBUG_TRACE |
191
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189
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|
325 memset(SIM_dbg_null, 0x00, SIM_DBG_NULL); |
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189
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|
326 SIM_dbg_tdma_diff = 0; |
0
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
327 #endif |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
328 |
191
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189
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|
329 // Issue initial SIM_Command() call |
0
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
330 res = SIM_Command_Base(p, n, dP, lP); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
331 /* Change from to 10 to 15 for specific SIM card (Racal) */ |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
332 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
333 #ifdef SIM_RETRY |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
334 // While there is an error then retry NUM_SIM_RETRIES times |
191
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
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|
335 while ((res & 0xFF00) == 0) { // Reissue command |
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parents:
189
diff
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|
336 p->errorSIM = 0; |
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parents:
189
diff
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|
337 if(++SimRetries > NUM_SIM_RETRIES) { // return special retry failure |
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parents:
189
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338 res = SIM_ERR_RETRY_FAILURE; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
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339 break; |
0
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
340 } |
191
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
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|
341 res = SIM_Command_Base(p, n, dP, lP); |
c1205c437943
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
342 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
343 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
344 #ifdef SIM_DEBUG_TRACE |
191
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parents:
189
diff
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|
345 SIM_dbg_null[SIM_DBG_NULL-1] = SimRetries; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
346 #endif |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
347 |
191
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189
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|
348 SimRetries = 0; |
0
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
349 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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350 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
351 return(res); |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
352 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
353 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
354 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
355 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
356 * SIM_ByteReverse |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
357 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
358 * Reverse a byte, both up/down (1 <> 0) and left/right (0001 <> 1000) |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
359 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
360 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
361 SYS_UWORD8 SIM_ByteReverse(SYS_UWORD8 b) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
362 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
363 SYS_UWORD8 bh, bl; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
364 int i; |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
365 const SYS_UWORD8 Reverse[] = {0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, |
191
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parents:
189
diff
changeset
|
366 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF }; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
367 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
368 // Up/Down |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
369 b = ~ b; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
370 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
371 // left / right (by nibble) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
372 bh = (b >> 4) & 0xF; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
373 bl = b & 0xF; |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
374 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
375 b = (Reverse[bl]) << 4 | Reverse[bh]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
376 return(b); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
377 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
378 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
379 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
380 * SIM_TxParityErrors |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
381 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
382 * return number of transmit parity errors occured since the last reset |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
383 * of the SIM card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
384 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
385 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
386 SYS_UWORD16 SIM_TxParityErrors(void) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
387 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
388 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
389 |
191
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
390 p = &(Sim[0]); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
391 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
392 return(p->txParityErr); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
393 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
394 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
395 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
396 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
397 * SIM_Reset |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
398 * |
189
b37e6c916df1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
399 * Reset SIM card |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
400 * Call-back SIM insert if successful |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
401 * or SIM remove otherwise |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
402 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
403 * Returns 0 for success, or |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
404 * SIM_ERR_NOCARD : no card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
405 * SIM_ERR_NATR : no answer to reset |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
406 * SIM_ERR_NOINT : no |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
407 * SIM_ERR_READ : unknown data return by the card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
408 * SIM_ERR_CARDREJECT : card not accepted |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
409 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
410 * 29/01/02, JYT, adding of low voltage managment for IOTA device |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
411 * 06/10/03, JYT, Split of Reset to handle Restart |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
412 */ |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
413 SYS_UWORD16 SIM_Reset(SIM_CARD *cP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
414 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
415 return(SIM_Reset_Restart_Internal(cP, 1)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
416 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
417 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
418 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
419 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
420 * SIM_Restart |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
421 * |
189
b37e6c916df1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
422 * Restart SIM card |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
423 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
424 * Returns 0 for success, or |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
425 * SIM_ERR_NOCARD : no card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
426 * SIM_ERR_NATR : no answer to reset |
189
b37e6c916df1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
427 * SIM_ERR_NOINT : no |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
428 * SIM_ERR_READ : unknown data return by the card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
429 * SIM_ERR_CARDREJECT : card not accepted |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
430 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
431 * 06/10/03, JYT, Split of Reset to handle Restart |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
432 */ |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
433 SYS_UWORD16 SIM_Restart(SIM_CARD *cP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
434 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
435 return(SIM_Reset_Restart_Internal(cP, 0)); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
436 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
437 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
438 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
439 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
440 * SIM_Reset_Restart_Internal |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
441 * |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
442 * Reset SIM card |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
443 * Call-back SIM insert if successful |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
444 * or SIM remove otherwise |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
445 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
446 * Returns 0 for success, or |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
447 * SIM_ERR_NOCARD : no card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
448 * SIM_ERR_NATR : no answer to reset |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
449 * SIM_ERR_NOINT : no |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
450 * SIM_ERR_READ : unknown data return by the card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
451 * SIM_ERR_CARDREJECT : card not accepted |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
452 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
453 * 29/01/02, JYT, adding of low voltage managment for IOTA device |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
454 * 06/10/03, JYT, Split of Reset to handle Restart, ResetFlag added. |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
455 */ |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
456 SYS_UWORD16 SIM_Reset_Restart_Internal(SIM_CARD *cP, SYS_UWORD8 ResetFlag) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
457 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
458 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
459 unsigned int ATR_Attempt; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
460 SYS_UWORD8 BackValue; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
461 SYS_UWORD8 Result_ATR; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
462 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
463 #ifdef SIM_DEBUG_TRACE |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
464 memset(SIM_dbg_null, 0x00, SIM_DBG_NULL); |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
465 SIM_dbg_cmd_cmpt = 0; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
466 memset(SIM_dbg_cmd, 0x00, SIM_DBG_CMD); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
467 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
468 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
469 // Initialize pointers |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
470 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
471 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
472 // begin of JYT modifications |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
473 if ( (BackValue = SIM_StartVolt(ResetFlag)) != SIM_OK) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
474 return((SYS_UWORD16)BackValue); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
475 // end of JYT modifications |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
476 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
477 p->etu9600 = 867; // old = 239, increase of 363% |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
478 p->etu400 = 20; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
479 p->hw_mask = MASK_INS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
480 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
481 ATR_Attempt = 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
482 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
483 COLD_RESET: |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
484 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
485 p->SWcount = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
486 p->Freq_Algo = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
487 p->PTS_Try = 0; //use to calculate how many PTS try were already done |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
488 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
489 // Initialize pointers |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
490 p->xIn = p->xOut = p->xbuf; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
491 p->rx_index = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
492 p->errorSIM = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
493 p->moderx = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
494 p->null_received = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
495 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
496 BackValue = SIM_ManualStart(p); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
497 if (BackValue != 0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
498 return ((SYS_UWORD16)BackValue); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
499 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
500 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
501 p->c->conf1 = p->conf1 &= ~SIM_CONF1_BYPASS; //switch to automatic mode |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
502 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
503 //#else //SW_WRK_AROUND_H_S == 0 // Automatic procedure -> fails with test 27.11.2.1 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
504 // |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
505 // // Mask all interrupts |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
506 // p->c->maskit = SIM_MASK_NATR | SIM_MASK_WT | SIM_MASK_OV | |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
507 // SIM_MASK_TX | SIM_MASK_RX | SIM_MASK_CD; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
508 // |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
509 // |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
510 // IQ_Unmask (IQ_SIM); // Unmask interrupt controller |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
511 // |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
512 // |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
513 // p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_STOP; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
514 // ind_os_sleep(1); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
515 // |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
516 // p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_SWRST; // Set START bit and wait a while |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
517 // ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
518 // // Unmask all sources of interrupts except WT, OV, and NATR |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
519 // p->c->maskit = SIM_MASK_OV | SIM_MASK_WT | SIM_MASK_NATR; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
520 // |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
521 // // Set Configuration bits |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
522 // p->c->conf1 = p->conf1 = SIM_CONF1_SRSTLEV | SIM_CONF1_SCLKEN; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
523 // p->c->conf2 = 0x0940; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
524 // |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
525 // //enable VCC |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
526 // #if(ANLG_FAM == 1) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
527 // SPIABB_wa_VRPC (SPIRead_ABB_Register (PAGE1,VRPCCTRL1) | MODE_ENA_VCC); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
528 // #elif(ANLG_FAM == 2) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
529 // SPIABB_wa_VRPC (SPIRead_ABB_Register (PAGE1,VRPCSIM) | MODE_ENA_VCC); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
530 // #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
531 // p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_START; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
532 // |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
533 //#endif |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
534 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
535 /*-----------------------------------------------------------*/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
536 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
537 while (p->PTS_Try != 5) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
538 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
539 while (ATR_Attempt != 0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
540 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
541 // Treat ATR response |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
542 BackValue = SIM_ATRdynamictreatement (p, cP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
543 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
544 if (BackValue == SIM_ERR_NOCARD) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
545 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
546 SIM_PowerOff (); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
547 return (SIM_ERR_NOCARD); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
548 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
549 // ATR received but wrong characters value |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
550 // Comply with Test 27.11.2.4.5 and Test 27.11.1.3 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
551 else if (BackValue == SIM_ERR_CARDREJECT) |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
552 { |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
553 if (ATR_Attempt >= 3) |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
554 { |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
555 SIM_PowerOff (); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
556 return ((SYS_UWORD16)BackValue); |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
557 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
558 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
559 ATR_Attempt++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
560 SIM_WARMReset(p); // assert a reset during at least 400 ETU |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
561 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
562 else if (BackValue != 0) //SIM_ERR_WAIT |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
563 { |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
564 if (ATR_Attempt == 3) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
565 { // switch to 5V (ANALOG1) or 3V (ANALOG2) if card send wrong ATR 3 consecutive times |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
566 // Apply 3 consecutive resets at 5V (ANALOG1) or 3V (ANALOG2) |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
567 // fix prb for old chinese card not GSM compliant |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
568 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
569 if ((BackValue = SIM_SwitchVolt(ResetFlag)) != SIM_OK) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
570 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
571 // SIM cannot be supplied at 3V (ANALOG2), because of an Hardware failure |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
572 SIM_PowerOff (); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
573 return((SYS_UWORD16)BackValue); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
574 } |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
575 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
576 ATR_Attempt++; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
577 goto COLD_RESET; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
578 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
579 if (ATR_Attempt >= 6) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
580 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
581 SIM_PowerOff (); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
582 return ((SYS_UWORD16)BackValue); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
583 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
584 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
585 ATR_Attempt++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
586 SIM_WARMReset(p); // assert a reset during at least 400 ETU |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
587 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
588 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
589 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
590 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
591 ATR_Attempt = 0; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
592 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
593 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
594 /*-----------------------------------------------------------*/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
595 // PTS procedure |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
596 BackValue = SIM_PTSprocedure(cP,p); //assert PTS if needed |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
597 // need upgrade with FIFO use to avoid CPU overloading |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
598 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
599 if (BackValue) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
600 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
601 if (BackValue == SIM_ERR_CARDREJECT) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
602 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
603 SIM_PowerOff (); //must be done by protocol stack |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
604 return (SIM_ERR_CARDREJECT); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
605 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
606 if (p->PTS_Try <= 4) //else error treatement |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
607 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
608 SIM_WARMReset(p); // assert a reset during at least 400 ETU |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
609 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
610 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
611 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
612 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
613 p->PTS_Try = 5; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
614 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
615 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
616 /*-----------------------------------------------------------*/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
617 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
618 //interpret SIM coding concerning SIM supply voltage |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
619 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
620 if (SIM_GetFileCharacteristics(p)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
621 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
622 #if ((SIM_TYPE == SIM_TYPE_3V) || (SIM_TYPE == SIM_TYPE_1_8V)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
623 SIM_PowerOff(); // Needed for tests 27.17.1.5.1 and 27.17.1.5.5 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
624 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
625 return (SIM_ERR_READ); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
626 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
627 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
628 // JYT, certainly unused because of previous test |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
629 if(p->errorSIM) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
630 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
631 return(p->errorSIM); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
632 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
633 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
634 if ((p->FileC & SIM_MASK_INFO_VOLT) == SIM_5V) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
635 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
636 #if ((SIM_TYPE == SIM_TYPE_3V ) || (SIM_TYPE == SIM_TYPE_1_8_3V) || (SIM_TYPE == SIM_TYPE_1_8V)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
637 SIM_PowerOff (); // required by ETSI if 5V only card is detected and 3V only ME chosen |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
638 return (SIM_ERR_CARDREJECT); // Test 27.17.1.5.2 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
639 #elif (SIM_TYPE == SIM_TYPE_3_5V) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
640 if (CurrentVolt == SIM_3V) //if 5V only SIM present -> the ME may switch to 5V operation |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
641 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
642 if ((BackValue = SIM_SwitchVolt(ResetFlag)) != SIM_OK) // switch to 5V |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
643 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
644 SIM_PowerOff (); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
645 return ((SYS_UWORD16)BackValue); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
646 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
647 ATR_Attempt = 1; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
648 goto COLD_RESET; // Test 27.17.1.5.3 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
649 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
650 #endif |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
651 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
652 else |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
653 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
654 if ((p->FileC & SIM_MASK_INFO_VOLT) == SIM_3V) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
655 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
656 #if (SIM_TYPE == SIM_TYPE_1_8V) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
657 SIM_PowerOff (); // required by ETSI if 3V only card is detected and 1.8V only ME chosen |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
658 return (SIM_ERR_CARDREJECT); // Test 27.17.1.5.2 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
659 #elif (SIM_TYPE == SIM_TYPE_1_8_3V) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
660 if (CurrentVolt == SIM_1_8V) //if 3V only SIM present -> the ME may switch to 3V operation |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
661 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
662 if ((BackValue = SIM_SwitchVolt(ResetFlag)) != SIM_OK) // switch to 3V |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
663 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
664 SIM_PowerOff (); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
665 return ((SYS_UWORD16)BackValue); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
666 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
667 ATR_Attempt = 1; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
668 goto COLD_RESET; // Test 27.17.1.5.3 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
669 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
670 #endif |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
671 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
672 else |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
673 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
674 if ((p->FileC & SIM_MASK_INFO_VOLT) == SIM_1_8V) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
675 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
676 #if (SIM_TYPE == SIM_TYPE_5V) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
677 SIM_PowerOff (); // required by ETSI if 5V only card is detected and 3V only ME chosen |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
678 return (SIM_ERR_CARDREJECT); // Test 27.17.1.5.2 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
679 #endif |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
680 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
681 else |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
682 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
683 // future class of sim card voltage !!!!!! never use it |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
684 SIM_PowerOff (); // Rec. 11.18 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
685 return (SIM_ERR_CARDREJECT); |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
686 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
687 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
688 } |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
689 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
690 SIM_Interpret_FileCharacteristics(p); //find which frequency (13/4 or 13/8 Mhz) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
691 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
692 if(p->errorSIM) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
693 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
694 return(p->errorSIM); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
695 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
696 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
697 status_os_sim = NU_Control_Timer (&SIM_timer, NU_ENABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
698 //enable starting of the os timer for sleep mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
699 if (ResetFlag) { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
700 if (p->InsertFunc != NULL) |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
701 (p->InsertFunc)(cP); |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
702 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
703 |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
704 return(0); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
705 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
706 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
707 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
708 /* SIM manual start |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
709 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
710 * purpose : manage manual start of the SIM interface |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
711 * input : pointer on sim structure SIM_PORT |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
712 * output : none |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
713 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
714 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
715 SYS_UWORD16 SIM_ManualStart (SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
716 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
717 volatile int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
718 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
719 //!! |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
720 p->c->conf1 = p->conf1 = 0x8004; //set conf1 to automatic mode SIO low |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
721 //enable sim interface clock module |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
722 p->c->cmd = SIM_CMD_CLKEN; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
723 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
724 //#if (SW_WRK_AROUND_H_S == 1) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
725 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
726 // Mask all interrupts |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
727 p->c->maskit = SIM_MASK_NATR | SIM_MASK_WT | SIM_MASK_OV | |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
728 SIM_MASK_TX | SIM_MASK_RX | SIM_MASK_CD; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
729 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
730 // Unmask interrupt controller |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
731 IQ_Unmask (IQ_SIM); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
732 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
733 p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_STOP; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
734 ind_os_sleep (4); //wait 5 TDMA due to SVCC falling down duration |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
735 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
736 p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_SWRST; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
737 ind_os_sleep (1); //wait 5 TDMA due to SVCC falling down duration |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
738 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
739 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
740 p->c->conf2 = 0x0940; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
741 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
742 i = p->c->it; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
743 // Unmask all sources of interrupts except WT and OV and NATR |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
744 p->c->maskit = SIM_MASK_WT | SIM_MASK_OV | SIM_MASK_NATR; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
745 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
746 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
747 //enter in manual mode to start the ATR sequence |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
748 p->c->conf1 = p->conf1 |= SIM_CONF1_BYPASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
749 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
750 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
751 p->c->conf1 = p->conf1 |= SIM_CONF1_SVCCLEV; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
752 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
753 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
754 #if(ANLG_FAM == 1) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
755 //set OMEGA to 3V mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
756 //enable VCC |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
757 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) | MODE_ENA_SIMLDOEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
758 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
759 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) | MODE_ENA_SIMEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
760 ind_os_sleep(1); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
761 #elif(ANLG_FAM == 2) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
762 //set IOTA to 3V mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
763 //enable VCC |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
764 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCSIM) | MODE_ENA_SIMEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
765 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
766 #elif(ANLG_FAM == 3) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
767 //set SYREN to 3V mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
768 //enable VCC |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
769 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) | MODE_ENA_SIMEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
770 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
771 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
772 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
773 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SIOLOW; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
774 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
775 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
776 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
777 p->c->conf1 = p->conf1 |= SIM_CONF1_SCLKEN; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
778 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
779 p->c->conf1 = p->conf1 &= ~SIM_CONF1_TXRX; //set to receive mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
780 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
781 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
782 if(p->errorSIM) //check for card detection |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
783 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
784 return(p->errorSIM); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
785 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
786 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
787 i = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
788 while ((p->rx_index == 0) && (i < 3)) //wait 40000*Tsclk |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
789 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
790 ind_os_sleep (1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
791 i++; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
792 } |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
793 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
794 if ((p->rx_index == 0) && (i >= 3)) //external reset card ATR treatement |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
795 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
796 i = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
797 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
798 p->c->conf1 = p->conf1 |= SIM_CONF1_SRSTLEV;//set reset level to high level |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
799 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
800 while ((p->rx_index == 0) && (i < 3)) //wait 40000*Tsclk |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
801 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
802 ind_os_sleep (1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
803 i++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
804 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
805 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
806 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
807 return (0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
808 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
809 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
810 /* SIM manual stop |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
811 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
812 * purpose : manage manual start of the SIM interface |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
813 * input : pointer on sim structure SIM_PORT |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
814 * output : none |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
815 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
816 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
817 void SIM_ManualStop (SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
818 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
819 // to write |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
820 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
821 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
822 /* Power off SIM == SIM_CMD_STOP |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
823 * input : none |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
824 * output : none |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
825 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
826 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
827 void SIM_PowerOff(void) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
828 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
829 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
830 volatile SYS_UWORD16 cmd; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
831 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
832 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
833 // Initialize pointers |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
834 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
835 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
836 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
837 // Reset and wait a while |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
838 cmd = p->c->cmd; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
839 p->c->cmd = (cmd & MASK_CMD) | SIM_CMD_STOP; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
840 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
841 ind_os_sleep(5); //wait for falling of SIM signals (RESET/CLK/IO) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
842 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
843 #if(ANLG_FAM == 1) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
844 //disable VCC : disable level shifter then SVDD |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
845 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) & MODE_DIS_SIMEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
846 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) & MODE_DIS_SIMLDOEN); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
847 #elif(ANLG_FAM == 2) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
848 //disable VCC : disable level shifter then SVDD |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
849 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & MODE_DIS_SIMEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
850 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & MODE_DIS_SIMLDOEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
851 #elif(ANLG_FAM == 3) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
852 //disable VCC : disable level shifter then SVDD |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
853 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & MODE_DIS_SIMEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
854 ABB_wa_VRPC (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & MODE_DIS_SIMLDOEN); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
855 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
856 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
857 ind_os_sleep(10); //wait for falling of VCC commanf by ABB |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
858 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
859 p->c->cmd = 0x0000; //disable clock of sim module |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
860 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
861 if ((SIM_sleep_status == SIM_SLEEP_DESACT) || (SIM_sleep_status == SIM_SLEEP_ACT)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
862 { //SIM sleep timer is not more needed |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
863 status_os_sim = NU_Delete_Timer (&SIM_timer); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
864 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
865 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
866 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
867 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
868 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
869 * SIM_Init |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
870 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
871 * Function for backward compatibility only |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
872 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
873 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
874 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
875 void SIM_Init(void (Insert(SIM_CARD *cP)), void (Remove(void))) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
876 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
877 // Call SIM Registration function. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
878 (void) SIM_Register (Insert, Remove); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
879 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
880 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
881 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
882 * SIM_Initialize |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
883 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
884 * Initialize data structures. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
885 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
886 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
887 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
888 void SIM_Initialize(void) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
889 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
890 int n; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
891 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
892 volatile SYS_UWORD32 dum; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
893 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
894 /* FreeCalypso addition */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
895 ffs_file_read("/etc/SIM_spenh", &SIM_allow_speed_enhancement, 1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
896 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
897 // Initialize registers |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
898 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
899 p->c = (SIM_CONTROLLER *) SIM_CMD; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
900 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
901 p->errorSIM = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
902 dum = (volatile SYS_UWORD32) SIM_Dummy; // to force linking SIM32 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
903 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
904 status_os_sim = NU_Create_Timer (&SIM_timer, "SIM_sleep_timer", &SIM_SleepMode_In, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
905 0, SIM_SLEEP_WAITING_TIME, 0, NU_DISABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
906 //timer start only with NU_Control_Timer function |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
907 //waiting time set to 2.3s |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
908 SIM_sleep_status = SIM_SLEEP_NONE; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
909 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
910 #ifdef SIM_RETRY |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
911 SimRetries = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
912 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
913 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
914 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
915 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
916 * SIM_Register |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
917 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
918 * SIM Registration function: Initialize callback functions |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
919 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
920 * Insert(void) : pointer to the function called when a card is inserted |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
921 * Remove(void) : pointer to the function called when the card is removed |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
922 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
923 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
924 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
925 SYS_UWORD16 SIM_Register(void (Insert(SIM_CARD *cP)), void (Remove(void))) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
926 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
927 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
928 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
929 // Initialize pointers |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
930 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
931 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
932 p->InsertFunc = Insert; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
933 p->RemoveFunc = Remove; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
934 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
935 return (SIM_OK); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
936 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
937 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
938 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
939 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
940 * High level routines : mapped to GSM 11.11 function calls |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
941 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
942 * Uses a Nucleus semaphore to ensure no simultaneous access to SIM and buffer |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
943 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
944 * Each routine does : |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
945 * write command |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
946 * sleep long enough for the expected transmission and reception |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
947 * return rest code |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
948 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
949 * SYS_UWORD8 *result : pointer to the string return by the SIM card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
950 * SYS_UWORD8 *rcvSize : size of the string return by the SIM card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
951 * |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
952 * other parameters : parameters needed by the SIM card to |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
953 * execute the function. |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
954 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
955 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
956 //unsigned char SIM_flag = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
957 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
958 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
959 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
960 * SIM_Select |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
961 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
962 * Select a DF or a EF |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
963 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
964 SYS_UWORD16 SIM_Select(SYS_UWORD16 id, SYS_UWORD8 *dat, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
965 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
966 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
967 int res; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
968 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
969 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
970 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
971 p->xbuf[0] = GSM_CLASS; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
972 p->xbuf[1] = SIM_SELECT; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
973 p->xbuf[2] = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
974 p->xbuf[3] = 0; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
975 p->xbuf[4] = 2; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
976 p->xbuf[5] = id >> 8; // high byte |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
977 p->xbuf[6] = id & 0xFF; // low byte |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
978 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
979 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
980 res = SIM_Command(p, 2, dat, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
981 /* Change from to 10 to 15 for specific SIM card (Racal) */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
982 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
983 // if (id == 0x6F07) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
984 // SIM_flag = 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
985 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
986 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
987 SIM_dbg_write_trace((SYS_UWORD8 *)"AACMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
988 SIM_dbg_write_trace(p->xbuf, 7); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
989 SIM_dbg_write_trace((SYS_UWORD8 *)"AAANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
990 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
991 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
992 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
993 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
994 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
995 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
996 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
997 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
998 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
999 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1000 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1001 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1002 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1003 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1004 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1005 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1006 * SIM_Status |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1007 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1008 * Returns data received from card and number of bytes received |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1009 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1010 SYS_UWORD16 SIM_Status(SYS_UWORD8 *dat, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1011 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1012 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1013 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1014 short len = 0x16; // length specified in GSM 11.11 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1015 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1016 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1017 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1018 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1019 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1020 p->xbuf[1] = SIM_STATUS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1021 p->xbuf[2] = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1022 p->xbuf[3] = 0; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1023 p->xbuf[4] = len; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1024 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1025 res = SIM_Command(p, 0, dat, rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1026 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1027 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1028 SIM_dbg_write_trace((SYS_UWORD8 *)"ABCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1029 SIM_dbg_write_trace(p->xbuf, 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1030 SIM_dbg_write_trace((SYS_UWORD8 *)"ABANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1031 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1032 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1033 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1034 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1035 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1036 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1037 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1038 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1039 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1040 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1041 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1042 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1043 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1044 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1045 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1046 * SIM_Status_Extended |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1047 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1048 * Returns data received from card and number of bytes received |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1049 * Add extra parameter len : number of returned byte |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1050 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1051 SYS_UWORD16 SIM_Status_Extended(SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1052 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1053 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1054 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1055 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1056 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1057 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1058 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1059 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1060 p->xbuf[1] = SIM_STATUS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1061 p->xbuf[2] = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1062 p->xbuf[3] = 0; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1063 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1064 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1065 res = SIM_Command(p, 0, dat, rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1066 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1067 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1068 SIM_dbg_write_trace((SYS_UWORD8 *)"ACCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1069 SIM_dbg_write_trace(p->xbuf, 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1070 SIM_dbg_write_trace((SYS_UWORD8 *)"ACANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1071 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1072 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1073 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1074 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1075 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1076 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1077 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1078 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1079 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1080 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1081 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1082 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1083 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1084 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1085 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1086 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1087 * SIM_ReadBinary |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1088 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1089 * Read data from the current EF |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1090 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1091 SYS_UWORD16 SIM_ReadBinary(SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1092 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1093 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1094 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1095 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1096 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1097 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1098 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1099 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1100 p->xbuf[1] = SIM_READ_BINARY; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1101 p->xbuf[2] = offset >> 8; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1102 p->xbuf[3] = offset & 0xFF; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1103 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1104 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1105 res = SIM_Command(p, 0, dat, rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1106 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1107 // if (SIM_flag) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1108 // SIM_flag = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1109 // dat[0] = 0x08; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1110 // } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1111 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1112 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1113 SIM_dbg_write_trace((SYS_UWORD8 *)"ADCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1114 SIM_dbg_write_trace(p->xbuf, 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1115 SIM_dbg_write_trace((SYS_UWORD8 *)"ADANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1116 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1117 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1118 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1119 SIM_dbg_write_trace(dat, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1120 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1121 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1122 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1123 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1124 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1125 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1126 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1127 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1128 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1129 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1130 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1131 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1132 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1133 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1134 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1135 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1136 * SIM_VerifyChv |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1137 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1138 * Verify the specified CHV (chvType) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1139 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1140 SYS_UWORD16 SIM_VerifyCHV(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 chvType, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1141 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1142 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1143 SYS_UWORD8 len; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1144 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1145 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1146 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1147 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1148 len = 8; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1149 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1150 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1151 p->xbuf[1] = SIM_VERIFY_CHV; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1152 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1153 p->xbuf[3] = chvType; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1154 p->xbuf[4] = len; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1155 for (i=0;i<8;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1156 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1157 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1158 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1159 res = SIM_Command(p, 8, result, rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1160 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1161 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1162 SIM_dbg_write_trace((SYS_UWORD8 *)"AECMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1163 SIM_dbg_write_trace(p->xbuf, len+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1164 SIM_dbg_write_trace((SYS_UWORD8 *)"AEANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1165 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1166 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1167 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1168 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1169 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1170 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1171 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1172 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1173 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1174 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1175 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1176 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1177 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1178 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1179 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1180 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1181 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1182 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1183 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1184 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1185 * SIM_RunGSMAlgo |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1186 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1187 * Authentication procedure |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1188 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1189 SYS_UWORD16 SIM_RunGSMAlgo(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1190 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1191 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1192 int len; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1193 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1194 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1195 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1196 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1197 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1198 if(p->Freq_Algo) //13/4 Mhz mandatory ?? |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1199 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SCLKDIV; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1200 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1201 len = 16; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1202 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1203 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1204 p->xbuf[1] = SIM_RUN_GSM_ALGO; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1205 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1206 p->xbuf[3] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1207 p->xbuf[4] = len; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1208 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1209 for (i=0;i<len;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1210 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1211 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1212 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1213 res = SIM_Command(p, len, result, rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1214 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1215 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1216 SIM_dbg_write_trace((SYS_UWORD8 *)"AFCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1217 SIM_dbg_write_trace(p->xbuf, len+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1218 SIM_dbg_write_trace((SYS_UWORD8 *)"AFANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1219 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1220 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1221 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1222 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1223 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1224 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1225 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1226 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1227 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1228 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1229 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1230 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1231 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1232 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1233 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1234 if(p->Freq_Algo) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1235 p->c->conf1 = p->conf1 |= SIM_CONF1_SCLKDIV; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1236 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1237 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1238 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1239 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1240 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1241 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1242 * SIM_GetResponse |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1243 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1244 * Get data from the card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1245 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1246 * SYS_UWORD8 len : length of the data to get |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1247 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1248 SYS_UWORD16 SIM_GetResponse(SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1249 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1250 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1251 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1252 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1253 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1254 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1255 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1256 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1257 p->xbuf[1] = SIM_GET_RESPONSE; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1258 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1259 p->xbuf[3] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1260 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1261 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1262 res = SIM_Command(p, 0, dat, rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1263 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1264 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1265 SIM_dbg_write_trace((SYS_UWORD8 *)"AGCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1266 SIM_dbg_write_trace(p->xbuf, 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1267 SIM_dbg_write_trace((SYS_UWORD8 *)"AGANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1268 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1269 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1270 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1271 SIM_dbg_write_trace(dat, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1272 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1273 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1274 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1275 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1276 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1277 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1278 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1279 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1280 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1281 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1282 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1283 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1284 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1285 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1286 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1287 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1288 * SIM_ChangeCHV |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1289 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1290 * Change the specified CHV (chvType) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1291 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1292 SYS_UWORD16 SIM_ChangeCHV(SYS_UWORD8 *result,SYS_UWORD8 *oldChv, SYS_UWORD8 *newChv, SYS_UWORD8 chvType, SYS_UWORD16 *lP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1293 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1294 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1295 SYS_UWORD16 len; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1296 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1297 SYS_UWORD16 res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1298 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1299 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1300 len = 16; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1301 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1302 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1303 p->xbuf[1] = SIM_CHANGE_CHV; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1304 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1305 p->xbuf[3] = chvType; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1306 p->xbuf[4] = (SYS_UWORD8)len; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1307 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1308 // Copy bytes to buffer |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1309 for (i=0;i<8;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1310 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1311 p->xbuf[5+i] = *(oldChv+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1312 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1313 for (i=0;i<8;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1314 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1315 p->xbuf[13+i] = *(newChv+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1316 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1317 res = SIM_Command(p, len, result, lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1318 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1319 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1320 SIM_dbg_write_trace((SYS_UWORD8 *)"AHCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1321 SIM_dbg_write_trace(p->xbuf, len+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1322 SIM_dbg_write_trace((SYS_UWORD8 *)"AHANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1323 SIM_dbg_tmp[0] = (SYS_UWORD8)(*lP >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1324 SIM_dbg_tmp[1] = (SYS_UWORD8)(*lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1325 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1326 SIM_dbg_write_trace(result, *lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1327 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1328 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1329 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1330 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1331 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1332 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1333 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1334 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1335 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1336 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1337 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1338 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1339 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1340 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1341 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1342 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1343 * SIM_DisableCHV |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1344 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1345 * Disable CHV 1 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1346 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1347 SYS_UWORD16 SIM_DisableCHV(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 *lP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1348 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1349 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1350 int len; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1351 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1352 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1353 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1354 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1355 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1356 len = 8; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1357 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1358 p->xbuf[1] = SIM_DISABLE_CHV; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1359 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1360 p->xbuf[3] = 1; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1361 p->xbuf[4] = 8; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1362 for (i=0;i<8;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1363 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1364 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1365 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1366 res = SIM_Command(p, len, result, lP); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1367 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1368 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1369 SIM_dbg_write_trace((SYS_UWORD8 *)"AICMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1370 SIM_dbg_write_trace(p->xbuf, 8+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1371 SIM_dbg_write_trace((SYS_UWORD8 *)"AIANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1372 SIM_dbg_tmp[0] = (SYS_UWORD8)(*lP >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1373 SIM_dbg_tmp[1] = (SYS_UWORD8)(*lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1374 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1375 SIM_dbg_write_trace(result, *lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1376 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1377 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1378 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1379 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1380 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1381 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1382 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1383 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1384 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1385 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1386 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1387 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1388 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1389 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1390 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1391 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1392 * SIM_EnableCHV |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1393 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1394 * Enable CHV 1 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1395 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1396 SYS_UWORD16 SIM_EnableCHV(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 *lP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1397 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1398 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1399 int len; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1400 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1401 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1402 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1403 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1404 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1405 len = 8; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1406 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1407 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1408 p->xbuf[1] = SIM_ENABLE_CHV; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1409 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1410 p->xbuf[3] = 1; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1411 p->xbuf[4] = (SYS_UWORD8)len; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1412 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1413 for (i=0;i<len;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1414 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1415 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1416 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1417 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1418 res = SIM_Command(p, len, result, lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1419 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1420 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1421 SIM_dbg_write_trace((SYS_UWORD8 *)"AJCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1422 SIM_dbg_write_trace(p->xbuf, len+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1423 SIM_dbg_write_trace((SYS_UWORD8 *)"AJANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1424 SIM_dbg_tmp[0] = (SYS_UWORD8)(*lP >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1425 SIM_dbg_tmp[1] = (SYS_UWORD8)(*lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1426 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1427 SIM_dbg_write_trace(result, *lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1428 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1429 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1430 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1431 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1432 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1433 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1434 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1435 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1436 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1437 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1438 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1439 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1440 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1441 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1442 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1443 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1444 * SIM_UnblockCHV |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1445 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1446 * Unblock the specified CHV (chvType) and store a new CHV |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1447 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1448 SYS_UWORD16 SIM_UnblockCHV(SYS_UWORD8 *result, SYS_UWORD8 *unblockChv, SYS_UWORD8 *newChv, |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1449 SYS_UWORD8 chvType, SYS_UWORD16 *lP) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1450 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1451 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1452 int len; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1453 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1454 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1455 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1456 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1457 len = 16; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1458 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1459 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1460 p->xbuf[1] = SIM_UNBLOCK_CHV; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1461 p->xbuf[2] = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1462 p->xbuf[3] = chvType; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1463 p->xbuf[4] = (SYS_UWORD8)len; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1464 for (i=0;i<8;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1465 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1466 p->xbuf[5+i] = *(unblockChv+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1467 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1468 for (i=0;i<8;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1469 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1470 p->xbuf[13+i] = *(newChv+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1471 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1472 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1473 res = SIM_Command(p, len, result, lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1474 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1475 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1476 SIM_dbg_write_trace((SYS_UWORD8 *)"AKCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1477 SIM_dbg_write_trace(p->xbuf, len+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1478 SIM_dbg_write_trace((SYS_UWORD8 *)"AKANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1479 SIM_dbg_tmp[0] = (SYS_UWORD8)(*lP >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1480 SIM_dbg_tmp[1] = (SYS_UWORD8)(*lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1481 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1482 SIM_dbg_write_trace(result, *lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1483 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1484 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1485 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1486 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1487 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1488 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1489 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1490 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1491 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1492 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1493 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1494 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1495 } |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1496 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1497 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1498 * SIM_Invalidate |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1499 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1500 * Invalidate the current EF |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1501 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1502 SYS_UWORD16 SIM_Invalidate(SYS_UWORD8 *rP, SYS_UWORD16 *lP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1503 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1504 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1505 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1506 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1507 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1508 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1509 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1510 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1511 p->xbuf[1] = SIM_INVALIDATE; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1512 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1513 p->xbuf[3] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1514 p->xbuf[4] = 0; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1515 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1516 res = SIM_Command(p, 0, rP, lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1517 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1518 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1519 SIM_dbg_write_trace((SYS_UWORD8 *)"ALCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1520 SIM_dbg_write_trace(p->xbuf, 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1521 SIM_dbg_write_trace((SYS_UWORD8 *)"ALANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1522 SIM_dbg_tmp[0] = (SYS_UWORD8)(*lP >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1523 SIM_dbg_tmp[1] = (SYS_UWORD8)(*lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1524 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1525 SIM_dbg_write_trace(rP, *lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1526 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1527 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1528 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1529 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1530 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1531 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1532 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1533 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1534 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1535 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1536 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1537 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1538 } |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1539 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1540 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1541 * SIM_Rehabilitate |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1542 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1543 * Rehabilitate the current EF |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1544 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1545 SYS_UWORD16 SIM_Rehabilitate(SYS_UWORD8 *rP, SYS_UWORD16 *lP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1546 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1547 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1548 int len; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1549 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1550 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1551 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1552 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1553 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1554 p->xbuf[1] = SIM_REHABILITATE; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1555 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1556 p->xbuf[3] = 0; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1557 p->xbuf[4] = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1558 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1559 res = SIM_Command(p, 0, rP, lP); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1560 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1561 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1562 SIM_dbg_write_trace((SYS_UWORD8 *)"AMCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1563 SIM_dbg_write_trace(p->xbuf, 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1564 SIM_dbg_write_trace((SYS_UWORD8 *)"AMANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1565 SIM_dbg_tmp[0] = (SYS_UWORD8)(*lP >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1566 SIM_dbg_tmp[1] = (SYS_UWORD8)(*lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1567 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1568 SIM_dbg_write_trace(rP, *lP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1569 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1570 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1571 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1572 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1573 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1574 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1575 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1576 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1577 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1578 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1579 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1580 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1581 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1582 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1583 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1584 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1585 * SIM_UpdateBinary |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1586 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1587 * Store data in the current transparent EF |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1588 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1589 SYS_UWORD16 SIM_UpdateBinary(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1590 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1591 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1592 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1593 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1594 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1595 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1596 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1597 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1598 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1599 p->xbuf[1] = SIM_UPDATE_BINARY; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1600 p->xbuf[2] = offset >> 8; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1601 p->xbuf[3] = offset & 0xFF; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1602 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1603 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1604 for (i=0;i<llen;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1605 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1606 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1607 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1608 res = SIM_Command(p, llen, result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1609 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1610 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1611 SIM_dbg_write_trace((SYS_UWORD8 *)"ANCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1612 SIM_dbg_write_trace(p->xbuf, llen+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1613 SIM_dbg_write_trace((SYS_UWORD8 *)"ANANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1614 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1615 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1616 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1617 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1618 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1619 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1620 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1621 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1622 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1623 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1624 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1625 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1626 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1627 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1628 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1629 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1630 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1631 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1632 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1633 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1634 * SIM_ReadRecord |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1635 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1636 * Read a record (recNum) from the current linear fixed or cyclic EF |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1637 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1638 SYS_UWORD16 SIM_ReadRecord(SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1639 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1640 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1641 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1642 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1643 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1644 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1645 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1646 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1647 p->xbuf[1] = SIM_READ_RECORD; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1648 p->xbuf[2] = recNum; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1649 p->xbuf[3] = mode; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1650 p->xbuf[4] = (SYS_UWORD8)llen; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1651 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1652 res = SIM_Command(p, 0, dat, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1653 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1654 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1655 SIM_dbg_write_trace((SYS_UWORD8 *)"AOCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1656 SIM_dbg_write_trace(p->xbuf, llen+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1657 SIM_dbg_write_trace((SYS_UWORD8 *)"AOANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1658 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1659 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1660 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1661 SIM_dbg_write_trace(dat, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1662 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1663 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1664 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1665 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1666 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1667 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1668 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1669 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1670 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1671 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1672 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1673 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1674 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1675 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1676 #ifdef SIM_APDU_TEST |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1677 SYS_UWORD8 snd[270]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1678 SYS_UWORD8 rec[270]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1679 SYS_UWORD8 logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1680 SYS_UWORD16 recl; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1681 unsigned short resopen, resclose, rescmd; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1682 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1683 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1684 #ifdef SIM_SAT_REFRESH_TEST |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1685 SIM_CARD ptr; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1686 SYS_UWORD16 lrcvSize; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1687 SYS_UWORD8 ldat[20]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1688 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1689 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1690 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1691 * SIM_UpdateRecord |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1692 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1693 * Store a record (recNum) in the current linear fixed or cyclic EF |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1694 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1695 SYS_UWORD16 SIM_UpdateRecord(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1696 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1697 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1698 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1699 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1700 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1701 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1702 #ifdef SIM_SAT_REFRESH_TEST |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1703 // do 1000 times the following sequence |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1704 for (i=0;i<1000;i++) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1705 SIM_PowerOff(); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1706 SIM_Restart(&ptr); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1707 SIM_Select((SYS_UWORD16)0x7f10, ldat, &lrcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1708 SIM_Select((SYS_UWORD16)0x6f3a, ldat, &lrcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1709 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1710 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1711 #ifdef SIM_APDU_TEST |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1712 // send OPEN LOGICAL CHANNEL |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1713 snd[0] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1714 snd[1] = 0x70; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1715 snd[2] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1716 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1717 snd[4] = 0x01; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1718 resopen = SIM_XchTPDU(&snd[0], 5, &rec[0], 1, &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1719 if (resopen == 0x9000) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1720 logchan = rec[0]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1721 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1722 // Select AID PKCS |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1723 snd[0] = logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1724 snd[1] = 0xA4; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1725 snd[2] = 0x04; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1726 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1727 snd[4] = 0x0C; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1728 snd[5] = 0xA0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1729 snd[6] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1730 snd[7] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1731 snd[8] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1732 snd[9] = 0x63; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1733 snd[10] = 0x50; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1734 snd[11] = 0x4B; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1735 snd[12] = 0x43; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1736 snd[13] = 0x53; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1737 snd[14] = 0x2D; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1738 snd[15] = 0x31; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1739 snd[16] = 0x35; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1740 rescmd = SIM_XchTPDU(&snd[0], 17, &rec[0], 0, &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1741 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1742 // Select file EF odf |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1743 snd[0] = 0x80 | logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1744 snd[1] = 0xA4; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1745 snd[2] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1746 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1747 snd[4] = 0x02; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1748 snd[5] = 0x50; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1749 snd[6] = 0x31; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1750 rescmd = SIM_XchTPDU(&snd[0], 7, &rec[0], 0, &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1751 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1752 // get response EF odf |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1753 snd[0] = logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1754 snd[1] = 0xC0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1755 snd[2] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1756 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1757 snd[4] = rescmd; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1758 rescmd = SIM_XchTPDU(&snd[0], 5, &rec[0], snd[4], &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1759 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1760 // read binary EF odf |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1761 snd[0] = 0x80 | logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1762 snd[1] = 0xB0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1763 snd[2] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1764 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1765 snd[4] = rec[3]-16; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1766 rescmd = SIM_XchTPDU(&snd[0], 5, &rec[0], snd[4], &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1767 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1768 // Select file EF cdf |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1769 snd[0] = 0x80 | logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1770 snd[1] = 0xA4; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1771 snd[2] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1772 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1773 snd[4] = 0x02; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1774 snd[5] = 0x51; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1775 snd[6] = 0x03; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1776 rescmd = SIM_XchTPDU(&snd[0], 7, &rec[0], 0, &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1777 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1778 // get response EF odf |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1779 snd[0] = logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1780 snd[1] = 0xC0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1781 snd[2] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1782 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1783 snd[4] = rescmd; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1784 rescmd = SIM_XchTPDU(&snd[0], 5, &rec[0], snd[4], &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1785 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1786 // read binary EF cdf |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1787 snd[0] = 0x80 | logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1788 snd[1] = 0xB0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1789 snd[2] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1790 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1791 snd[4] = 0xff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1792 rescmd = SIM_XchTPDU(&snd[0], 5, &rec[0], snd[4], &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1793 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1794 // read binary EF cdf |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1795 snd[0] = 0x80 | logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1796 snd[1] = 0xB0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1797 snd[2] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1798 snd[3] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1799 snd[4] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1800 rescmd = SIM_XchTPDU(&snd[0], 5, &rec[0], 256, &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1801 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1802 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1803 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1804 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1805 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1806 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1807 p->xbuf[1] = SIM_UPDATE_RECORD; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1808 p->xbuf[2] = recNum; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1809 p->xbuf[3] = mode; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1810 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1811 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1812 for (i=0;i<llen;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1813 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1814 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1815 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1816 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1817 res = SIM_Command(p, llen, result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1818 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1819 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1820 SIM_dbg_write_trace((SYS_UWORD8 *)"APCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1821 SIM_dbg_write_trace(p->xbuf, llen+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1822 SIM_dbg_write_trace((SYS_UWORD8 *)"APANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1823 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1824 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1825 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1826 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1827 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1828 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1829 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1830 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1831 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1832 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1833 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1834 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1835 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1836 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1837 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1838 #ifdef SIM_APDU_TEST |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1839 // send CLOSE LOGICAL CHANNEL |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1840 snd[0] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1841 snd[1] = 0x70; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1842 snd[2] = 0x80; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1843 snd[3] = logchan; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1844 snd[4] = 0x00; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1845 resclose = SIM_XchTPDU(&snd[0], 5, &rec[0], 0, &recl); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1846 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1847 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1848 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1849 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1850 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1851 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1852 * SIM_Seek |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1853 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1854 * Search data in a linear fixed or cyclic EF. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1855 * return the first record number in which it found the data. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1856 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1857 SYS_UWORD16 SIM_Seek(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1858 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1859 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1860 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1861 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1862 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1863 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1864 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1865 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1866 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1867 p->xbuf[1] = SIM_SEEK; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1868 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1869 p->xbuf[3] = mode; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1870 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1871 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1872 for (i=0;i<llen;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1873 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1874 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1875 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1876 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1877 res = SIM_Command(p, llen, result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1878 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1879 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1880 SIM_dbg_write_trace((SYS_UWORD8 *)"AQCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1881 SIM_dbg_write_trace(p->xbuf, llen+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1882 SIM_dbg_write_trace((SYS_UWORD8 *)"AQANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1883 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1884 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1885 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1886 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1887 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1888 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1889 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1890 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1891 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1892 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1893 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1894 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1895 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1896 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1897 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1898 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1899 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1900 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1901 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1902 * SIM_Increase |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1903 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1904 * Add value to a record of a cyclic EF |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1905 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1906 SYS_UWORD16 SIM_Increase(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1907 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1908 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1909 int len; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1910 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1911 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1912 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1913 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1914 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1915 len = 3; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1916 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1917 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1918 p->xbuf[1] = SIM_INCREASE; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1919 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1920 p->xbuf[3] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1921 p->xbuf[4] = 3; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1922 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1923 for (i=0;i<3;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1924 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1925 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1926 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1927 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1928 res = SIM_Command(p, len, result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1929 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1930 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1931 SIM_dbg_write_trace((SYS_UWORD8 *)"ARCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1932 SIM_dbg_write_trace(p->xbuf, 3+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1933 SIM_dbg_write_trace((SYS_UWORD8 *)"ARANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1934 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1935 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1936 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1937 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1938 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1939 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1940 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1941 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1942 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1943 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1944 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1945 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1946 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1947 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1948 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1949 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1950 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1951 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1952 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1953 * SIM_TerminalProfile |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1954 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1955 * Used by ME to send its toolkit capabilities to SIM |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1956 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1957 SYS_UWORD16 SIM_TerminalProfile(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1958 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1959 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1960 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1961 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
1962 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1963 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1964 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1965 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1966 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1967 p->xbuf[1] = SIM_TERMINAL_PROFILE; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1968 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1969 p->xbuf[3] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1970 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1971 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1972 for (i=0;i<llen;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1973 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1974 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1975 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1976 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
1977 res = SIM_Command(p, llen, result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1978 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1979 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1980 SIM_dbg_write_trace((SYS_UWORD8 *)"ASCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1981 SIM_dbg_write_trace(p->xbuf, llen+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1982 SIM_dbg_write_trace((SYS_UWORD8 *)"ASANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1983 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1984 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1985 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1986 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1987 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1988 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1989 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1990 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1991 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1992 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1993 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1994 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1995 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1996 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1997 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1998 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1999 * SIM_FETCH |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2000 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2001 * Used by ME to inquiry of what SIM toolkit need to do |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2002 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2003 SYS_UWORD16 SIM_Fetch(SYS_UWORD8 *result, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2004 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2005 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2006 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2007 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2008 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2009 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2010 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2011 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2012 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2013 p->xbuf[1] = SIM_FETCH; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2014 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2015 p->xbuf[3] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2016 p->xbuf[4] = (SYS_UWORD8)llen; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2017 |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2018 res = SIM_Command(p, 0, result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2019 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2020 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2021 SIM_dbg_write_trace((SYS_UWORD8 *)"ATCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2022 SIM_dbg_write_trace(p->xbuf, 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2023 SIM_dbg_write_trace((SYS_UWORD8 *)"ATANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2024 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2025 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2026 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2027 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2028 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2029 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2030 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2031 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2032 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2033 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2034 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2035 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2036 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2037 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2038 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2039 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2040 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2041 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2042 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2043 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2044 * SIM_TerminalResponse * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2045 * Used for ME to respond at a SIM toolkit command |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2046 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2047 SYS_UWORD16 SIM_TerminalResponse(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2048 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2049 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2050 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2051 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2052 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2053 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2054 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2055 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2056 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2057 p->xbuf[1] = SIM_TERMINAL_RESPONSE; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2058 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2059 p->xbuf[3] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2060 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2061 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2062 for (i=0;i<llen;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2063 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2064 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2065 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2066 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2067 res = SIM_Command(p, llen, result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2068 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2069 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2070 SIM_dbg_write_trace((SYS_UWORD8 *)"AUCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2071 SIM_dbg_write_trace(p->xbuf, llen+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2072 SIM_dbg_write_trace((SYS_UWORD8 *)"AUANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2073 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2074 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2075 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2076 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2077 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2078 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2079 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2080 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2081 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2082 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2083 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2084 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2085 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2086 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2087 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2088 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2089 * SIM_Envelope |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2090 * |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2091 * Used by Network to transfer data download to the SIM in a transparent way for user |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2092 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2093 SYS_UWORD16 SIM_Envelope(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2094 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2095 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2096 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2097 int res; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2098 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2099 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2100 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2101 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2102 p->xbuf[0] = GSM_CLASS; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2103 p->xbuf[1] = SIM_ENVELOPE; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2104 p->xbuf[2] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2105 p->xbuf[3] = 0; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2106 p->xbuf[4] = (SYS_UWORD8)llen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2107 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2108 for (i=0;i<llen;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2109 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2110 p->xbuf[5+i] = *(dat+i); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2111 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2112 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2113 res = SIM_Command(p, llen, result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2114 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2115 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2116 SIM_dbg_write_trace((SYS_UWORD8 *)"AVCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2117 SIM_dbg_write_trace(p->xbuf, llen+5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2118 SIM_dbg_write_trace((SYS_UWORD8 *)"AVANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2119 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2120 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2121 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2122 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2123 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2124 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2125 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2126 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2127 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2128 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2129 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2130 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2131 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2132 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2133 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2134 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2135 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2136 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2137 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2138 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2139 * SIM_XchTPDU * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2140 * Used for ME to send generic command to WIM Card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2141 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2142 SYS_UWORD16 SIM_XchTPDU(SYS_UWORD8 *dat, SYS_UWORD16 trxLen, SYS_UWORD8 *result, |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2143 SYS_UWORD16 rcvLen, SYS_UWORD16 *rcvSize) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2144 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2145 SIM_PORT *p; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2146 int i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2147 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2148 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2149 p = &(Sim[0]); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2150 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2151 p->xbuf[0] = dat[0]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2152 p->xbuf[1] = dat[1]; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2153 p->xbuf[2] = dat[2]; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2154 p->xbuf[3] = dat[3]; |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2155 p->xbuf[4] = dat[4]; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2156 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2157 for (i=5;i<trxLen;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2158 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2159 p->xbuf[i] = dat[i]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2160 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2161 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2162 // enable the WIM behavior of the sim driver |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2163 p->apdu_ans_length = rcvLen; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2164 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2165 res = SIM_Command(p, (trxLen - 5), result, rcvSize); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2166 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2167 // disable the WIM behavior of the sim driver |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2168 p->apdu_ans_length = 0; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2169 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2170 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2171 SIM_dbg_write_trace((SYS_UWORD8 *)"AWCMD", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2172 SIM_dbg_write_trace(p->xbuf, trxLen); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2173 SIM_dbg_write_trace((SYS_UWORD8 *)"AWANS", 5); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2174 SIM_dbg_tmp[0] = (SYS_UWORD8)(*rcvSize >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2175 SIM_dbg_tmp[1] = (SYS_UWORD8)(*rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2176 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2177 SIM_dbg_write_trace(result, *rcvSize); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2178 SIM_dbg_tmp[0] = (SYS_WORD8)(res>>8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2179 SIM_dbg_tmp[1] = (SYS_WORD8)res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2180 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2181 SIM_dbg_write_trace(SIM_dbg_null, SIM_DBG_NULL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2182 if (SIM_dbg_tdma_diff > SIM_dbg_max_interchardelay) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2183 SIM_dbg_max_interchardelay = SIM_dbg_tdma_diff; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2184 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2185 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2186 SIM_dbg_write_trace(SIM_dbg_tmp, 2); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2187 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2188 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2189 return(res); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2190 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2191 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2192 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2193 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2194 * Use to detect end of characters reception |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2195 * input: p pointer on sim structure |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2196 * n number of extra character to send |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2197 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2198 * output: return 0 if sucess |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2199 * SIM_ERR_x in case of error |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2200 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2201 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2202 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2203 SYS_UWORD16 SIM_WaitReception(SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2204 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2205 SYS_UWORD16 returncode; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2206 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2207 //analyse the nature of the command to execute |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2208 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2209 if ( |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2210 (p->xbuf[1] == 0x12) || |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2211 (p->xbuf[1] == 0xB2) || |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2212 (p->xbuf[1] == 0xB0) || |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2213 (p->xbuf[1] == 0xF2) || |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2214 (p->xbuf[1] == 0xC0) || |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2215 (p->apdu_ans_length != 0) |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2216 ) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2217 //FETCH, READ_RECORD, READ_BINARY, STATUS, GET_RESPONSE commands == receive command |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2218 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2219 if (p->xbuf[4] == 0) //if P3 == 0 when sending receive command |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2220 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2221 p->expected_data = 256; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2222 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2223 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2224 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2225 p->expected_data = p->xbuf[4]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2226 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2227 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2228 p->moderx = 1; //wait for procedure byte |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2229 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2230 if (returncode = SIM_Waitforchars (p, p->etu9600)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2231 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2232 return returncode; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2233 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2234 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2235 else //direct command : INVALIDATE, REHABILITATE, SLEEP |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2236 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2237 p->moderx = 5; //mode reception of SW1/SW2 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2238 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2239 if (returncode = SIM_Waitforchars (p, p->etu9600)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2240 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2241 return returncode; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2242 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2243 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2244 return (0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2245 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2246 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2247 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2248 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2249 * Use to read file characteristics information |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2250 * input: p pointer on sim structure |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2251 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2252 * output: return 0 if sucess |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2253 * 1 in case of error |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2254 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2255 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2256 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2257 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2258 SYS_UWORD8 SIM_GetFileCharacteristics(SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2259 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2260 int res; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2261 SYS_UWORD8 ubuf[40]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2262 SYS_UWORD16 sz; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2263 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2264 res = SIM_Select(DF_GSM, ubuf, &sz); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2265 if ((res & 0xFF00) != 0x9F00) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2266 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2267 res = SIM_Select(DF_DCS1800, ubuf, &sz); |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2268 if ((res & 0xFF00) != 0x9F00) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2269 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2270 return (1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2271 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2272 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2273 res = SIM_GetResponse( ubuf, res & 0x00FF , &sz); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2274 if (res != 0x9000) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2275 return (1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2276 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2277 p->FileC = ubuf[13]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2278 return (0); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2279 } |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2280 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2281 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2282 * Use to determine value of b2 in file caracteristics contained in response |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2283 * of SELECT Master File command |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2284 * return 0 if no preferred speed during authentication |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2285 * 1 if 13/4Mhz mandatory |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2286 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2287 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2288 */ |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2289 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2290 void SIM_Interpret_FileCharacteristics(SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2291 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2292 //interpret b2 bit for operating authentication speed |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2293 if((p->conf1 & 0x0020) && (p->FileC & 0x02)) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2294 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2295 p->Freq_Algo = 1; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2296 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2297 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2298 //interpret Clock stop behavior |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2299 // modified by J. Yp-Tcha to integrate all the behaviors required by ETSI. |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2300 // 18/11/2002 : TI Chip always allowed low level, high level is hard dependant |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2301 |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2302 if ((p->FileC & SIM_CLK_STOP_MASK) == SIM_CLK_STOP_NOT_ALLWD) { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2303 /* Sim Clock Stop Not Allowed */ |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2304 SIM_sleep_status = SIM_SLEEP_NOT_ALLOWED; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2305 /* There is not need to modifiy p->conf1 */ |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2306 status_os_sim = NU_Delete_Timer (&SIM_timer); |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2307 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2308 else { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2309 if ((p->FileC & SIM_CLK_STOP_MASK) == SIM_CLK_STOP_ALLWD) { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2310 /* Sim Clock Stop Allowed, no prefered level */ |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2311 /* Default value for TI Chip shall always be Low Level */ |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2312 SIM_sleep_status = SIM_SLEEP_DESACT; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2313 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SCLKLEV; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2314 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2315 else { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2316 /* Clock Stop is allowed, the level shall be checked */ |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2317 if ((p->FileC & SIM_CLK_STOP_HIGH) == SIM_CLK_STOP_HIGH) { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2318 /* high level is mandatory */ |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2319 /* OMEGA/NAUSICA can not handle sim stop clock at high level */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2320 #ifndef ANALOG1 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2321 SIM_sleep_status = SIM_SLEEP_DESACT; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2322 p->c->conf1 = p->conf1 |= SIM_CONF1_SCLKLEV; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2323 #else |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2324 /* Sim Clock Stop Not Allowed because the interface do not support this level */ |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2325 SIM_sleep_status = SIM_SLEEP_NOT_ALLOWED; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2326 /* There is not need to modifiy p->conf1 */ |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2327 status_os_sim = NU_Delete_Timer (&SIM_timer); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2328 #endif |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2329 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2330 else { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2331 /* by default, Low Level is allowed */ |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2332 SIM_sleep_status = SIM_SLEEP_DESACT; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2333 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SCLKLEV; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2334 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2335 } |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2336 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2337 if (SIM_sleep_status == SIM_SLEEP_NONE) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2338 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2339 status_os_sim = NU_Delete_Timer (&SIM_timer); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2340 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2341 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2342 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2343 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2344 * Use to evaluate need of sending PTS procedure regarding |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2345 * the ATR. If default not used, PTS initiates F and D adequate values |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2346 * for speed enhancement. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2347 * In case of 2 wrong PTS answer (speed enhanced), a third PTS with default value |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2348 * is used. If the third PTS attempt failed, the ME reset the SIM and use default |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2349 * value. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2350 * Return Value : SIM_ERR_READ, SIM_ERRCARDREJECT, SIM_ERR_WAIT |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2351 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2352 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2353 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2354 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2355 SYS_UWORD16 SIM_PTSprocedure(SIM_CARD *cP, SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2356 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2357 SYS_UWORD8 TA1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2358 SYS_UWORD8 n; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2359 SYS_UWORD8 err; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2360 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2361 p->xbuf[0] = 0xFF; //character of PTS proc to send |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2362 p->xbuf[1] = 0; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2363 p->xbuf[2] = 0xFF; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2364 p->xbuf[3] = 0x7B; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2365 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2366 //TA1,TB1,TC1,TD1 present in ATR ? |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2367 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2368 n = 3; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2369 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2370 p->PTS_Try++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2371 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2372 if (p->PTS_Try > 4) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2373 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2374 return (SIM_ERR_CARDREJECT); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2375 } // at the fourth attempt, PTS procedure is unusefull. Use default value. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2376 //TA1 present? Test 27.11.2.6 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2377 else if (p->PTS_Try == 4) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2378 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2379 SIM_Calcetu (p); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2380 return (0); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2381 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2382 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2383 if (cP->AtrData[1] & 0x10) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2384 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2385 TA1 = cP->AtrData[2]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2386 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2387 else //if TA1 not present, return |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2388 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2389 SIM_Calcetu (p); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2390 return (0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2391 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2392 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2393 if (TA1 >= 0x94 && SIM_allow_speed_enhancement) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2394 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2395 // JYT 26/9/2003 to check correct behavior of the SIM Driver vs the PPS. |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2396 //#ifdef NOTTOLOADBECAUSENOTTESTED |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2397 // SIM_Calcetu (p); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2398 // return (0); //temporary disabling of speed enhancement feature |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2399 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2400 if (p->PTS_Try <= 2) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2401 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2402 n = 4; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2403 p->xbuf[1] = 0x10; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2404 p->xbuf[2] = 0x94; // if speed enhancement, then at least (and at most) F = 512 and D = 8 is supported |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2405 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2406 //#endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2407 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2408 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2409 if ((TA1 == 0x11) || (TA1 == 0x01)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2410 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2411 SIM_Calcetu (p); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2412 return (0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2413 } //if TA1 != 0x11 and 0x94, need to send PTS request |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2414 //transmit request of speed enhancement : PTS |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2415 SIM_WriteBuffer(p, 0, n); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2416 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2417 p->moderx = 0; //mode of normal reception |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2418 p->expected_data = n; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2419 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2420 if (err = SIM_Waitforchars (p, p->etu9600)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2421 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2422 return (err); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2423 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2424 //should received same chars as PTS request |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2425 if ((p->rbuf[0] != p->xbuf[0]) || (p->rbuf[1] != p->xbuf[1]) || |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2426 (p->rbuf[2] != p->xbuf[2])) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2427 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2428 return(SIM_ERR_READ); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2429 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2430 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2431 if (n == 4) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2432 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2433 if (p->rbuf[3] != p->xbuf[3]) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2434 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2435 return(SIM_ERR_READ); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2436 } |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2437 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2438 //correct response from SIM : with speed enhanced |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2439 p->c->conf1 = p->conf1 |= SIM_CONF1_ETU; //set F=512 D=8 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2440 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2441 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2442 SIM_Calcetu (p); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2443 return (0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2444 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2445 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2446 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2447 * procedure of WARM reset consists on asserting |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2448 * reset signal at 0 during at least 400 ETU |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2449 * input p pointer of type SIM_PORT |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2450 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2451 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2452 void SIM_WARMReset (SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2453 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2454 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SRSTLEV; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2455 ind_os_sleep (p->etu400); /// wait 400 ETU |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2456 p->c->conf1 = p->conf1 |= SIM_CONF1_SRSTLEV; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2457 p->rx_index = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2458 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2459 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2460 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2461 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2462 * procedure use to get out sleepMode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2463 * input p pointer of type SIM_PORT |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2464 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2465 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2466 void SIM_SleepMode_In (SYS_UWORD32 param) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2467 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2468 if (SIM_sleep_status == SIM_SLEEP_DESACT) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2469 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2470 (&(Sim[0]))->c->conf1 &= ~SIM_CONF1_SCLKEN; //disabled the clock for the SIM card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2471 SIM_sleep_status = SIM_SLEEP_ACT; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2472 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2473 status_os_sim = NU_Control_Timer (&SIM_timer, NU_DISABLE_TIMER); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2474 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2475 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2476 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2477 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2478 * procedure use to get out sleepMode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2479 * input p pointer of type SIM_PORT |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2480 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2481 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2482 void SIM_SleepMode_Out (SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2483 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2484 if (SIM_sleep_status == SIM_SLEEP_ACT) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2485 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2486 p->c->conf1 = p->conf1 |= SIM_CONF1_SCLKEN; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2487 // WCS patch for NU_Sleep(0) bug |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2488 if (p->startclock > 0) |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2489 ind_os_sleep (p->startclock); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2490 // End WCS patch |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2491 SIM_sleep_status = SIM_SLEEP_DESACT; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2492 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2493 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2494 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2495 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2496 * procedure to parse ATR dynamically |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2497 * input p pointer of type SIM_PORT |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2498 * output return error code |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2499 * SIM_ERR_WAIT, p->errorSIM |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2500 * SIM_ERR_CARDREJECT, |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2501 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2502 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2503 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2504 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2505 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2506 SYS_UWORD16 SIM_ATRdynamictreatement (SIM_PORT *p, SIM_CARD *cP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2507 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2508 volatile SYS_UWORD8 HistChar; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2509 volatile SYS_UWORD8 InterfChar; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2510 SYS_UWORD16 countT; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2511 SYS_UWORD16 mask; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2512 SYS_UWORD16 returncode; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2513 SYS_UWORD8 i; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2514 SYS_UWORD8 firstprotocol; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2515 SYS_UWORD8 Tx,T; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2516 SYS_UWORD8 TDi; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2517 SYS_UWORD8 position_of_TC1, position_of_TB1; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2518 SYS_UWORD8 another_protocol_present; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2519 SYS_UWORD16 wait80000clk; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2520 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2521 i = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2522 //wait for TS and T0 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2523 p->moderx = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2524 p->expected_data= 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2525 firstprotocol = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2526 position_of_TC1 = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2527 position_of_TB1 = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2528 another_protocol_present = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2529 wait80000clk = 6; // > 24 ms |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2530 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2531 //wait for first character TS of ATR sequence. It should arrive before 80000sclk |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2532 if (returncode = SIM_Waitforchars (p, wait80000clk)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2533 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2534 return returncode; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2535 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2536 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2537 //wait for T0 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2538 p->expected_data++; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2539 if (returncode = SIM_Waitforchars (p, p->etu9600)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2540 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2541 return returncode; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2542 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2543 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2544 ind_os_sleep(220); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2545 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2546 if (((p->rbuf[0] & 0xF0) == 0x30) && (p->rx_index != 0)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2547 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2548 cP->Inverse = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2549 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2550 /*-----------------------------------------------------------*/ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2551 /* Inverse convention card */ |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2552 // If first byte is correct for inverse card, return success |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2553 else if (((p->rbuf[0] & 0x0F) == 0x03) && (p->rx_index != 0)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2554 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2555 cP->Inverse = 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2556 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2557 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2558 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2559 return (SIM_ERR_CARDREJECT); //Test 27.11.2.4.5 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2560 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2561 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2562 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2563 mask = 0x10; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2564 InterfChar = 2; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2565 TDi = 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2566 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2567 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2568 Tx = SIM_Translate_atr_char (p->rbuf[1], cP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2569 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2570 HistChar = Tx & 0x0F; //get K, number of transmitted historical character |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2571 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2572 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2573 while (TDi != 0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2574 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2575 while (mask < 0x100) //monitors interface chars |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2576 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2577 if ((Tx & mask) == mask) //monitors if interface character TAx,TBx,TCx,TDc present |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2578 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2579 InterfChar++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2580 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2581 //wait for TC1 and save its position |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2582 if ((firstprotocol == 0) && ((Tx & 0x40) == mask)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2583 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2584 position_of_TC1 = InterfChar - 1; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2585 } |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2586 if ((firstprotocol == 0) && ((Tx & 0x20) == mask)) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2587 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2588 position_of_TB1 = InterfChar - 1; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2589 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2590 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2591 mask = mask << 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2592 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2593 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2594 p->expected_data = InterfChar; //wait for TAi,TBi,TCi,TDi if present |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2595 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2596 if (returncode = SIM_Waitforchars (p, p->etu9600)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2597 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2598 return returncode; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2599 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2600 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2601 //need to monitor if TC1 present and if equal to 0 or 255 on first protocol |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2602 if ((firstprotocol == 0) && (position_of_TC1 != 0)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2603 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2604 T = SIM_Translate_atr_char (p->rbuf[position_of_TC1], cP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2605 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2606 if ((T != 0) && (T != 255)) //test 27.11.1.3 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2607 { //return Error in case of bad TC1 value |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2608 return (SIM_ERR_CARDREJECT); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2609 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2610 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2611 //need to monitor if TB1 present and if differente from 0 on first protocol |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2612 if ((firstprotocol == 0) && (position_of_TB1 != 0)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2613 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2614 T = SIM_Translate_atr_char (p->rbuf[position_of_TB1], cP); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2615 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2616 if (T != 0) //ITU |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2617 { //return Error in case of bad TB1 value |
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2618 return (SIM_ERR_CARDREJECT); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2619 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2620 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2621 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2622 if ((Tx & 0x80) == 0x80) //TDi byte on first protocol must be 0 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2623 { //get new TD char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2624 Tx = SIM_Translate_atr_char (p->rbuf[InterfChar - 1], cP); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2625 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2626 if ((Tx & 0x0F) != 0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2627 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2628 if (firstprotocol == 0) //if first protocol received is not T=0, card is rejected |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2629 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2630 return (SIM_ERR_CARDREJECT); //protocol other than T=0 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2631 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2632 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2633 { //if an another protocol T != 0 present, need to wait for TCK char |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2634 another_protocol_present = 1; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2635 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2636 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2637 mask = 0x10; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2638 firstprotocol++; //indicate another protocol T |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2639 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2640 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2641 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2642 TDi = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2643 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2644 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2645 //add TCK if necessary |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2646 p->expected_data = HistChar + InterfChar + another_protocol_present; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2647 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2648 if (returncode = SIM_Waitforchars (p, p->etu9600)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2649 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2650 return returncode; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2651 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2652 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2653 cP->AtrSize = p->rx_index; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2654 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2655 if (cP->Inverse) //inverse card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2656 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2657 // Copy ATR data |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2658 for (i=0;i<cP->AtrSize;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2659 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2660 cP->AtrData[i] = SIM_ByteReverse(p->rbuf[i]); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2661 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2662 p->c->conf1 = p->conf1 |= SIM_CONF1_CONV | SIM_CONF1_CHKPAR; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2663 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2664 else //direct card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2665 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2666 p->c->conf1 = p->conf1 |= SIM_CONF1_CHKPAR; //0x0409 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2667 // Copy ATR data |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2668 for (i=0;i<cP->AtrSize;i++) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2669 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2670 cP->AtrData[i] = p->rbuf[i]; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2671 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2672 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2673 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2674 return (0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2675 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2676 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2677 /* |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2678 ** SIM_Translate_atr_char |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2679 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2680 * FILENAME: sim.c |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2681 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2682 * PARAMETERS: input char to translate |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2683 * cP sim structure (indicates if inverse card present) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2684 * DESCRIPTION: return the correct value of input for inverse card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2685 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2686 * RETURNS: character after parsing |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2687 * stays the same if direct card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2688 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2689 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2690 SYS_UWORD8 SIM_Translate_atr_char (SYS_UWORD8 input, SIM_CARD *cP) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2691 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2692 SYS_UWORD8 translated; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2693 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2694 if (cP->Inverse) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2695 { |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2696 translated = SIM_ByteReverse(input); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2697 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2698 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2699 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2700 translated = input; //get character next char T0 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2701 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2702 return (translated); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2703 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2704 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2705 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2706 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2707 * SIM_Waitforchars is used for waiting nbchar characters from SIM |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2708 * input p sim port |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2709 * max_wait max number of TDMA to wait between 2 characters |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2710 * output |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2711 * error code 0 if OK |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2712 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2713 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2714 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2715 SYS_UWORD16 SIM_Waitforchars (SIM_PORT *p, SYS_UWORD16 max_wait) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2716 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2717 volatile SYS_UWORD8 old_nb_char; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2718 volatile SYS_UWORD16 countT; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2719 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2720 if (p->moderx == 6) //use for reception of ACK when command need to transmit rest of data |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2721 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2722 p->ack = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2723 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2724 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2725 while((p->ack == 0) && (p->moderx == 6)) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2726 { //if p->moderx change from 6 to 5, need to wait for SW1 and SW2 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2727 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2728 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2729 countT++; //implementation of software Waiting time overflow |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2730 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2731 if (p->null_received) //if NULL char received, wait for next procedure char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2732 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2733 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2734 p->null_received = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2735 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2736 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2737 if (countT > max_wait) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2738 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2739 return (SIM_ERR_WAIT); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2740 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2741 if (p->errorSIM) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2742 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2743 return(p->errorSIM); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2744 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2745 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2746 if (p->moderx == 6) //if transition to moderx = 5 in synchronous part |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2747 { //need to quit for SW1/SW2 reception |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2748 return (0); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2749 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2750 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2751 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2752 if ((p->moderx != 6) && (p->moderx != 5)) //treatement of mode 0, 1, 2, 3, 4 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2753 { |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2754 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2755 old_nb_char = p->rx_index; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2756 //leave while if moderx == 5 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2757 while((p->rx_index < p->expected_data) && (p->moderx != 5)) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2758 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2759 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2760 countT++; //implementation of software Waiting time overflow |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2761 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2762 if (p->null_received) //if NULL char received, wait for next procedure char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2763 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2764 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2765 p->null_received = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2766 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2767 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2768 if (countT > max_wait) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2769 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2770 return (SIM_ERR_WAIT); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2771 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2772 if (p->errorSIM) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2773 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2774 return(p->errorSIM); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2775 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2776 if (p->rx_index > old_nb_char) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2777 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2778 old_nb_char = p->rx_index; //if char received before max_wait TDMA, reset the counter |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2779 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2780 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2781 } //end while |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2782 if (p->moderx == 0) |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2783 { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2784 return (0); |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2785 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2786 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2787 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2788 if (p->moderx == 5) //use for reception of SW1 SW2 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2789 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2790 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2791 old_nb_char = p->SWcount; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2792 |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2793 while (p->SWcount < 2) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2794 { //if p->moderx change from 6 to 5, need to wait for SW1 and SW2 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2795 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2796 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2797 countT++; //implementation of software Waiting time overflow |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2798 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2799 if (p->null_received) //if NULL char received, wait for next procedure char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2800 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2801 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2802 p->null_received = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2803 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2804 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2805 if (countT > max_wait) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2806 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2807 return (SIM_ERR_WAIT); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2808 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2809 if (p->errorSIM) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2810 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2811 return(p->errorSIM); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2812 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2813 if (p->SWcount > old_nb_char) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2814 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2815 old_nb_char = p->SWcount; //if char received before max_wait TDMA, reset the counter |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2816 countT = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2817 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2818 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2819 p->SWcount = 0; //reset SWcount buffer index when SW1 SW2 received |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2820 return (0); |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2821 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2822 else //treatement of abnormal case of the asynchronous state machine |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2823 { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2824 return (SIM_ERR_ABNORMAL_CASE1); |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2825 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2826 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2827 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2828 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2829 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2830 * SIM_Calcetu is used for calculating 9600 etu and 400 etu depending on sim clock freq |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2831 * and etu period |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2832 * input p sim port |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2833 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2834 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2835 void SIM_Calcetu (SIM_PORT *p) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2836 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2837 if (p->conf1 & SIM_CONF1_SCLKDIV) //clock input is 13/8 Mhz |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2838 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2839 if (p->conf1 & SIM_CONF1_ETU) //etu period is 512/8*Tsclk |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2840 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2841 p->etu9600 = 319; // old = 88, increase of 363% |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2842 p->etu400 = 6; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2843 p->stopclock = 18; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2844 p->startclock = 8; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2845 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2846 else //etu period is 372/1*Tsclk |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2847 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2848 p->etu9600 = 1815; // old = 500, increase of 363% |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2849 p->etu400 = 28; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2850 p->stopclock = 94; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2851 p->startclock = 38; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2852 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2853 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2854 else //clock input is 13/4 Mhz |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2855 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2856 if (p->conf1 & SIM_CONF1_ETU) //etu period is 512/8*Tsclk |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2857 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2858 p->etu9600 = 159; // old = 44, increase of 363% |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2859 p->etu400 = 3; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2860 p->stopclock = 9; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2861 p->startclock = 4; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2862 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2863 else //etu period is 372/1*Tsclk |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2864 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2865 p->etu9600 = 907; // old = 250, increase of 363% |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2866 p->etu400 = 14; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2867 p->stopclock = 47; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2868 p->startclock = 19; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2869 } |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2870 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2871 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2872 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2873 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2874 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2875 * Set the level shifter voltage for start up sequence |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2876 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2877 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2878 |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2879 SYS_UWORD8 SIM_StartVolt (SYS_UWORD8 ResetFlag) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2880 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2881 SYS_UWORD8 abbmask; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2882 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2883 #if(ANLG_FAM == 1) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2884 // we assume that in SIM_TYPE_5V there is nothing to do because it is the reset value |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2885 #if ((SIM_TYPE == SIM_TYPE_3V) || (SIM_TYPE == SIM_TYPE_3_5V)) // { shut down VCC from ABB and prepare to start at 3V mode |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2886 if (ResetFlag) { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2887 abbmask = MODE_INIT_OMEGA_3V; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2888 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning. |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2889 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2890 else { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2891 if (CurrentVolt == SIM_3V) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2892 abbmask = MODE_INIT_OMEGA_3V; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2893 else |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2894 abbmask = MODE5V_OMEGA; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2895 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2896 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) & 0xC0) | abbmask); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2897 ind_os_sleep(1); //wait for charge pump regulation |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2898 return(SIM_OK); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2899 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2900 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2901 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2902 #if(ANLG_FAM == 2) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2903 SYS_UWORD8 count = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2904 // code for Iota |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2905 // reset value for IOTA is for 1.8V, but specific procedure is needed |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2906 #if ((SIM_TYPE == SIM_TYPE_1_8V) || (SIM_TYPE == SIM_TYPE_1_8_3V)) // shut down VCC from ABB and prepare to start at 1.8V mode |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2907 if (ResetFlag) { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2908 abbmask = MODE_INIT_IOTA_1_8V; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2909 CurrentVolt = SIM_1_8V; // we assume the sim is 1.8v tech. from beginning. |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2910 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2911 else { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2912 if (CurrentVolt == SIM_1_8V) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2913 abbmask = MODE_INIT_IOTA_1_8V; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2914 else |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2915 abbmask = MODE_INIT_IOTA_3V; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2916 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2917 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2918 while(count++ < 5) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2919 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2920 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04) // test RSIMRSU |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2921 return(SIM_OK); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2922 ind_os_sleep(1); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2923 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2924 // IOTA failure activation |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2925 return(SIM_ERR_HARDWARE_FAIL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2926 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2927 // 3V only |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2928 #if (SIM_TYPE == SIM_TYPE_3V) |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2929 abbmask = MODE_INIT_IOTA_3V; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2930 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning. |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2931 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2932 while(count++ < 5) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2933 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2934 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04) // test RSIMRSU |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2935 return(SIM_OK); |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2936 ind_os_sleep(1); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2937 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2938 // IOTA failure activation |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2939 return(SIM_ERR_HARDWARE_FAIL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2940 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2941 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2942 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2943 #if(ANLG_FAM == 3) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2944 SYS_UWORD8 count = 0; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2945 // code for Syren |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2946 // reset value for SYREN is for 1.8V, but specific procedure is needed |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2947 #if ((SIM_TYPE == SIM_TYPE_1_8V) || (SIM_TYPE == SIM_TYPE_1_8_3V)) // { shut down VCC from ABB and prepare to start at 1.8V mode |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2948 if (ResetFlag) { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2949 abbmask = MODE_INIT_SYREN_1_8V; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2950 CurrentVolt = SIM_1_8V; // we assume the sim is 1.8v tech. from beginning. |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2951 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2952 else { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2953 if (CurrentVolt == SIM_1_8V) |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2954 abbmask = MODE_INIT_SYREN_1_8V; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2955 else |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2956 abbmask = MODE_INIT_SYREN_3V; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2957 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2958 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x1F4) | abbmask); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2959 while(count++ < 5) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2960 { |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2961 if (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x04) // test RSIMRSU |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2962 return(SIM_OK); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2963 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2964 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2965 // SYREN failure activation |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2966 return(SIM_ERR_HARDWARE_FAIL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2967 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2968 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2969 // 3V only |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2970 #if (SIM_TYPE == SIM_TYPE_3V) |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2971 abbmask = MODE_INIT_SYREN_3V; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2972 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning. |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2973 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x1F4) | abbmask); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2974 while(count++ < 5) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2975 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2976 if (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x04) // test RSIMRSU |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2977 return(SIM_OK); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2978 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2979 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2980 // SYREN failure activation |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2981 return(SIM_ERR_HARDWARE_FAIL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2982 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2983 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2984 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2985 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2986 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2987 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2988 * Set the level shifter to switch from 3V to 5V |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2989 * |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2990 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2991 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2992 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2993 SYS_UWORD8 SIM_SwitchVolt (SYS_UWORD8 ResetFlag) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2994 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2995 SYS_UWORD8 count = 0; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
2996 SYS_UWORD8 abbmask; |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
2997 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2998 SIM_PowerOff(); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2999 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3000 #if(ANLG_FAM == 1) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3001 #if (SIM_TYPE == SIM_TYPE_3_5V) // shut down VCC from ABB and prepare to start at 5V mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3002 if (ResetFlag) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3003 abbmask = MODE5V_OMEGA; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3004 CurrentVolt = SIM_5V; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3005 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3006 else { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3007 if (CurrentVolt == SIM_3V) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3008 abbmask = MODE_INIT_OMEGA_3V; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3009 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3010 abbmask = MODE5V_OMEGA; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3011 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3012 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) & 0xC0) | abbmask); |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3013 return(SIM_OK); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3014 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3015 #elif(ANLG_FAM == 2) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3016 #if (SIM_TYPE == SIM_TYPE_1_8_3V) // shut down VCC from ABB and prepare to start at 3V mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3017 if (ResetFlag) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3018 abbmask = MODE_INIT_IOTA_3V; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3019 CurrentVolt = SIM_3V; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3020 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3021 else { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3022 if (CurrentVolt == SIM_1_8V) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3023 abbmask = MODE_INIT_IOTA_1_8V; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3024 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3025 abbmask = MODE_INIT_IOTA_3V; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3026 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3027 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask); |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3028 while(count++ < 5) |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3029 { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3030 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04) |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3031 return(SIM_OK); |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3032 ind_os_sleep(1); |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3033 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3034 // IOTA failure activation |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3035 return(SIM_ERR_HARDWARE_FAIL); |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3036 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3037 #elif(ANLG_FAM == 3) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3038 #if (SIM_TYPE == SIM_TYPE_1_8_3V) // shut down VCC from ABB and prepare to start at 3V mode |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3039 if (ResetFlag) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3040 abbmask = MODE_INIT_SYREN_3V; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3041 CurrentVolt = SIM_3V; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3042 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3043 else { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3044 if (CurrentVolt == SIM_1_8V) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3045 abbmask = MODE_INIT_SYREN_1_8V; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3046 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3047 abbmask = MODE_INIT_SYREN_3V; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3048 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3049 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x1F4) | abbmask); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3050 while(count++ < 5) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3051 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3052 if (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x04) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3053 return(SIM_OK); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3054 ind_os_sleep(1); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3055 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3056 // SYREN failure activation |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3057 return(SIM_ERR_HARDWARE_FAIL); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3058 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3059 #endif // ANLG_FAM == 1, 2, 3 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3060 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3061 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3062 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3063 SYS_UWORD8 SIM_Memcpy(SYS_UWORD8 *Buff_target, SYS_UWORD8 Buff_source[], SYS_UWORD16 len) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3064 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3065 SYS_UWORD16 i; //unsigned short type counter chosen for copy of 256 bytes |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3066 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3067 for (i = 0; i < len; i++) |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3068 { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3069 if (i == RSIMBUFSIZE) |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3070 { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3071 return (SIM_ERR_BUFF_OVERFL); |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3072 } |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3073 else |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3074 { |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3075 (*(Buff_target+i)) = Buff_source[i]; |
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3076 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3077 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3078 return (0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3079 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3080 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3081 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3082 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3083 * SIM_SleepStatus |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
3084 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3085 * Return SIM status for sleep manager |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
3086 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3087 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3088 SYS_BOOL SIM_SleepStatus(void) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3089 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3090 if ((SIM_sleep_status == SIM_SLEEP_ACT) || (SIM_sleep_status == SIM_SLEEP_NONE)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3091 return(1); // SIM is ready for deep sleep |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
3092 else |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3093 return(0); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3094 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3095 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3096 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3097 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3098 * Special lock function to force SIM entity to use adequat SIM Driver |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3099 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3100 void SIM_lock_cr17689(void) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3101 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3102 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3103 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3104 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3105 void SIM_dbg_write_trace(SYS_UWORD8 *ptr, SYS_UWORD16 len) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3106 SYS_UWORD16 i; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3107 for(i=0;i<len;i++) { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3108 if (SIM_dbg_cmd_cmpt == SIM_DBG_CMD) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3109 SIM_dbg_cmd_cmpt = 0; |
191
c1205c437943
../drv_app/sim/sim.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
3110 SIM_dbg_cmd[SIM_dbg_cmd_cmpt++] = ptr[i]; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3111 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3112 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3113 #endif |