FreeCalypso > hg > fc-tourmaline

annotate src/cs/layer1/cfile/l1_small_asm.S @ 268:f2e52cab0a73

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abb_inth.c: check all interrupt causes, not just one The original code used if - else if - else if etc constructs, thus the first detected interrupt was the only one handled. However, Iota ITSTATREG is a clear-on-read register, thus if we only handle the first detected interrupt and skip checking the others, then the other interrupts will be lost, if more than one interrupt happened to occur in one ABB interrupt handling cycle - a form of rare race condition. Change the code to check all interrupts that were read in this cycle.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 13 Jun 2021 18:17:53 +0000
parents 4e78acac3d88
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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1 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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2 * Assembly code extracted out of TI's l1_small.c
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3 *
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4 * This code is correct ONLY for CHIPSET 10 or 11 as currently used
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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5 * by FreeCalypso; see TI's original code for what changes would be
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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6 * needed to support other CHIPSETs.
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7 */
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8
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9 .text
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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10 .code 32
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11
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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12 /*-------------------------------------------------------*/
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13 /* _GSM_Small_Sleep */
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14 /* (formerly INT_Small_Sleep) */
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15 /*-------------------------------------------------------*/
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16 /* */
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17 /* Description: small sleep */
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18 /* ------------ */
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19 /* Called by TCT_Schedule main loop of Nucleus */
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20 /*-------------------------------------------------------*/
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21
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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22 #define SMALL_SLEEP 0x01
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23 #define ALL_SLEEP 0x04
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24 #define BIG_SMALL_SLEEP 0x05
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25 #define PWR_MNGT 0x01
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26
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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27 .globl _GSM_Small_Sleep
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28 _GSM_Small_Sleep:
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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30 ldr r0,Switch
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31 ldr r0,[r0]
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32 ldrb r1,[r0]
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33 cmp r1,#PWR_MNGT
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34 bne TCT_Schedule_Loop
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35
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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36 ldr r0,Mode
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37 ldr r0,[r0]
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38 ldrb r1,[r0]
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39 cmp r1,#SMALL_SLEEP
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40 beq Small_sleep_ok
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41 cmp r1,#ALL_SLEEP
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42 beq Small_sleep_ok
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43 cmp r1,#BIG_SMALL_SLEEP
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44 bne TCT_Schedule_Loop
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45
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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46 Small_sleep_ok:
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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48 // *****************************************************
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49 //reset the DEEP_SLEEP bit 12 of CNTL_ARM_CLK register
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50 // (Cf BUG_1278)
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51
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52 ldr r0,addrCLKM @ pick up CNTL_ARM_CLK register address
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53 ldrh r1,[r0] @ take the current value of the register
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54 orr r1,r1,#0x1000 @ reset the bit
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55 strh r1,[r0] @ store the result
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56
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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57 ldr r0,addrCLKM @ pick up CLKM clock register address
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58 ldrh r1,[r0] @ take the current value of the register
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59 bic r1,r1,#1 @ disable ARM clock
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60 strh r1,[r0]
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61
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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62 B TCT_Schedule_Loop @ Return to TCT_Schedule main loop
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63
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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64 addrCLKM: .word 0xfffffd00 @ CLKM clock register address
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65
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66 Mode: .word mode_authorized
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67 Switch: .word switch_PWR_MNGT