FreeCalypso > hg > fc-tourmaline

annotate src/cs/drivers/drv_app/fchg/fchg_struct.h @ 304:58c7961bd0b0 default tip

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TCH tap: extend DL sniffing feature to support CSD modes Our debug feature for TCH DL sniffing reads the content of the DSP's a_dd_0 buffer (or a_dd_1 for TCH/H subchannel 1) at appropriate times and forwards captured bits to the host. This feature was originally implemented for TCH/FS, TCH/EFS and TCH/HS - now extend it to cover TCH/F data modes too.
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 25 Nov 2024 23:33:27 +0000
parents 769cf6273fe4
children
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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1 /*
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2 * Internal structure definitions for the FCHG SWE reside here.
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3 * abb_inth.c will also need to include this header in order to
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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4 * get our T_PWR_CTRL_BLOCK definition.
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5 */
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6
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7 #ifndef __FCHG_STRUCT_H
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8 #define __FCHG_STRUCT_H
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9
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10 #include "rv/rv_general.h"
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11 #include "rvf/rvf_api.h"
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12 #include "fchg/fchg_common.h"
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13
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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14 struct charging_config {
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15 UINT16 start_delay;
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16 UINT16 start_thresh;
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17 UINT16 restart_thresh;
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18 UINT16 ci2cv_thresh;
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19 UINT16 cv_init_set;
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20 UINT16 cv_ctrl_loop_high;
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21 UINT16 cv_ctrl_loop_low;
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22 UINT16 cv_dac_max_incr;
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23 UINT16 cv_dac_max_decr;
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24 UINT16 cv_samples_needed;
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25 UINT16 overvoltage;
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26 UINT16 ci_current;
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27 UINT16 end_current;
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28 UINT16 ichg_max_spike;
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29 UINT16 ichg_samples_needed;
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30 UINT16 charge_time_limit;
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31 UINT16 recharge_delay;
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32 UINT16 bciconf;
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33 };
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34
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35 /* from original PWR SWE */
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36 typedef struct {
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37 UINT16 bat_voltage;
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38 T_PWR_PERCENT remain_capa;
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39 } T_PWR_THRESHOLDS;
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40
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41 #define MIN_PERCENT_THRESH 5
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42 #define MAX_PERCENT_THRESH 21 /* allowing 5% steps */
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43 #define NB_BARS_THRESH 4
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44
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45 struct battery_config {
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46 UINT8 bars_thresh[NB_BARS_THRESH];
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47 T_PWR_THRESHOLDS percent_thresh[MAX_PERCENT_THRESH];
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48 };
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49
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50 struct bsim_config {
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51 UINT8 init_percent;
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52 UINT8 start_enable;
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53 UINT8 pad[2];
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54 };
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55
0
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56 #define ICHG_AVG_WINDOW 6
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57
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58 typedef struct {
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59 /* RiViera boilerplate */
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60 T_RVF_ADDR_ID addr_id;
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61 T_RVF_MB_ID prim_id;
61
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62 /* interface to upper layers */
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63 T_FCHG_EVENT_HANDLER event_handler;
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64 /* configuration */
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65 struct charging_config config;
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66 BOOL config_present;
61
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67 struct battery_config batt;
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68 UINT16 nb_percent_thresh;
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69 struct bsim_config bsim;
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70 BOOL bsim_mode;
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71 /* state */
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72 enum fchg_state state;
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73 UINT16 batt_mv;
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74 UINT16 curr_disch_thresh;
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75 /* valid only during a charging cycle */
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76 UINT16 i2v_offset;
61
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77 UINT16 ci_ichg;
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78 UINT16 cv_dac_init;
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79 UINT16 cv_dac_curr;
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80 UINT16 cv_high_vbat_count;
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81 UINT16 cv_low_vbat_count;
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82 UINT16 ichg_avg_buf[ICHG_AVG_WINDOW];
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83 UINT16 ichg_fill_level;
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84 UINT16 ichg_ring_ptr;
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85 UINT16 ichg_average;
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86 UINT16 ichg_low_count;
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87 UINT32 start_time;
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88 } T_PWR_CTRL_BLOCK;
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89
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90 #endif /* include guard */