FreeCalypso > hg > fc-tourmaline

annotate src/cs/drivers/drv_app/sim/sim.h @ 303:f76436d19a7a default tip

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!GPRS config: fix long-standing AT+COPS chance hanging bug There has been a long-standing bug in FreeCalypso going back years: sometimes in the AT command bring-up sequence of an ACI-only MS, the AT+COPS command would produce only a power scan followed by cessation of protocol stack activity (only L1 ADC traces), instead of the expected network search sequence. This behaviour was seen in different FC firmware versions going back to Citrine, and seemed to follow some law of chance, not reliably repeatable. This bug has been tracked down and found to be specific to !GPRS configuration, stemming from our TCS2/TCS3 hybrid and reconstruction of !GPRS support that was bitrotten in TCS3.2/LoCosto version. ACI module psa_mms.c, needed only for !GPRS, was missing in the TCS3 version and had to be pulled from TCS2 - but as it turns out, there is a new field in the MMR_REG_REQ primitive that needs to be set correctly, and that psa_mms.c module is the place where this initialization needed to be added.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 08 Jun 2023 08:23:37 +0000
parents 2e4afc93045d
children
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1 /*
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2 * SIM.H
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3 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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4 * Pole Star SIM
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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5 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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6 * Target : ARM
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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7 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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8 * Copyright (c) Texas Instruments 1995-1997
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9 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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10 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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12 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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13 * Device addresses - GCS000 (Gemini / Polestar)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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14 * HER207 (Hercules)
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15 */
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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17 #ifndef _WINDOWS
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18 #include "l1sw.cfg"
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19 #include "chipset.cfg"
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20 #endif
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21
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22 #include "nucleus.h"
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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24 /* Flags activation section */
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25 //#define SIM_RETRY /* by default : NOT ACTIVE */
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26 //#define SIM_DEBUG_TRACE /* by default : NOT ACTIVE */
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27 //#define SIM_UWORD16_MASK 0x00ff //when using SIM entity not maped to length on 16 bits
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28 #define SIM_UWORD16_MASK 0xffff //when using SIM entity maped to length on 16 bits
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29 //#define SIM_APDU_TEST
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30 //#define SIM_SAT_REFRESH_TEST
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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32 #define SIM_CMD (MEM_SIM + 0x00)
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33 #define SIM_STAT (MEM_SIM + 0x02)
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34 #define SIM_CONF1 (MEM_SIM + 0x04)
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35 #define SIM_CONF2 (MEM_SIM + 0x06)
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36 #define SIM_IT (MEM_SIM + 0x08)
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37 #define SIM_DRX (MEM_SIM + 0x0A)
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38 #define SIM_DTX (MEM_SIM + 0x0C)
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39 #define SIM_MASK (MEM_SIM + 0x0E)
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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41
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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42 /*
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43 * Bit definitions
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44 */
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45 // control regidter
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46 #define SIM_CMD_CRST 0x0001
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47 #define SIM_CMD_SWRST 0x0002
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48 #define SIM_CMD_STOP 0x0004
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49 #define SIM_CMD_START 0x0008
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50 #define SIM_CMD_CLKEN 0x0010
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51
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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52 // status register
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53 #define SIM_STAT_CD 0x0001 // card present
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54 #define SIM_STAT_TXPAR 0x0002 // transmit parity status
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55 #define SIM_STAT_FFULL 0x0004 // fifo full
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56 #define SIM_STAT_FEMPTY 0x0008 // fifo empty
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57
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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58 // configuration register
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59 #define SIM_CONF1_CHKPAR 0x0001 // enable receipt check parity
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60 #define SIM_CONF1_CONV 0x0002 // coding convention
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61 #define SIM_CONF1_TXRX 0x0004 // SIO line direction
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62 #define SIM_CONF1_SCLKEN 0x0008 // enable SIM clock
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63 #define SIM_CONF1_RSVD 0x0010 // reserved
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64 #define SIM_CONF1_SCLKDIV 0x0020 // SIM clock frquency
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65 #define SIM_CONF1_SCLKLEV 0x0040 // SIM clock idle level
0
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66 #define SIM_CONF1_ETU 0x0080 // ETU period
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67 #define SIM_CONF1_BYPASS 0x0100 // bypass hardware timers
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68 #define SIM_CONF1_SVCCLEV 0x0200
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69 #define SIM_CONF1_SRSTLEV 0x0400
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70 #define SIM_CONF1_SIOLOW 0x8000 //force SIO to low level
0
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71
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72 // interrupt status register
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73 #define SIM_IT_NATR 0x0001 // No answer to reset
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74 #define SIM_IT_WT 0x0002
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75 #define SIM_IT_ITOV 0x0004
0
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76 #define SIM_IT_ITTX 0x0008 // Transmit
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77 #define SIM_IT_ITRX 0x0010 // Receipt
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78
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79 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
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80 #define SIM_IT_CD 0x0001 // Card insertion/extraction
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81 #else
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82 #define SIM_IT_CD 0x0020 // Card insertion/extraction
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83 #endif
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84
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85 // interrupt mask register
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86 #define SIM_MASK_NATR 0x0001 // No answer to reset
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87 #define SIM_MASK_WT 0x0002
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88 #define SIM_MASK_OV 0x0004
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89 #define SIM_MASK_TX 0x0008 // Transmit
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90 #define SIM_MASK_RX 0x0010 // Receipt
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91 #define SIM_MASK_CD 0x0020 // Card insertion/extraction
0
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92
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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93 // receveid byte register
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94 #define SIM_DRX_STATRXPAR 0x0100 // received byte parity status
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95
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96 // SIM return code OK
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97 #define SIM_OK 0
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98
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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99 // SIM return error codes
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100 #define SIM_ERR_NOCARD 1
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101 #define SIM_ERR_NOINT 2
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102 #define SIM_ERR_NATR 3
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103 #define SIM_ERR_READ 4
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104 #define SIM_ERR_XMIT 5
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105 #define SIM_ERR_OVF 6
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106 #define SIM_ERR_LEN 7
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107 #define SIM_ERR_CARDREJECT 8
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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108 #define SIM_ERR_WAIT 9
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109 #define SIM_ERR_ABNORMAL_CASE1 10
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110 #define SIM_ERR_ABNORMAL_CASE2 11
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111 #define SIM_ERR_BUFF_OVERFL 12
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112
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
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113 // begin of JYT modifications
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 #define SIM_ERR_HARDWARE_FAIL 13
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115 // end of JYT modifications
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116 #define SIM_ERR_RETRY_FAILURE 14
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
118 #define SIM_SLEEP_NONE 0 // No SIM available
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 #define SIM_SLEEP_DESACT 1 // The Driver is NOT currently in sleep mode (clock is off)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120 #define SIM_SLEEP_ACT 2 // The Driver is currently in sleep mode (clock is on)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121 #define SIM_SLEEP_NOT_ALLOWED 3 // The Driver cannot stop the clock :
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
122 // The card don't want or the interface is not able
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
123 // to do it.
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 #define SIM_SLEEP_WAITING_TIME 500 //represent 2.3s of period before entering in sleep mode
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
126 #define SIM_CLK_STOP_MASK 0x0D // Clock Stop mask defined by ETSI 11.11
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 #define SIM_CLK_STOP_NOT_ALLWD 0x00 // see ETSI 11.11 : Clock Stop never allowed
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
128 #define SIM_CLK_STOP_ALLWD 0x01 // see ETSI 11.11 : No prefered level
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
129 #define SIM_CLK_STOP_HIGH 0x04 // see ETSI 11.11 : High level only
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
130 #define SIM_CLK_STOP_LOW 0x08 // see ETSI 11.11 : Low level only
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 #if(ANLG_FAM == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 //OMEGA specific definitions
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 #define MODE5V_OMEGA 0x06 // used in SIM_SwitchVolt
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 #define MODE_INIT_OMEGA_3V 0x05 // used in SIM_StartVolt
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 #define MODE_INIT_OMEGA_5V 0x07 // unused !!!!
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 #define MODE3V_OMEGA 0x01 // unused !!!!
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 #define MODE_DIS_SIMLDOEN 0xDF // used in SIM_PowerOff
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 #define MODE_DIS_SIMEN 0xFD // used in SIM_PowerOff
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 #define MODE_ENA_SIMLDOEN 0x20 // used in SIM_ManualStart
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 #define MODE_ENA_SIMEN 0x02 // used in SIM_ManualStart
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 #elif(ANLG_FAM == 2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 //IOTA specific definitions
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
144 #define MODE1_8V_IOTA 0x00
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 #define MODE_INIT_IOTA_3V 0x03
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
146 #define MODE_INIT_IOTA_1_8V 0x02
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 #define MODE3V_IOTA 0x01
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 #define MODE_DIS_SIMLDOEN 0xFC // SIMSEL + Regulator RSIMEN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 #define MODE_DIS_SIMEN 0xF7
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 #define MODE_ENA_SIMLDOEN 0x03 // SIMSEL + Regulator RSIMEN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 #define MODE_ENA_SIMEN 0x08
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 #elif(ANLG_FAM == 3)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 //SYREN specific definitions
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
154 #define MODE1_8V_SYREN 0x00
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 #define MODE_INIT_SYREN_3V 0x03
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
156 #define MODE_INIT_SYREN_1_8V 0x02
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 #define MODE3V_SYREN 0x01
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 #define MODE_DIS_SIMLDOEN 0x1FC // SIMSEL + Regulator RSIMEN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 #define MODE_DIS_SIMEN 0x1F7
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 #define MODE_ENA_SIMLDOEN 0x03 // SIMSEL + Regulator RSIMEN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 #define MODE_ENA_SIMEN 0x08
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 // define type of interface if not defined
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 // 5V only ME SIM_TYPE = 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 // 3V technology ME SIM_TYPE = 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 // 3V only ME SIM_TYPE = 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 // 1.8V technology ME SIM_TYPE = 3 // JYT, 29/01/02, from new specs IOTA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 // 1.8V Only ME SIM_TYPE = 4 // JYT, 29/01/02, from new specs IOTA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 #define SIM_TYPE_5V 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 #define SIM_TYPE_3_5V 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 #define SIM_TYPE_3V 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 #define SIM_TYPE_1_8_3V 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 #define SIM_TYPE_1_8V 4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 //default configuration
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 #ifndef SIM_TYPE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 #if((ANLG_FAM == 2) || (ANLG_FAM == 3))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 // Until now (20/03/2003), it is impossible to test IOTA or SYREN with 1.8V Sim Card,
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 // so SIM drv is configured in 3V only with IOTA.and SYREN
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
182 // When 1.8V Sim Card will be delivered and tested on IOTA and SYREN, then Sim driver will pass
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
183 // to : #define SIM_TYPE SIM_TYPE_1_8_3V
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
184 #define SIM_TYPE SIM_TYPE_1_8_3V // MODIFY BY JENNIFER SIM_TYPE_3V
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 #else
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
186 #define SIM_TYPE SIM_TYPE_3_5V
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 // begin of modifications of JYT
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 #if((ANLG_FAM == 2) || (ANLG_FAM == 3))
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
193 #define SIM_MASK_INFO_VOLT 0x70
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 #define SIM_MASK_INFO_VOLT 0x10
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 #define SIM_1_8V 0x30
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
199 #define SIM_3V 0x10
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 #define SIM_5V 0x00
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 // end of modifications of JYT
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 // Max size of Answer to Reset (GSM11.11 5.7.1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 #define MAX_ATR_SIZE 33
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 // GSM Instruction Class (GSM 11.11 SIM spec)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 #define GSM_CLASS 0xA0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 // SIM Instruction Codes
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
211 #define SIM_SELECT 0xA4
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
212 #define SIM_STATUS 0xF2
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
213 #define SIM_READ_BINARY 0xB0
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
214 #define SIM_UPDATE_BINARY 0xD6
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
215 #define SIM_READ_RECORD 0xB2
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
216 #define SIM_UPDATE_RECORD 0xDC
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
217 #define SIM_SEEK 0xA2
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
218 #define SIM_INCREASE 0x32
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
219 #define SIM_VERIFY_CHV 0x20
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
220 #define SIM_CHANGE_CHV 0x24
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
221 #define SIM_DISABLE_CHV 0x26
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
222 #define SIM_ENABLE_CHV 0x28
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
223 #define SIM_UNBLOCK_CHV 0x2C
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
224 #define SIM_INVALIDATE 0x04
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
225 #define SIM_REHABILITATE 0x44
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
226 #define SIM_RUN_GSM_ALGO 0x88
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
227 #define SIM_GET_RESPONSE 0xC0
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 #define SIM_TERMINAL_PROFILE 0x10
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
229 #define SIM_FETCH 0x12
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 #define SIM_TERMINAL_RESPONSE 0x14
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
231 #define SIM_ENVELOPE 0xC2
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 // SIM file identifiers
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 #define MF 0x3F00
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 #define EF_ICCID 0x2FE2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 #define DF_GSM 0x7F20
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 #define DF_DCS1800 0x7F21
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 #define EF_LP 0x6F05
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 #define EF_IMSI 0x6F07
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 #define EF_KC 0x6F20
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 #define EF_PLMNSEL 0x6F30
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 #define EF_HPLMN 0x6F31
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 #define EF_ACMAX 0x6F37
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 #define EF_SST 0x6F38
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 #define EF_ACM 0x6F39
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 #define EF_PUCT 0x6F41
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 #define EF_CBMI 0x6F45
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 #define EF_BCCH 0x6F74
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 #define EF_ACC 0x6F78
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 #define EF_FPLMN 0x6F7B
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 #define EF_LOCI 0x6F7E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 #define EF_AD 0x6FAD
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 #define EF_PHASE 0x6FAE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 #define DF_TELECOM 0x7F10
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 #define EF_ADN 0x6F3A
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 #define EF_FDN 0x6F3B
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 #define EF_SMS 0x6F3C
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 #define EF_CCP 0x6F3D
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 #define EF_MSISDN 0x6F40
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 #define EF_SMSP 0x6F42
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 #define EF_SMSS 0x6F43
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 #define EF_LND 0x6F44
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 #define EF_EXT1 0x6F4A
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 #define EF_EXT2 0x6F4B
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 #define EF_ECC 0x6FB7
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 #define MASK_INS 0xFE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 #define MASK_CMD 0x11
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
271 #define MASK_RST 0x10
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 // Buffer sizes
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 #define RSIMBUFSIZE 270
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
276 #define RSIZESW1SW2 2
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 #define XSIMBUFSIZE 270
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 // Structures
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 typedef struct
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 volatile unsigned short cmd;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 volatile unsigned short stat;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 volatile unsigned short conf1;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 volatile unsigned short conf2;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 volatile unsigned short it;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 volatile unsigned short rx;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 volatile unsigned short tx;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 volatile unsigned short maskit;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 volatile unsigned short it_cd;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 #endif
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
294 } SIM_CONTROLLER;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 typedef struct
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 SYS_UWORD8 Inverse;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 SYS_UWORD8 AtrSize;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 SYS_UWORD8 AtrData[MAX_ATR_SIZE];
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 } SIM_CARD;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 typedef struct
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 {
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 SIM_CONTROLLER *c;
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
308 SYS_UWORD8 *xIn; // xmit input pointer
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
309 SYS_UWORD8 *xOut; // xmit output pointer
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
310 unsigned errorSIM; // code return in case of error detectd
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
311 unsigned short conf1; // image of the configuration register - avoids read/mod/write cycles
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 volatile unsigned short txParityErr;
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
313 unsigned short rxParityErr; // if 0 no parity error on receipt, 1 if...
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
314 SYS_UWORD8 Freq_Algo; //use to determine which sim clk freq to choose for running GSM algo
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
315 SYS_UWORD8 PTS_Try; //use to calculate how many PTS try were already done
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
316 SYS_UWORD8 FileC; //value of File Characteristic
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 SYS_UWORD16 etu9600;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 SYS_UWORD16 etu400;
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
319 SYS_UWORD16 startclock; //744 clock cycle translated in ETU
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
320 SYS_UWORD16 stopclock; //1860 clock cycle translated in ETU
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
321 SYS_UWORD8 moderx; //inform that we are in receive mode
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 // 0 : mode of normal reception without procedure
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 // 1 : mode of wait for acknowledge during reception of char
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 // 2 : mode of reception of data by bloc
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 // 3 : mode of reception of data char by char (proc char)
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
326 // 4 : mode of reception of data char by char (data)
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 // 5 : mode of reception of procedure char SW1/SW2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 // 6 : mode of wait for acknowledge char after transmission of char
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
329 SYS_UWORD16 expected_data; //number of expected char in receive mode proc char
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
330 SYS_UWORD8 ack; //acknowledge char
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
331 SYS_UWORD8 null_received; //indicates if a NULL char was received
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
332 SYS_UWORD8 hw_mask; //mask used because of pole112 hw prb
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 SYS_UWORD8 rbuf[RSIMBUFSIZE];
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
335 SYS_UWORD8 rx_index; // receive index on rbuf buffer
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 SYS_UWORD8 xbuf[XSIMBUFSIZE];
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 SYS_UWORD8 rSW12[RSIZESW1SW2]; //buffer to store SW1 and SW2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 SYS_UWORD8 SWcount; //static counter
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 void (*InsertFunc)(SIM_CARD *);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 void (*RemoveFunc)(void);
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
342 SYS_UWORD16 apdu_ans_length;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 }
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 SIM_PORT;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 void SIM_IntHandler(void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 void SIM_CD_IntHandler(void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 * Prototypes
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
355 */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 // obsolete function
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 void SIM_Init(void (Insert(SIM_CARD *cP)), void (Remove(void)));
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
359 // initialization
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 void SIM_Initialize(void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 SYS_UWORD16 SIM_Register(void (Insert(SIM_CARD *cP)), void (Remove(void)));
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 SYS_UWORD16 SIM_Reset(SIM_CARD *cP);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363 SYS_UWORD16 SIM_Restart(SIM_CARD *cP);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 // file commands
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 SYS_UWORD16 SIM_Select(SYS_UWORD16 id, SYS_UWORD8 *dat, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 SYS_UWORD16 SIM_Status(SYS_UWORD8 *dat, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 SYS_UWORD16 SIM_ReadBinary(SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD16 len, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 SYS_UWORD16 SIM_UpdateBinary(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD16 len, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 SYS_UWORD16 SIM_ReadRecord(SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD16 len, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 SYS_UWORD16 SIM_UpdateRecord(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD16 len, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 SYS_UWORD16 SIM_Seek(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD16 len, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 SYS_UWORD16 SIM_Increase(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 // Authentication
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 SYS_UWORD16 SIM_VerifyCHV(SYS_UWORD8 *result, SYS_UWORD8 *chv, SYS_UWORD8 chvType, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 SYS_UWORD16 SIM_ChangeCHV(SYS_UWORD8 *result,SYS_UWORD8 *oldChv, SYS_UWORD8 *newChv, SYS_UWORD8 chvType, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 SYS_UWORD16 SIM_DisableCHV(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 SYS_UWORD16 SIM_EnableCHV(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 SYS_UWORD16 SIM_UnblockCHV(SYS_UWORD8 *result, SYS_UWORD8 *unblockChv, SYS_UWORD8 *newChv, SYS_UWORD8 chvType, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 // managing
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 SYS_UWORD16 SIM_Invalidate(SYS_UWORD8 *rP, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 SYS_UWORD16 SIM_Rehabilitate(SYS_UWORD8 *rP, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 SYS_UWORD16 SIM_RunGSMAlgo(SYS_UWORD8 *result, SYS_UWORD8 *rand, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 SYS_UWORD16 SIM_GetResponse(SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *size);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
388 // STK
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 SYS_UWORD16 SIM_TerminalProfile(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 SYS_UWORD16 SIM_Fetch(SYS_UWORD8 *result, SYS_UWORD16 len, SYS_UWORD16 *rcvSize);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 SYS_UWORD16 SIM_TerminalResponse(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 SYS_UWORD16 SIM_Envelope(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 // power off
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
395 void SIM_PowerOff(void);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 // WIM
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 SYS_UWORD16 SIM_XchTPDU(SYS_UWORD8 *dat, SYS_UWORD16 trxLen, SYS_UWORD8 *result,
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 SYS_UWORD16 rcvLen, SYS_UWORD16 *rcvSize);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 void SIM_lock_cr17689(void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 * Internal Prototypes
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
406 */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 void SIM_WriteBuffer(SIM_PORT *p, SYS_UWORD16 offset, SYS_UWORD16 n);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 SYS_UWORD16 SIM_Result(SIM_PORT *p, SYS_UWORD8 *rP, SYS_UWORD16 *lenP, SYS_UWORD8 offset);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 SYS_UWORD16 SIM_Command(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *rP, SYS_UWORD16 *lP);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 SYS_UWORD16 SIM_Command_Base(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *dP, SYS_UWORD16 *lP);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 SYS_UWORD16 SIM_Dummy(void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 void SIM_InitLog(void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 SYS_UWORD16 SIM_TxParityErrors();
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
415 SYS_UWORD16 SIM_WaitReception(SIM_PORT *p);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
416 void SIM_Interpret_FileCharacteristics(SIM_PORT *p);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
417 SYS_UWORD16 SIM_PTSprocedure(SIM_CARD *cP, SIM_PORT *p);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
418 void SIM_WARMReset (SIM_PORT *p);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
419 void SIM_SleepMode_In(SYS_UWORD32 param);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
420 void SIM_SleepMode_Out(SIM_PORT *p);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
421 SYS_UWORD8 SIM_GetFileCharacteristics(SIM_PORT *p);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
422 SYS_UWORD16 SIM_ATRdynamictreatement (SIM_PORT *p, SIM_CARD *cP);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
423 SYS_UWORD16 SIM_Waitforchars (SIM_PORT *p, SYS_UWORD16 max_wait);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
424 void SIM_Calcetu (SIM_PORT *p);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
425 SYS_UWORD8 SIM_Translate_atr_char (SYS_UWORD8 input, SIM_CARD *cP);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
428 SYS_UWORD8 SIM_StartVolt (SYS_UWORD8 ResetFlag);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
429 SYS_UWORD8 SIM_SwitchVolt (SYS_UWORD8 ResetFlag);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430
190
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
431 SYS_UWORD16 SIM_ManualStart (SIM_PORT *p);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
432 SYS_UWORD8 SIM_Memcpy(SYS_UWORD8 *Buff_target, SYS_UWORD8 Buff_source[], SYS_UWORD16 len);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
433 SYS_BOOL SIM_SleepStatus(void);
2e4afc93045d ../drv_app/sim/sim.h: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents: 189
diff changeset
434 SYS_UWORD16 SIM_Reset_Restart_Internal(SIM_CARD *cP, SYS_UWORD8 ResetFlag);
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 * Global variables
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
438 */
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 #ifdef SIM_C
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
440 #define SI_GLOBAL
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 #define SI_GLOBAL extern
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445
189
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
446 SI_GLOBAL SIM_PORT Sim[1];
b37e6c916df1 ../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
447 SI_GLOBAL NU_TIMER SIM_timer;
0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 SI_GLOBAL STATUS status_os_sim;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 SI_GLOBAL SYS_UWORD8 SIM_sleep_status;