FreeCalypso > hg > fc-tourmaline
annotate src/cs/drivers/drv_app/sim/sim32.c @ 303:f76436d19a7a default tip
!GPRS config: fix long-standing AT+COPS chance hanging bug
There has been a long-standing bug in FreeCalypso going back years:
sometimes in the AT command bring-up sequence of an ACI-only MS,
the AT+COPS command would produce only a power scan followed by
cessation of protocol stack activity (only L1 ADC traces), instead
of the expected network search sequence. This behaviour was seen
in different FC firmware versions going back to Citrine, and seemed
to follow some law of chance, not reliably repeatable.
This bug has been tracked down and found to be specific to !GPRS
configuration, stemming from our TCS2/TCS3 hybrid and reconstruction
of !GPRS support that was bitrotten in TCS3.2/LoCosto version.
ACI module psa_mms.c, needed only for !GPRS, was missing in the TCS3
version and had to be pulled from TCS2 - but as it turns out,
there is a new field in the MMR_REG_REQ primitive that needs to be
set correctly, and that psa_mms.c module is the place where this
initialization needed to be added.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Thu, 08 Jun 2023 08:23:37 +0000 |
parents | cf882d95c799 |
children |
rev | line source |
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1 /* |
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2 * SIM32.C |
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3 * |
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4 * Pole Star SIM |
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5 * |
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6 * Target : ARM |
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7 * |
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8 * Copyright (c) Texas Instruments 1995 |
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9 * |
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10 */ |
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11 |
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12 #define SIM32_C 1 |
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13 |
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14 #include "chipset.cfg" |
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15 |
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16 #include "main/sys_types.h" |
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17 #include <assert.h> |
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18 #include "inth/iq.h" |
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19 #include "sim.h" |
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20 |
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21 |
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22 #ifdef SIM_DEBUG_TRACE |
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23 /* working buffer for NULL BYTE */ |
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24 extern SYS_UWORD8 SIM_dbg_null[]; |
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25 /* Nucleus variable given the current number of TDMA frames */ |
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26 extern SYS_UWORD32 IQ_FrameCount; |
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27 /* working variable to calculate the TDMA ecart */ |
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28 extern SYS_UWORD16 SIM_dbg_tdma_diff; |
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29 /* working variable storing the current number of TDMA frames elapsed */ |
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30 SYS_UWORD32 SIM_dbg_local_count; |
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31 #endif |
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32 |
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33 /* |
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34 * SIM_IntHandler |
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35 * |
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36 * Read cause of SIM interrupt : |
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37 * |
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38 * if receive buffer full, read char |
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39 * if transmitter empty, change direction, transmit a dummy char |
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40 * |
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41 */ |
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42 void SIM_IntHandler(void) |
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43 { |
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44 volatile unsigned short it, i, stat, conf1; |
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45 volatile SYS_UWORD8 ins; |
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46 volatile SYS_UWORD8 rx; |
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47 volatile SYS_UWORD8 nack; |
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48 volatile SYS_UWORD8 nack1; |
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49 |
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50 SIM_PORT *p; |
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51 |
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52 p = &(Sim[0]); |
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53 |
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54 p->rxParityErr = 0; |
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55 it = p->c->it; |
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56 |
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57 if ((it & SIM_IT_ITRX) && !(p->c->maskit & SIM_MASK_RX)) // int on reception |
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58 { |
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59 stat = p->c->rx; |
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60 conf1 = p->conf1; |
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61 |
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62 #ifdef SIM_DEBUG_TRACE |
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63 if ((IQ_FrameCount - SIM_dbg_local_count) > SIM_dbg_tdma_diff) { |
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64 SIM_dbg_tdma_diff = IQ_FrameCount - SIM_dbg_local_count; |
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65 } |
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66 SIM_dbg_local_count = IQ_FrameCount; |
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67 #endif |
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68 |
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69 // Check if reception parity is enable |
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70 if (((conf1 & SIM_CONF1_CHKPAR) && ((stat & SIM_DRX_STATRXPAR) != 0))\ |
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71 || ((conf1 & SIM_CONF1_CHKPAR) == 0)) |
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72 { |
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73 rx = (SYS_UWORD8) (stat & 0x00FF); |
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74 ins = p->xbuf[1] & p->hw_mask; |
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75 nack = (~p->xbuf[1]) & p->hw_mask; |
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76 |
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77 switch (p->moderx) |
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78 { |
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79 case 0: //mode of normal reception without proc char (like PTS proc) |
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80 p->rbuf[p->rx_index++] = rx; |
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81 break; |
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82 |
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83 case 1: //mode wait for ACK |
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84 if ((rx & p->hw_mask) == ins) |
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85 { |
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86 p->moderx = 2; |
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87 } |
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88 else if ((rx & p->hw_mask) == nack) |
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89 { |
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90 p->moderx = 4; |
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91 } |
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92 else if (((rx & 0xF0) == 0x60) || ((rx & 0xF0) == 0x90)) |
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93 { |
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94 if (rx != 0x60) //in case of error code (SW1/SW2) returned by sim card |
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95 { |
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96 p->rSW12[p->SWcount++] = rx; |
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97 p->moderx = 5; |
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98 } |
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99 else |
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100 { |
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101 p->null_received = 1; |
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102 #ifdef SIM_DEBUG_TRACE |
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103 SIM_dbg_null[0]++; |
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104 #endif |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
105 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
106 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
107 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
108 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
109 p->errorSIM = SIM_ERR_ABNORMAL_CASE2; |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
110 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
111 //if rx = 0x60 wait for ACK |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
112 break; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
113 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
114 case 2: //mode reception by block |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
115 p->rbuf[p->rx_index++] = rx; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
116 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
117 if(p->expected_data == 256) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
118 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
119 if (p->rx_index == 0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
120 { |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
121 p->moderx = 5; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
122 } |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
123 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
124 else |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
125 { |
192
cf882d95c799
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
126 if (p->rx_index == p->expected_data) |
cf882d95c799
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
127 { |
cf882d95c799
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
128 p->moderx = 5; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
129 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
130 } |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
131 break; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
132 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
133 case 3: //mode reception char by char. reception of proc char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
134 if ((rx & p->hw_mask) == ins) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
135 { |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
136 p->moderx = 2; |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
137 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
138 else if ((rx & p->hw_mask) == nack) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
139 { |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
140 p->moderx = 4; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
141 } //if rx = 0x60 wait for ACK |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 else if (rx == 0x60) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
143 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
144 p->null_received == 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
145 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 SIM_dbg_null[1]++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 #endif |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
148 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
149 break; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
150 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
151 case 4: //mode reception char by char. reception of data |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
152 p->rbuf[p->rx_index++] = rx; |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
153 p->moderx = 3; //switch to receive proc char mode |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
154 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 if(p->expected_data == 256) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 if (p->rx_index == 0) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 p->moderx = 5; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 else |
189
b37e6c916df1
../drv_app/sim/*: rm trailing white space
Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
163 { |
192
cf882d95c799
.../drv_app/sim/sim32.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
164 if (p->rx_index == p->expected_data) |
cf882d95c799
.../drv_app/sim/sim32.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
165 { |
cf882d95c799
.../drv_app/sim/sim32.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
166 p->moderx = 5; |
cf882d95c799
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Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
167 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 break; |
189
b37e6c916df1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
170 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 case 5: //mode wait for procedure character except NULL |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 if ((rx != 0x60) || (p->SWcount != 0)) //treat NULL character only if arriving before SW1 SW2 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 p->rSW12[p->SWcount++] = rx; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 p->null_received = 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 SIM_dbg_null[2]++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 break; |
189
b37e6c916df1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
184 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 case 6: //give the acknowledge char |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 if (((rx & 0xF0) == 0x60) || ((rx & 0xF0) == 0x90)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 if (rx != 0x60) //in case of error code (SW1/SW2) returned by sim card |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
189 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
190 p->rSW12[p->SWcount++] = rx; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 p->moderx = 5; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
193 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
194 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
195 p->null_received = 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
196 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
197 SIM_dbg_null[3]++; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
198 #endif |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
199 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
200 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
201 else |
189
b37e6c916df1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
202 { |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
203 p->ack = rx; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
204 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
205 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
206 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
207 else |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
208 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
209 p->rxParityErr = 1; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
210 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
211 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
212 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
213 if ((it & SIM_IT_ITTX) && !(p->c->maskit & SIM_MASK_TX)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
214 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
215 #ifdef SIM_DEBUG_TRACE |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
216 SIM_dbg_local_count = IQ_FrameCount; |
4e78acac3d88
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parents:
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217 #endif |
4e78acac3d88
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parents:
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218 // check the transmit parity |
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parents:
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219 stat = p->c->stat; |
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220 |
4e78acac3d88
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parents:
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221 if ((stat & SIM_STAT_TXPAR) || ((p->conf1 & SIM_CONF1_CHKPAR) == 0)) //parity disable |
4e78acac3d88
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222 { |
4e78acac3d88
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parents:
diff
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223 if (p->xOut != (p->xIn - 1)) //if only one char transmitted (already transmitted) |
4e78acac3d88
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parents:
diff
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224 { //just need to have confirmation of reception |
4e78acac3d88
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225 if (p->xOut == (p->xIn - 2)) |
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parents:
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226 { |
4e78acac3d88
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227 p->xOut++; |
4e78acac3d88
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228 p->c->tx = *(p->xOut); // transmit |
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229 |
4e78acac3d88
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parents:
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230 p->conf1 &= ~SIM_CONF1_TXRX; // return the direction |
4e78acac3d88
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parents:
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231 p->c->conf1 = p->conf1; |
4e78acac3d88
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232 } |
189
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0
diff
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233 |
0
4e78acac3d88
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234 if (p->xOut < (p->xIn - 2)) |
4e78acac3d88
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|
235 { |
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236 p->xOut++; |
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237 p->c->tx = *(p->xOut); // transmit |
189
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|
238 } |
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diff
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|
239 } |
0
4e78acac3d88
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|
240 } |
4e78acac3d88
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parents:
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|
241 else |
4e78acac3d88
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parents:
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|
242 { |
4e78acac3d88
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243 p->c->tx = *(p->xOut); // transmit same char |
189
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diff
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244 p->txParityErr++; // count number of transmit parity errors |
0
4e78acac3d88
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|
245 } |
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|
246 } |
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|
247 |
4e78acac3d88
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248 // Handle errors |
4e78acac3d88
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parents:
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249 if ((it & SIM_IT_ITOV) && !(p->c->maskit & SIM_MASK_OV)) |
4e78acac3d88
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parents:
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|
250 { |
4e78acac3d88
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parents:
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|
251 p->errorSIM = SIM_ERR_OVF; |
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parents:
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|
252 } |
4e78acac3d88
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parents:
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253 if ((it & SIM_IT_WT) && !(p->c->maskit & SIM_MASK_WT)) |
4e78acac3d88
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parents:
diff
changeset
|
254 { |
4e78acac3d88
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parents:
diff
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|
255 p->errorSIM = SIM_ERR_READ; |
4e78acac3d88
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parents:
diff
changeset
|
256 } |
4e78acac3d88
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parents:
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257 |
4e78acac3d88
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parents:
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258 // Reset the card in case of NATR to let the program continue |
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parents:
diff
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|
259 if ((it & SIM_IT_NATR) && !(p->c->maskit & SIM_MASK_NATR)) |
4e78acac3d88
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parents:
diff
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|
260 { |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
261 p->c->cmd = SIM_CMD_STOP; |
4e78acac3d88
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parents:
diff
changeset
|
262 p->errorSIM = SIM_ERR_NATR; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
263 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
264 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
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parents:
diff
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|
265 #if ((CHIPSET == 2) || (CHIPSET == 3)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
266 // SIM card insertion / extraction |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
267 if ((it & SIM_IT_CD) && !(p->c->maskit & SIM_MASK_CD)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
268 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
269 stat = p->c->stat; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
270 if ((stat & SIM_STAT_CD) != SIM_STAT_CD) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
271 { |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
272 (p->RemoveFunc)(); |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
273 p->errorSIM = SIM_ERR_NOCARD; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
274 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
275 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
276 #endif |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
277 } |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
278 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
279 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
280 /* |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
281 * SIM_CD_IntHandler |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
282 * |
189
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parents:
0
diff
changeset
|
283 * Read cause of SIM interrupt : |
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parents:
0
diff
changeset
|
284 * |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
285 */ |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
286 void SIM_CD_IntHandler(void) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
287 { |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
288 volatile unsigned short it_cd, stat; |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
289 SIM_PORT *p; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
290 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
291 p = &(Sim[0]); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
292 |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
293 p->rxParityErr = 0; |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
294 it_cd = p->c->it_cd; |
4e78acac3d88
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parents:
diff
changeset
|
295 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
296 // SIM card insertion / extraction |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
297 if ((it_cd & SIM_IT_CD) && !(p->c->maskit & SIM_MASK_CD)) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
298 { |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
299 stat = p->c->stat; |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
300 if ((stat & SIM_STAT_CD) != SIM_STAT_CD) |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
301 { |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
302 (p->RemoveFunc)(); |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
303 p->errorSIM = SIM_ERR_NOCARD; |
4e78acac3d88
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parents:
diff
changeset
|
304 } |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
305 } |
192
cf882d95c799
.../drv_app/sim/sim32.c: white space fixes
Mychaela Falconia <falcon@freecalypso.org>
parents:
189
diff
changeset
|
306 } |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
307 #endif |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
308 |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
309 |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
310 // to force this module to be linked |
4e78acac3d88
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
311 SYS_UWORD16 SIM_Dummy(void) |
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
312 { |
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
0
diff
changeset
|
313 |
0
4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
314 } |