fc-tourmaline: src/cs/layer1/include/l1

annotate src/cs/layer1/include/l1_confg.h @ 303:f76436d19a7a default tip

!GPRS config: fix long-standing AT+COPS chance hanging bug There has been a long-standing bug in FreeCalypso going back years: sometimes in the AT command bring-up sequence of an ACI-only MS, the AT+COPS command would produce only a power scan followed by cessation of protocol stack activity (only L1 ADC traces), instead of the expected network search sequence. This behaviour was seen in different FC firmware versions going back to Citrine, and seemed to follow some law of chance, not reliably repeatable. This bug has been tracked down and found to be specific to !GPRS configuration, stemming from our TCS2/TCS3 hybrid and reconstruction of !GPRS support that was bitrotten in TCS3.2/LoCosto version. ACI module psa_mms.c, needed only for !GPRS, was missing in the TCS3 version and had to be pulled from TCS2 - but as it turns out, there is a new field in the MMR_REG_REQ primitive that needs to be set correctly, and that psa_mms.c module is the place where this initialization needed to be added.

author	Mychaela Falconia <falcon@freecalypso.org>
date	Thu, 08 Jun 2023 08:23:37 +0000
parents	5caa86ee2cfa
children

rev	line source
0 4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /*********** Revision Controle System Header ***********
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * GSM Layer 1 software
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 * L1_CONFG.H
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * Filename l1_confg.h
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * Copyright 2003 (C) Texas Instruments
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 *********** Revision Controle System Header ***********/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 #ifndef __L1_CONFG_H__
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 #define __L1_CONFG_H__
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 #ifndef _WINDOWS
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 #include "l1sw.cfg" // Configuration Software
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 #include "board.cfg"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16 #include "chipset.cfg"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #include "rf.cfg"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 #include "swconfig.cfg"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 #include "sys.cfg"
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 // Traces...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 // TRACE_TYPE == 1 -> L1/L3 interface trace
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 // TRACE_TYPE == 2 -> Trace mode: ~33~~1~011...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 // TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 // TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 // TRACE_TYPE == 5 -> trace for full simulation
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 // TRACE_TYPE == 6 -> CPU load trace for hisr
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 // TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 // UART at 38400 bps =>
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 // format : <hisr cpu value in microseconds> <frame number>
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 // Code PB reported workaround
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 //------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 // Code Version possible choices
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 //------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 #define SIMULATION 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 #define NOT_SIMULATION 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 // RCL functions Version possible choices
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 //------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #define POLL_FORCED 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #define RLC_SCENARIO 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 #define MODEM_FLOW 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 // possible choices for UART trace output
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 //------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 #define MODEM_UART 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #define IRDA_UART 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #if (CHIPSET == 12)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #define MODEM2_UART 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 //============
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 // CODE CHOICE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 //============
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #if (OP_L1_STANDALONE==0)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define CODE_VERSION NOT_SIMULATION
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #else // OP_L1_STANDALONE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #ifdef WIN32
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 #define CODE_VERSION SIMULATION
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #else // WIN32
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #define CODE_VERSION NOT_SIMULATION
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #endif // WIN32
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #endif // OP_L1_STANDALONE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 //---------------------------------------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 // Test with full simulation.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 //---------------------------------------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 #if (CODE_VERSION == SIMULATION)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 // Test Scenari...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 // Traces...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 #undef TRACE_TYPE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82 #define TRACE_TYPE 5
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 #define LOGFILE_TRACE 1 // trace in an output logfile
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 #define FLOWCHART 0 // Message sequence/flow chart trace.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 #define NUCLEUS_TRACE 0 // Nucleus error trace
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #define EOTD_TRACE 1 // EOTD log trace
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 // Control algorithms...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 #define AFC_ALGO 1 // AFC algorithm.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define TOA_ALGO 1 // TOA algorithm.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94 #define AGC_ALGO 1 // AGC algorithm.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 #undef VCXO_ALGO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 #define VCXO_ALGO 0 // VCXO algo
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98 #undef DCO_ALGO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 #define DCO_ALGO 0 // DCO algo (TIDE)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #undef ORDER2_TX_TEMP_CAL
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 #define FACCH_TEST 0 // FACCH test enabled.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #define ADC_TIMER_ON 0 // Timer for ADC measurements
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107 #define AFC_ON 1 // Enable of the Omega AFC module
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 #define AUDIO_TASK 1 // Enable the L1 audio features
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 #define TTY_SYNC_MCU_2 1 //
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 #define NEW_WKA_PATCH 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #define OPTIMISED 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120 #define L1_RECOVERY 0 // L1 recovery
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 #undef L1_GPRS
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #undef AMR
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 #define AMR 1 // AMR version 1.0 supported
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 #undef L1_12NEIGH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 #define L1_12NEIGH 1 // new L1-RR interface for 12 neighbour cells
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131 #undef L1_GTT
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 #define L1_GTT 1 // Enable Global Text Telephony feature for simulation
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 #undef OP_L1_STANDALONE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135 #define OP_L1_STANDALONE 1 // Selection of code for L1 stand alone
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 #undef OP_RIV_AUDIO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 #undef OP_WCP
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 #define OP_WCP 0 // No WCP integration
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 //---------------------------------------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 // Test with H/W platform.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 //---------------------------------------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 #elif (CODE_VERSION == NOT_SIMULATION)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 // (corrected with Calypso ReV B and Calypso C035)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #if (CHIPSET == 7)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 #define W_A_CALYPSO_BUG_01435 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #define W_A_CALYPSO_BUG_01435 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 // for AMR thresolds definition CQ22226
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #define AMR_THRESHOLDS_WORKAROUND 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #if (L1_GTT==1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161 #define TTY_SYNC_MCU 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 #define TTY_SYNC_MCU_2 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 #define L1_GTT_FIFO_TEST_ATOMIC 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 #define NEW_WKA_PATCH 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 #define OPTIMISED 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 #define TTY_SYNC_MCU_2 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define L1_GTT_FIFO_TEST_ATOMIC 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169 #define TTY_SYNC_MCU 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 #define NEW_WKA_PATCH 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #define OPTIMISED 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 // Traces...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 #define NUCLEUS_TRACE 0 // Nucleus error trace
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 #define FLOWCHART 0 // Message sequence/flow chart trace.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 #define LOGFILE_TRACE 0 // trace in an output logfile
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 // Test Scenari...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #define SCENARIO_FILE 0 // Test Scenario comes from input files.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 #define SCENARIO_MEM 1 // // Test Scenario comes from RAM.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 #if (OP_L1_STANDALONE == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 #define L2_L3_SIMUL 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 // Control algorithms...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 #define AFC_ALGO 1 // AFC algorithm.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 #define TOA_ALGO 1 // TOA algorithm.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #define AGC_ALGO 1 // AGC algorithm.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 #define FACCH_TEST 0 // FACCH test enabled.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 #define ADC_TIMER_ON 0 // Timer for ADC measurements
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 #define AFC_ON 1 // Enable of the Omega AFC module
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 #define AUDIO_TASK 1 // Enable the L1 audio features
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 #if (OP_L1_STANDALONE == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 #define AUDIO_L1_STANDALONE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 #define L1_RECOVERY 1 // L1 recovery
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 #if (L1_GPRS == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 #define RLC_VERSION RLC_SCENARIO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 #if (RLC_VERSION == RLC_SCENARIO)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222 // output stat on CRC error blocks
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 // The user must enter the cs type and
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224 // the number of frames desired.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 #if (OP_L1_STANDALONE == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230 #define DSP_BACKGROUND_TASKS 1 // Enable the TEST of DSP background.tasks
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 // activated by a layer 3 message (BG_TASK_START (<task number>))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 // deactivated by a layer 3 message (BG_TASK_STOP (<task number>))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233 // Warning : Works only with DSP>=31
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 #define DSP_BACKGROUND_TASKS 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239 #define DSP_BACKGROUND_TASKS 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244 // Audio tasks selection
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 //-----------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 #if (AUDIO_TASK == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 #define KEYBEEP 1 // Enable keybeep feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249 #define TONE 1 // Enable tone feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 #if (OP_L1_STANDALONE == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252 #define GSMLITE 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254 #if ((OP_L1_STANDALONE == 1) \|\| (!GSMLITE))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 #define MELODY_E1 1 // Enable melody format E1 feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256 #define VOICE_MEMO 1 // Enable voice memorization feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 #define FIR 1 // Enable FIR feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 #if (DSP == 33) \|\| (DSP == 34) \|\| (DSP == 35) \|\| (DSP == 36)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 #define AUDIO_MODE 1 // Enable Audio mode feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262 #define AUDIO_MODE 0 // Disable Audio mode feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 #define MELODY_E1 0 // Disable melody format E1 feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 #define VOICE_MEMO 0 // Disable voice memorization feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267 #if (MELODY_E2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 #define FIR 1 // Enable FIR feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 #define FIR 0 // Disable FIR feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 #define AUDIO_MODE 0 // Disable Audio mode feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 // Define CPORT for ESample only
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 #if ((CHIPSET == 12) && ((DSP == 35) \|\| (DSP == 36)))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277 #define L1_CPORT 1 // Enable cport feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 #define L1_CPORT 0 // Disable cport feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 #define KEYBEEP 0 // Enable keybeep feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 #define TONE 0 // Enable tone feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 #define MELODY_E1 0 // Enable melody format E1 feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 #define VOICE_MEMO 0 // Enable voice memorization feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 #define FIR 0 // Enable FIR feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 #define AUDIO_MODE 0 // Enable Audio mode feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 #define L1_CPORT 0 // Enable cport feature
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO \| MELODY_E2) // audio background task is used by speech reco and melody_e2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 #if (OP_RIV_AUDIO == 1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 // Vocoder selections
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 //-------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 #define FR 1 // Full Rate
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 #define FR_HR 2 // Full Rate + Half Rate
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 // Standard (frequency plan) selections
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 //-------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 #define GSM 1 // GSM900.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 #define GSM_E 2 // GSM900 Extended.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 #define PCS1900 3 // PCS1900.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 #define DCS1800 4 // DCS1800.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 #define GSM850 7 // GSM850 Band
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 #define DUAL_US 8 // PCS1900 + GSM850
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319 /------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 /* Power Management */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321 /------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 /---------------------------------------------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 /* DSP configurations */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327 /* ------------------ */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 /* DSP \| FR\| HR\|EFR\|14.4\| SPEED \|12LA68\|12LA68 \|4L32\|AEC\| MCU/DSP */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 /* (version) \| \| \| \| \| \|POLE80\|POLE112\| \|/NS\| interface */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 /* 0 (821) \| x \| \| \| \| 39Mhz \| x \| \| \| \| 1 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 /* 1 (830) \| x \| \| \| \| 39Mhz \| (1) \| \| x \| \| 1 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 /* 2 (912) \| x \| x \| \| \| 58.5Mhz \| x \| \| \| \| 2 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 /* 3 (10xx) \| x \| \| x \| x \| 65Mhz \| x \| \| \| x \| 3 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 /* ----------+---+---+---+----+---------+------+-------+----\|---+---------- */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 /* 4 (11xx) \| x \| x \| x \| x \| 65Mhz \| x \| x (3)\| \| x \| 3 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 /* 5 (830) \| x \| \| \| \| 39Mhz \| x \| \| \| \| 1 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343 /* 6 (11xx) \| x \| x \| x \| x \| 65Mhz \| x \| x (3)\| \|(2)\| 3 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 /(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 /* not corrected. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 /(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP /
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 /* interface which support AEC, therefore AEC is defined as 1. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352 /(3) Pole112 include RIF DL correction. No patch is needed if this one only /
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 /* include RIF/DL problem. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 /* */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 /---------------------------------------------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #if (DSP == 16 \|\| DSP == 17)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 /* #define CLKMOD1 0x414e // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 #define CLKMOD2 0x414e // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 #define CLKSTART 0x29 // ...65 Mips */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 #define CLKMOD1 0x4006 // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363 #define CLKMOD2 0x4116 // ...65 Mips pll free
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 #define CLKSTART 0x29 // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 /* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 #define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368 #define CLKSTART 0x25 // ...39 Mips */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 #define VOC FR_HR_EFR // FR + HR + EFR.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 #define DATA14_4 1 // No 14.4 data allowed.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372 #define AEC 1 // AEC/NS supported.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373 #define MAP 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 #define DSP_START 0x2000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379 /* DSP debug trace configuration */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 #if (MELODY_E2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 // In case of the melody E2 the DSP trace must be disable because the
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 // melody instrument waves are overlayed with DSP trace buffer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 #elif (DSP == 30) // First GPRS.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 #define CLKMOD1 0x4006 // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 #define CLKMOD2 0x4116 // ...65 Mips pll free
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 #define CLKSTART 0x29 // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 #define VOC FR_HR_EFR // FR + HR + EFR.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400 #define DATA14_4 1 // No 14.4 data allowed.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 #define AEC 1 // AEC/NS not supported.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402 #define MAP 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 #define DSP_START 0x1F81
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405 #define ULYSSE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 #elif (DSP == 31) // ROM Code GPRS G0.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409 #define CLKMOD1 0x4006 // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 #define CLKMOD2 0x4116 // ...65 Mips pll free
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 #define CLKSTART 0x29 // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 #define DATA14_4 1 // 14.4 data allowed.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 #define AEC 1 // AEC/NS not supported.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 #define MAP 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 #define DSP_START 0x8763
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 #define ULYSSE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427 #elif (DSP == 32) // ROM Code GPRS G1.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428 #define CLKMOD1 0x4006 // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 #define CLKMOD2 0x4116 // ...65 Mips pll free
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 #define CLKSTART 0x29 // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 #define DATA14_4 1 // 14.4 data allowed.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 #define AEC 1 // AEC/NS not supported.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 #define MAP 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 #define DSP_START 0x8763
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 #define ULYSSE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 #elif (DSP == 33) // ROM Code GPRS.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446 #define CLKMOD1 0x4006 // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447 #define CLKMOD2 0x4116 // ...65 Mips pll free
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 #define CLKSTART 0x29 // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451 #define AEC 1 // AEC/NS not supported.
273 5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	452 /* FreeCalypso change: enable L1_NEW_AEC to match DSP reality */
5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	453 /* with DSP ROM 33 our patch version 2140 must be used */
5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	454 #define L1_NEW_AEC 1
0 4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455 #if ((L1_NEW_AEC) && (!AEC))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 // First undef the flag to avoid warnings at compilation time
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 #undef AEC
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 #define AEC 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 #define MAP 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463 #define DSP_START 0x7000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 #define ULYSSE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 // management.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478 // DSP_IDLE3 is not supported in simulation
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481 #define W_A_DSP_IDLE3 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 // DSP software work-around config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485 // bit0 - Work-around to support CRTG.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 #define C_DSP_SW_WORK_AROUND 0x0006
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 #elif (ANLG_FAM == 2) // IOTA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 #define C_DSP_SW_WORK_AROUND 0x000E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496 #elif (ANLG_FAM == 3) // SYREN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 #define C_DSP_SW_WORK_AROUND 0x000E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501 /* DSP debug trace configuration */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 #if (MELODY_E2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504 // In case of the melody E2 the DSP trace must be disable because the
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 // melody instrument waves are overlayed with DSP trace buffer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 // DSP debug trace type config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518 // Currently not supported !
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 // DSP debug trace type config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 /* d_error_status */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 #define DSP_DEBUG_GSM_MASK 0x0000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542 #define DSP_DEBUG_GPRS_MASK 0x0f3d
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545 #if DCO_ALGO
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546 // DCO type of scheduling
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 #define C_CN_DCO_PARAM 0xA248
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 #elif (DSP == 34) // ROM Code GPRS AMR.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 #define CLKMOD1 0x4006 // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552 #define CLKMOD2 0x4116 // ...65 Mips pll free
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553 #define CLKSTART 0x29 // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 #define AEC 1 // AEC/NS not supported.
273 5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	557 /* FreeCalypso change: enable L1_NEW_AEC to match DSP reality */
5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	558 #define L1_NEW_AEC 1
0 4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 #if ((L1_NEW_AEC) && (!AEC))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 // First undef the flag to avoid warnings at compilation time
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561 #undef AEC
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 #define AEC 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 #define MAP 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 #define DSP_START 0x7000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571 #define ULYSSE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	573 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	574
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	575 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	576
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	577 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	578
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	579 // management.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	580
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	581 // DSP_IDLE3 is not supported in simulation
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	582
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	583 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	584 #define W_A_DSP_IDLE3 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	585 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	586
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	587 // DSP software work-around config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	588 // bit0 - Work-around to support CRTG.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	589 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	590 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	591 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	592 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	593 #define C_DSP_SW_WORK_AROUND 0x0006
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	594
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	595 #elif (ANLG_FAM == 2) // IOTA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	596 #define C_DSP_SW_WORK_AROUND 0x000E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	597
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	598 #elif (ANLG_FAM == 3) // SYREN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	599 #define C_DSP_SW_WORK_AROUND 0x000E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	600
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	601 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	602
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	603 /* DSP debug trace configuration */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	604 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	605 #if (MELODY_E2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	606 // In case of the melody E2 the DSP trace must be disable because the
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	607 // melody instrument waves are overlayed with DSP trace buffer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	608
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	609 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	610 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	611 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	612
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	613 // DSP debug trace type config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	614 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	615 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	616 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	617
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	618 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	619 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	620 // Currently not supported !
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	621 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	622 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	623 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	624 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	625 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	626
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	627 // DSP debug trace type config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	628 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	629 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	630 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	631
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	632 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	633 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	634 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	635
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	636 // AMR trace
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	637 #define C_AMR_TRACE_ID 55
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	638
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	639 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	640 /* d_error_status */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	641 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	642
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	643 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	644 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	645
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	646 // masks to apply on d_error_status bit field
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	647 #define DSP_DEBUG_GSM_MASK 0x0000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	648 #define DSP_DEBUG_GPRS_MASK 0x0f3d
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	649 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	650
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	651 #elif (DSP == 35) // ROM Code GPRS AMR.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	652 #define CLKMOD1 0x4006 // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	653 #define CLKMOD2 0x4116 // ...65 Mips pll free
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	654 #define CLKSTART 0x29 // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	655 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	656 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	657 #define AEC 1 // AEC/NS not supported.
273 5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	658 /* FreeCalypso change: enable L1_NEW_AEC to match DSP reality */
5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	659 #define L1_NEW_AEC 1
0 4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	660 #if ((L1_NEW_AEC) && (!AEC))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	661 // First undef the flag to avoid warnings at compilation time
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	662 #undef AEC
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	663 #define AEC 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	664 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	665 #define MAP 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	666
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	667 #define FF_L1_TCH_VOCODER_CONTROL 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	668 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	669
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	670 #define DSP_START 0x7000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	671
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	672 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	673
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	674 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	675 #define ULYSSE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	676
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	677 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	678
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	679 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	680
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	681 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	682
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	683 // management.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	684
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	685 // DSP_IDLE3 is not supported in simulation
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	686
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	687 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	688 #define W_A_DSP_IDLE3 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	689 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	690
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	691 // DSP software work-around config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	692 // bit0 - Work-around to support CRTG.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	693 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	694 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	695 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	696 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	697 #define C_DSP_SW_WORK_AROUND 0x0006
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	698
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	699 #elif (ANLG_FAM == 2) // IOTA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	700 #define C_DSP_SW_WORK_AROUND 0x000E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	701
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	702 #elif (ANLG_FAM == 3) // SYREN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	703 #define C_DSP_SW_WORK_AROUND 0x000E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	704
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	705 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	706
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	707 /* DSP debug trace configuration */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	708 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	709 #if (MELODY_E2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	710 // In case of the melody E2 the DSP trace must be disable because the
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	711 // melody instrument waves are overlayed with DSP trace buffer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	712
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	713 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	714 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	715 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	716
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	717 // DSP debug trace type config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	718 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	719 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	720 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	721
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	722 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	723 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	724 // Currently not supported !
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	725 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	726 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	727 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	728 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	729 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	730
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	731 // DSP debug trace type config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	732 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	733 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	734 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	735
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	736 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	737 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	738 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	739
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	740 // AMR trace
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	741 #define C_AMR_TRACE_ID 55
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	742
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	743 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	744 /* d_error_status */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	745 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	746
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	747 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	748 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	749
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	750 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	751 #define DSP_DEBUG_GSM_MASK 0x08BD
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	752 #define DSP_DEBUG_GPRS_MASK 0x0f3d
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	753 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	754 #elif (DSP == 36) // ROM Code GPRS AMR.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	755 #define CLKMOD1 0x4006 // ...
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	756 #define CLKMOD2 0x4116 // ...65 Mips pll free
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	757 #define CLKSTART 0x29 // ...65 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	758 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	759 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	760 #define AEC 1 // AEC/NS not supported.
273 5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	761 /* FreeCalypso change: enable L1_NEW_AEC to match DSP reality */
5caa86ee2cfa enable L1_NEW_AEC in l1_confg.h (bold change) Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	762 #define L1_NEW_AEC 1
0 4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	763 #if ((L1_NEW_AEC) && (!AEC))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	764 // First undef the flag to avoid warnings at compilation time
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	765 #undef AEC
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	766 #define AEC 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	767 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	768 #define MAP 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	769 #undef L1_AMR_NSYNC
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	770 #define L1_AMR_NSYNC 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	771 #define FF_L1_TCH_VOCODER_CONTROL 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	772 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	773
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	774 #define DSP_START 0x7000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	775
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	776 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	777
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	778 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	779 #define ULYSSE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	780
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	781 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	782
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	783 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	784
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	785 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	786
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	787 // management.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	788
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	789 // DSP_IDLE3 is not supported in simulation
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	790
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	791 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	792 #define W_A_DSP_IDLE3 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	793 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	794
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	795 // DSP software work-around config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	796 // bit0 - Work-around to support CRTG.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	797 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	798 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	799 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	800 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	801 #define C_DSP_SW_WORK_AROUND 0x0006
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	802
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	803 #elif (ANLG_FAM == 2) // IOTA
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	804 #define C_DSP_SW_WORK_AROUND 0x000E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	805
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	806 #elif (ANLG_FAM == 3) // SYREN
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	807 #define C_DSP_SW_WORK_AROUND 0x000E
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	808 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	809
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	810 // This workaround should be enabled only for H2-sample on full build config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	811 #if (OP_L1_STANDALONE==1)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	812 #define RAZ_VULSWITCH_REGAUDIO 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	813 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	814
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	815 /* DSP debug trace configuration */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	816 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	817 #if (MELODY_E2)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	818 // In case of the melody E2 the DSP trace must be disable because the
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	819 // melody instrument waves are overlayed with DSP trace buffer
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	820
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	821 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	822 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	823 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	824
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	825 // DSP debug trace type config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	826 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	827 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	828 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	829
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	830 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	831 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	832 // Currently not supported !
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	833 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	834 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	835 // DSP debug trace API buufer config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	836 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	837 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	838
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	839 // DSP debug trace type config
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	840 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	841 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	842 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	843
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	844 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	845 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	846 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	847
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	848 // AMR trace
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	849 #define C_AMR_TRACE_ID 55
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	850
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	851 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	852 /* d_error_status */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	853 /-------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	854
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	855 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	856 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	857
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	858 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	859 #define DSP_DEBUG_GSM_MASK 0x08BD
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	860 #define DSP_DEBUG_GPRS_MASK 0x0f3d
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	861 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	862 #endif // DSP
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	863
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	864 /------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	865 /* Default value */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	866 /------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	867 #ifndef W_A_DSP1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	868 #define W_A_DSP1 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	869 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	870
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	871 #ifndef DATA14_4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	872 #define DATA14_4 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	873 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	874
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	875 #ifndef W_A_ITFORCE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	876 #define W_A_ITFORCE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	877 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	878
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	879 #ifndef W_A_DSP_IDLE3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	880 #define W_A_DSP_IDLE3 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	881 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	882
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	883 #ifndef L1_NEW_AEC
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	884 #define L1_NEW_AEC 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	885 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	886
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	887 #ifndef DSP_DEBUG_TRACE_ENABLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	888 #define DSP_DEBUG_TRACE_ENABLE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	889 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	890
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	891 #ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	892 #define DEBUG_DEDIC_TCH_BLOCK_STAT 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	893 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	894
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	895 #ifndef D_ERROR_STATUS_TRACE_ENABLE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	896 #define D_ERROR_STATUS_TRACE_ENABLE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	897 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	898
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	899 #ifndef L1_GTT
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	900 #define L1_GTT 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	901 #define TTY_SYNC_MCU 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	902 #define TTY_SYNC_MCU_2 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	903 #define L1_GTT_FIFO_TEST_ATOMIC 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	904 #define NEW_WKA_PATCH 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	905 #define OPTIMISED 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	906 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	907
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	908 #ifndef L1_AMR_NSYNC
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	909 #define L1_AMR_NSYNC 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	910 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	911
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	912 #ifndef FF_L1_TCH_VOCODER_CONTROL
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	913 #define FF_L1_TCH_VOCODER_CONTROL 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	914 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	915 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	916
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	917 /------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	918 /* Download */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	919 /------------------------------------/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	920
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	921
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	922 /* Possible values for the download status */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	923
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	924 #define LEAD_READY 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	925 #define BLOCK_READY 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	926 #define PROGRAM_DONE 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	927 #define PAGE_SELECTION 4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	928
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	929
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	930 /************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	931 /* Options of compilation... */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	932 /************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	933
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	934 // Possible choice of hardware plateform.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	935 #define GEMINI 1 // GEMINI chip (rom dsp code)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	936 #define POLESTAR 2 // POLESTAR chip (no rom)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	937
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	938 // Possible choice for DSP software setup.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	939 #define NO_DWNLD 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	940 #define PATCH_DWNLD 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	941 #define DSP_DWNLD 2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	942 #define PATCH_DSP_DWNLD 3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	943
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	944 // MAC-S status reporting to Layer 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	945 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	946
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	947
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	948 // Possible choice for dll_dcch_downlink interface (with FN or without FN)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	949 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	950
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	951 //---------------------------------------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	952
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	953 // Neighbor Cell RXLEV indication
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	954 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	955 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	956 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	957 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	958 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	959
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	960 #endif /* __L1_CONFG_H__ */

FreeCalypso > hg > fc-tourmaline

annotate src/cs/layer1/include/l1_confg.h @ 303:f76436d19a7a default tip