FreeCalypso > hg > fc-tourmaline

annotate src/cs/layer1/tpu_drivers/source/tpudrv.h @ 303:f76436d19a7a default tip

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!GPRS config: fix long-standing AT+COPS chance hanging bug There has been a long-standing bug in FreeCalypso going back years: sometimes in the AT command bring-up sequence of an ACI-only MS, the AT+COPS command would produce only a power scan followed by cessation of protocol stack activity (only L1 ADC traces), instead of the expected network search sequence. This behaviour was seen in different FC firmware versions going back to Citrine, and seemed to follow some law of chance, not reliably repeatable. This bug has been tracked down and found to be specific to !GPRS configuration, stemming from our TCS2/TCS3 hybrid and reconstruction of !GPRS support that was bitrotten in TCS3.2/LoCosto version. ACI module psa_mms.c, needed only for !GPRS, was missing in the TCS3 version and had to be pulled from TCS2 - but as it turns out, there is a new field in the MMR_REG_REQ primitive that needs to be set correctly, and that psa_mms.c module is the place where this initialization needed to be added.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 08 Jun 2023 08:23:37 +0000
parents 4e78acac3d88
children
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4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 /************* Revision Controle System Header *************
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 * GSM Layer 1 software
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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3 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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4 * Filename tpudrv.h
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5 * Copyright 2003 (C) Texas Instruments
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 *
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 ************* Revision Controle System Header *************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 * Device addresses - GCS000
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 // GSM 1.5 : TPU / TSP addresses
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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13 //-------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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14
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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15 #if ((CHIPSET ==2) || (CHIPSET == 3) || (CHIPSET == 4))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 #define TPU_ADDR 0xFFFE0000l // Hercule / Ulysse / Samson
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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17
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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18 #define TPU_RAM (TPU_ADDR + 0x1400)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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19
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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20 #define TPU_REG (TPU_ADDR + 0x1000)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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21 #define TSP_REG (TPU_ADDR + 0x0800)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 #define TPU_TIM (TPU_ADDR + 0x2000)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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23
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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24 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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25 #define TPU_ADDR 0xFFFF0000l // Strobe 1 address
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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26
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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27 #define TPU_RAM 0xFFFF9000l // TPU RAM
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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28
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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29 #define TPU_REG (TPU_ADDR + 0x1000) // TPU register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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30 #define TSP_REG 0xFFFE0800l // TSP register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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31 #define TPU_TIM 0xFFFE2000l // ULPD register
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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32
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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33 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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34
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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35
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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36 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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37 * Macros for defining TPU instructions
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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38 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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39 #define TPU_SLEEP 0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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40 #define TPU_MOVE(addr,data) (0x8000 | ((data)<<5) | (addr))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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41 #define TPU_AT(time) (0x2000 | (((time + 5000) % 5000)))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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42 #define TPU_FAT(time) (0x2000 | (time)) // Fast version without modulo
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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43 #define TPU_SYNC(time) (0x6000 | (time))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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44 #define TPU_WAIT(time) (0xA000 | (time))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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45 #define TPU_OFFSET(time) (0x4000 | (time))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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46 #define MOD5000(a) (((a) + 5000) % 5000)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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47
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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48
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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49 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50 * TSP registers - defined in GCS004 - Time Serial Port
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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51 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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52 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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53 * in TPU address space
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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54 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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55 // GSM 1.5 : TSP_TX_REG_1/2/3/4 instead of TSP_TX_U/M/L
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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56 // added TSP_SPI_SET1/2/3 to ctrl up to 5 periph.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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57 //-----------------------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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58 #define TSP_CTRL1 0x00
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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59 #define TSP_CTRL2 0x01
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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60 #define TSP_TX_REG_1 0x04
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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61 #define TSP_TX_REG_2 0x03
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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62 #define TSP_TX_REG_3 0x02
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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63 #define TSP_TX_REG_4 0x05
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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64 #define TSP_ACT 0x06
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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65 #define TSP_ACTX 0x07
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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66 #define TSP_GAUGING_EN 0x11
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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67 #define TSP_SPI_SET1 0x09
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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68 #define TSP_SPI_SET2 0x0A
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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69 #define TSP_SPI_SET3 0x0B
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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70 #define TPU_IT_DSP_PG 0x10
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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71 #define TSP_GAUGING_EN 0x11
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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72
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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73 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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74 * in ARM address space - defined in HYP004
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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75 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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76 #define TSP_RX_LSB (TSP_REG + 0x00)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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77
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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78 #define TSP_RX_MSB (TSP_REG + 0x02)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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79
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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80 #define TSP_TX_LSB (TSP_REG + 0x0c)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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81
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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82 #define TSP_TX_MSB (TSP_REG + 0x0a)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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83
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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84
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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85 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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86 * TSP registers bit definitions
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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87 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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88 #define TC1_DEVICE0 0x00
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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89 #define TC1_DEVICE1 0x20
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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90 #define TC1_DEVICE2 0x40
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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91 #define TC1_DEVICE3 0x60
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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92 #define TC1_DEVICE4 0x80
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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93 #define TC2_RD 0x01
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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94 #define TC2_WR 0x02
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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95 #define TC2_EDGE_TRIG 0x40
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
96 #define TC2_RISING 0x80
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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97 #define TSP_CLK_RISE 0x01
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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98 #define TSP_ENA_POS 0x02
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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99 #define TSP_ENA_EDGE 0x04
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
100 #define GAUGING_START 0x01
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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101 #define GAUGING_STOP 0x00
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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102 #define TSP_ENA_POS_MSB 0x20
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
103
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
104
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
105
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
106 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
107 * TPU registers - defined in HYP002
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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108 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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109 // GSM 1.5 : TPU reg are 16-bit access
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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110 //---------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
111 #define TPU_CTRL (TPU_REG + 0x00)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
112 #define TPU_INT_CTRL (TPU_REG + 0x02)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 #define TPU_INT_STAT (TPU_REG + 0x04)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 #define TPU_OFFSET_REG (TPU_REG + 0x0C)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
115 #define TPU_SYNCHRO_REG (TPU_REG + 0x0E)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116 #define TPU_DSP_PG (TPU_REG + 0x20)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
117
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
118
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
120
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
121
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
122 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
123 * TPU control register bits
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
124 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
125 // GSM 1.5 : TPU bits changed
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
126 //---------------------------------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
127 #define TPU_CTRL_RESET 0x0001
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 #define TSP_CTRL_RESET 0x0080
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
129 #define TPU_CTRL_T_PAGE 0x0002
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
130 #define TPU_CTRL_T_ENBL 0x0004
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
131 #define TPU_CTRL_D_ENBL 0x0010 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 #define TPU_CTRL_SPI_RST 0x0080
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 #define TPU_CTRL_WAIT 0x0200
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 #define TPU_CTRL_CLK_EN 0x0400
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 #define TPU_CTRL_FULL_WRITE 0x0800
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 * TPU interrupt control register bits
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 /* WARNING BUG IN HYPERION. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 /* READING TPU_INT_CRTL, TPU_INT_ITP_M BIT CONTENTS AFFECTS THE TPU_INT_ITD_M VALUE. */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 #define TPU_INT_ITF_M 0x0001
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 #define TPU_INT_ITP_M 0x0002
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 #define TPU_INT_ITD_M 0x0004
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 #define TPU_INT_ITD_F 0x0008 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 #define INT_FRAME 4 /* TPU frame interrupt */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 #define INT_PAGE 5 /* TPU page interrupt */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 #define INT_TSP 3 /* TSP interrupt */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 // BB signals connected to serial link1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 #define BULON 0x80 // bit6
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 #define BULCAL 0x40 // bit5
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 #define BULENA 0x20 // bit4
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 #define BDLON 0x10 // bit3
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 #define BDLCAL 0x08 // bit2
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 #define BDLENA 0x04 // bit1
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 #define STARTADC 0x02 // bit0
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 * GSM RF programming times in quarter bits
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 /**************************************************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 /**************************************************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 /****************************** W A R N I N G !!! *************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 /******* This values are fine tuned for LAYER 1 . DO NOT MODIFY !!! *******/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 /****** FOR ANY MODIFICATION , PLEASE CONTACT Texas Instruments Inc. ******/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 /**************************************************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 /**************************************************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 /**************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 /* TPU Macros: prototypes functions */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 /**************************************/
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 // TPU macros.
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 //------------
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 void l1dmacro_reset_hw (UWORD32 servingCellOffset);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 void l1dmacro_init_hw (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 void l1dmacro_init_hw_light (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 void l1dmacro_idle (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 void l1dmacro_rx_synth (SYS_UWORD16 radio_freq);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 void l1dmacro_tx_synth (SYS_UWORD16 radio_freq);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 void l1dmacro_agc (SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 void l1dmacro_afc (SYS_UWORD16 afc_value, UWORD8 win_id);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 void l1dmacro_rx_ms (SYS_UWORD16 radio_freq);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 void l1dmacro_rx_fb (SYS_UWORD16 radio_freq);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 void l1dmacro_offset (UWORD32 offset_value,
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 WORD32 relative_time);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 void l1dmacro_synchro (UWORD32 when, UWORD32 value);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 void l1dmacro_rx_sb (SYS_UWORD16 radio_freq);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 void l1dmacro_tx_nb (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 void l1dmacro_tx_ra (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 void l1dmacro_adc_read_tx (UWORD32 when);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 void l1dmacro_adc_read_rx (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 void l1dmacro_set_frame_it (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 void l1pdmacro_it_dsp_gen(WORD16 time);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 #if TESTMODE
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 void l1dmacro_stop_cont (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 * TPU prototypes
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 void TP_PageIntHandler (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 void TP_FrameIntHandler (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 void TP_PageIntHandler (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 void TP_FrameIntHandler (void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 void TPU_Reset(SYS_UWORD16 on);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 void TSP_Reset(SYS_UWORD16 on);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 void TPU_ClkEnable(SYS_UWORD16 on);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 void TP_Reset(SYS_UWORD16 on);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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231 void TP_Enable(SYS_UWORD16 on);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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232 BOOL TPU_check_IT_DSP(void);
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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233
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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234
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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235 /*
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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236 * TPUDRV global variables
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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237 */
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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238 #ifdef TPUDRV_C
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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239 #define TP_GLOBAL
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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240 #else
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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241 #define TP_GLOBAL extern
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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242 #endif
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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243
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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244 TP_GLOBAL volatile UWORD32 TP_PageInt;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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245 TP_GLOBAL volatile UWORD32 TP_FrameInt;
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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246
4e78acac3d88 src/{condat,cs,gpf,nucleus}: import from Selenite
Mychaela Falconia <falcon@freecalypso.org>
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247