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src/{condat,cs,gpf,nucleus}: import from Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 16 Oct 2020 06:23:26 +0000
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-1:000000000000 0:4e78acac3d88
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_DEFTY.H
4 *
5 * Filename l1_defty.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9 #if(L1_DYN_DSP_DWNLD == 1)
10 #include "l1_dyn_dwl_defty.h"
11 #endif
12
13 typedef struct
14 {
15 UWORD16 modulus;
16 UWORD16 relative_position;
17 }
18 T_BCCHS_SCHEDULE;
19
20 typedef struct
21 {
22 UWORD8 schedule_array_size;
23 T_BCCHS_SCHEDULE schedule_array[10];
24 }
25 T_BCCHS;
26
27 typedef struct
28 {
29 BOOL status;
30 UWORD16 radio_freq;
31 UWORD32 fn_offset;
32 UWORD32 time_alignmt;
33 UWORD8 sb26_attempt;
34 UWORD8 tsc;
35 UWORD16 bcch_blks_req;
36 UWORD8 timing_validity;
37 UWORD8 search_mode;
38 UWORD8 gprs_priority;
39 UWORD8 sb26_offset; // Set to 1 when SB26 RX win is entirely in frame 25.
40 #if (L1_12NEIGH ==1)
41 UWORD32 fn_offset_mem;
42 UWORD32 time_alignmt_mem;
43 #endif
44 }
45 T_NCELL_SINGLE;
46
47 typedef struct
48 {
49 UWORD8 active_neigh_id_norm;
50 UWORD8 active_neigh_tc_norm;
51 UWORD8 active_neigh_id_top;
52 UWORD8 active_neigh_tc_top;
53 UWORD8 current_list_size;
54 T_NCELL_SINGLE list[6];
55 }
56 T_BCCHN_LIST;
57
58 typedef struct
59 {
60 UWORD8 active_fb_id;
61 UWORD8 active_sbconf_id;
62 UWORD8 active_sb_id;
63 UWORD8 current_list_size;
64 UWORD8 first_in_list; //point at oldest element in list. Used when parsing the list.
65 #if (L1_EOTD==1)
66 #if L1_EOTD_QBIT_ACC
67 // Store serving fn_offset and time_alignmt, so that they can be tracked
68 // independently.
69 UWORD32 serv_fn_offset;
70 UWORD32 serv_time_alignmt;
71 #endif
72 // Need to track any TOA updates in dedicated mode else
73 // QB errors are introduced in the results...
74
75 UWORD8 eotd_toa_phase;
76 WORD32 eotd_toa_tracking;
77 WORD32 eotd_cache_toa_tracking;
78
79 UWORD8 eotd_meas_session;
80 UWORD32 fn_sb_serv; // for methods 1 & 2
81 UWORD32 ta_sb_serv; // for methods 1 & 2
82 WORD32 teotdS; // for method 2 only
83 UWORD32 fn_offset_serv; // for method 2 only
84 #endif
85 #if (L1_12NEIGH==1)
86 T_NCELL_SINGLE list[NBR_NEIGHBOURS+1]; // 1 place (13th) for S.C in EOTD.
87 #else
88 T_NCELL_SINGLE list[6];
89 #endif
90 }
91 T_NSYNC_LIST;
92
93 typedef struct
94 {
95 UWORD8 cbch_state;
96 UWORD32 starting_fn;
97 UWORD32 first_block[48];
98 UWORD8 cbch_num;
99 UWORD8 schedule_length;
100 UWORD8 next;
101 WORD32 start_continuous_fn;
102 }
103 T_CBCH_HEAD_SCHEDULE;
104
105 typedef struct
106 {
107 UWORD8 cbch_num;
108 UWORD8 next;
109 UWORD32 start_fn[6];
110 }
111 T_CBCH_INFO_SCHEDULE;
112
113 /*=========================================================================*/
114 /* Moved type definitions from Debis files. */
115 /*=========================================================================*/
116 #if (AMR == 1)
117 // AMR ver 1.0 parameters
118 typedef struct
119 {
120 BOOL noise_suppression_bit;
121 BOOL initial_codec_mode_indicator;
122 UWORD8 initial_codec_mode;
123 UWORD8 active_codec_set;
124 UWORD8 threshold[3];
125 UWORD8 hysteresis[3];
126 }
127 T_AMR_CONFIGURATION;
128 #endif
129
130 typedef struct
131 {
132 UWORD8 A[7+1];
133 }
134 T_ENCRYPTION_KEY;
135
136 typedef struct
137 {
138 UWORD8 A[22+1];
139 }
140 T_RADIO_FRAME;
141
142 typedef struct
143 {
144 UWORD8 n32;
145 UWORD8 n51;
146 UWORD8 n26;
147 }
148 T_SHORT_FRAME_NUMBER;
149
150 typedef struct
151 {
152 UWORD16 A[31+1];
153 }
154 T_CHAN_LIST;
155
156 typedef struct
157 {
158 UWORD16 num_of_chans;
159 T_CHAN_LIST chan_number;
160 }
161 T_BCCH_LIST;
162
163 typedef struct
164 {
165 UWORD16 rf_chan_num;
166 UWORD8 l2_channel_type;
167 UWORD8 error_cause;
168 T_RADIO_FRAME l2_frame;
169 UWORD8 bsic;
170 UWORD8 tc;
171 }
172 T_PH_DATA_IND;
173
174 typedef struct
175 {
176 UWORD16 A[63+1];
177 }
178 T_MA_FIELD;
179
180 typedef struct
181 {
182 UWORD16 rf_chan_cnt;
183 T_MA_FIELD rf_chan_no;
184 }
185 T_MOBILE_ALLOCATION;
186
187 typedef struct
188 {
189 BOOL start_time_present;
190 T_SHORT_FRAME_NUMBER start_time;
191 }
192 T_STARTING_TIME;
193
194 typedef struct
195 {
196 UWORD16 radio_freq_no;
197 WORD8 rxlev;
198 }
199 T_RXLEV_MEAS;
200
201 typedef struct
202 {
203 UWORD8 maio;
204 UWORD8 hsn;
205 }
206 T_HOPPING_RF;
207
208 typedef struct
209 {
210 UWORD16 radio_freq;
211 }
212 T_SINGLE_RF;
213
214 typedef union
215 {
216 T_SINGLE_RF single_rf;
217 T_HOPPING_RF hopping_rf;
218 }
219 T_CHN_SEL_CHOICE;
220
221 typedef struct
222 {
223 BOOL h;
224 T_CHN_SEL_CHOICE rf_channel;
225 }
226 T_CHN_SEL;
227
228 typedef struct
229 {
230 T_CHN_SEL chan_sel;
231 UWORD8 channel_type;
232 UWORD8 subchannel;
233 UWORD8 timeslot_no;
234 UWORD8 tsc;
235 }
236 T_CHANNEL_DESCRIPTION;
237
238 typedef struct
239 {
240 UWORD8 ncc;
241 UWORD8 bcc;
242 UWORD16 bcch_carrier;
243 }
244 T_CELL_DESC;
245
246 typedef struct
247 {
248 T_CELL_DESC cell_description;
249 T_CHANNEL_DESCRIPTION channel_desc_1;
250 UWORD8 channel_mode_1;
251 T_STARTING_TIME starting_time;
252 UWORD8 ho_acc;
253 UWORD8 txpwr;
254 BOOL report_time_diff;
255 T_MOBILE_ALLOCATION frequency_list;
256 T_CHANNEL_DESCRIPTION channel_desc_2;
257 UWORD8 channel_mode_2;
258 T_MOBILE_ALLOCATION frequency_list_bef_sti;
259 T_CHANNEL_DESCRIPTION channel_desc_1_bef_sti;
260 T_CHANNEL_DESCRIPTION channel_desc_2_bef_sti;
261 BOOL cipher_mode;
262 UWORD8 a5_algorithm;
263 }
264 T_HO_PARAMS;
265
266 typedef struct
267 {
268 T_CHANNEL_DESCRIPTION channel_desc;
269 T_MOBILE_ALLOCATION frequency_list;
270 T_STARTING_TIME starting_time;
271 }
272 T_MPHC_CHANGE_FREQUENCY;
273
274 typedef struct
275 {
276 UWORD8 subchannel;
277 UWORD8 channel_mode;
278 #if (AMR == 1)
279 T_AMR_CONFIGURATION amr_configuration;
280 #endif
281 }
282 T_MPHC_CHANNEL_MODE_MODIFY_REQ;
283
284 typedef struct
285 {
286 UWORD8 cipher_mode;
287 UWORD8 a5_algorithm;
288 T_ENCRYPTION_KEY new_ciph_param;
289 }
290 T_MPHC_SET_CIPHERING_REQ;
291
292 typedef struct
293 {
294 UWORD8 sub_channel;
295 UWORD8 frame_erasure;
296 }
297 T_OML1_CLOSE_TCH_LOOP_REQ;
298
299 typedef struct
300 {
301 #if (defined _WINDOWS && (OP_RIV_AUDIO == 1))
302 T_RV_HDR header;
303 #endif
304 UWORD8 tested_device;
305 }
306 T_OML1_START_DAI_TEST_REQ;
307
308 /***********************************************************/
309 /* Type definitions for DEBUG... */
310 /***********************************************************/
311 typedef struct // translate string in int and int in string
312 {
313 CHAR *message;
314 WORD32 SignalCode;
315 WORD32 size;
316 }
317 MSG_DEBUG;
318
319 typedef struct // translate string in int and int in string
320 {
321 CHAR *name;
322 }
323 TASK_TRACE;
324
325 /***********************************************************/
326 /* Type definitions for data structures used for MFTAB */
327 /* managment... */
328 /***********************************************************/
329 typedef struct
330 {
331 void (*fct_ptr)(UWORD8,UWORD8);
332 CHAR param1;
333 CHAR param2;
334 }
335 T_FCT;
336
337 typedef struct
338 {
339 T_FCT fct[L1_MAX_FCT];
340 }
341 T_FRM;
342
343 typedef struct
344 {
345 T_FRM frmlst[MFTAB_SIZE];
346 }
347 T_MFTAB;
348
349 typedef struct
350 {
351 const T_FCT *address;
352 UWORD8 size;
353 }
354 T_TASK_MFTAB;
355
356 /***********************************************************/
357 /* TPU controle register components definition. */
358 /***********************************************************/
359
360 #if (CODE_VERSION==SIMULATION)
361 typedef struct // contents of REG_CMD register
362 {
363 unsigned int tpu_reset_bit : 1; // TPU_RESET bit : ON (reset TPU)
364 unsigned int tpu_pag_bit : 1; // TPU_PAG bit : 0 (page 0)
365 unsigned int tpu_enb_bit : 1; // TPU_ENB bit : ON (TPU commun.int.)
366 unsigned int dsp_pag_bit : 1; // DSP_PAG bit : 0 (page 0)
367 unsigned int dsp_enb_bit : 1; // DSP_ENB bit : ON (DSP commun.int.)
368 unsigned int tpu_stat_bit : 1; // TPU_STAT bit : ON (if TPU active) OFF (if TPU in IDLE)
369 unsigned int tpu_idle_bit : 1; // TPU_IDLE bit : ON (force IDLE mode)
370 }
371 T_reg_cmd; // Rem: we must keep "unsigned int" type for bitmap.
372 #else
373 typedef struct // contents of REG_CMD register
374 {
375 unsigned int tpu_reset_bit : 1; // TPU_RESET bit : ON (reset TPU)
376 unsigned int tpu_pag_bit : 1; // TPU_PAG bit : 0 (page 0)
377 unsigned int tpu_enb_bit : 1; // TPU_ENB bit : ON (TPU commun.int.)
378 unsigned int unused_1 : 1; //
379 unsigned int dsp_enb_bit : 1; // DSP_ENB bit : ON (DSP commun.int.)
380 unsigned int unused_2 : 1; //
381 unsigned int unused_3 : 1; //
382 unsigned int tsp_reset_bit : 1; // TSP_RESET bit : ON (reset TSP)
383 unsigned int tpu_idle_bit : 1; // TPU_IDLE bit : ON (force IDLE mode)
384 unsigned int tup_wait_bit : 1; // TPU_WAIT bit : ON (TPU ready)
385 unsigned int tpu_ck_enb_bit: 1; // TPU_CLK bit : ON (TPU clock on)
386 }
387 T_reg_cmd;
388 #endif
389 /***********************************************************/
390 /* */
391 /* Data structure for global info components. */
392 /* */
393 /***********************************************************/
394
395 typedef struct
396 {
397 API d_task_d; // (0) Downlink task command.
398 API d_burst_d; // (1) Downlink burst identifier.
399 API d_task_u; // (2) Uplink task command.
400 API d_burst_u; // (3) Uplink burst identifier.
401 API d_task_md; // (4) Downlink Monitoring (FB/SB) command.
402 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
403 API d_background; // (5) Background tasks
404 #else
405 API d_reserved; // (5) Reserved
406 #endif
407 API d_debug; // (6) Debug/Acknowledge/general purpose word.
408 API d_task_ra; // (7) RA task command.
409 API d_fn; // (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only.
410 // bit [0..7] -> b_fn_report, FN in the normalized reporting period.
411 // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning.
412 API d_ctrl_tch; // (9) Tch channel description.
413 // bit [0..3] -> b_chan_mode, channel mode.
414 // bit [4..5] -> b_chan_type, channel type.
415 // bit [6] -> reset SACCH
416 // bit [7] -> vocoder ON
417 // bit [8] -> b_sync_tch_ul, synchro. TCH/UL.
418 // bit [9] -> b_sync_tch_dl, synchro. TCH/DL.
419 // bit [10] -> b_stop_tch_ul, stop TCH/UL.
420 // bit [11] -> b_stop_tch_dl, stop TCH/DL.
421 // bit [12.13] -> b_tch_loop, tch loops A/B/C.
422 API hole; // (10) unused hole.
423
424 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
425 API d_ctrl_abb; // (11) Bit field indicating the analog baseband register to send.
426 // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB
427 // bit [1.2] -> unused
428 // bit [3] -> b_apcdel: delays-register in NDB
429 // bit [4] -> b_afc: freq control register in DB
430 // bit [5..15] -> unused
431 #endif
432 API a_a5fn[2]; // (12..13) Encryption Frame number.
433 // word 0, bit [0..4] -> T2.
434 // word 0, bit [5..10] -> T3.
435 // word 1, bit [0..11] -> T1.
436 API d_power_ctl; // (14) Power level control.
437 API d_afc; // (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb").
438 API d_ctrl_system; // (16) Controle Register for RESET/RESUME.
439 // bit [0..2] -> b_tsq, training sequence.
440 // bit [3] -> b_bcch_freq_ind, BCCH frequency indication.
441 // bit [15] -> b_task_abort, DSP task abort command.
442 }
443 T_DB_MCU_TO_DSP;
444
445 typedef struct
446 {
447 API d_task_d; // (0) Downlink task command.
448 API d_burst_d; // (1) Downlink burst identifier.
449 API d_task_u; // (2) Uplink task command.
450 API d_burst_u; // (3) Uplink burst identifier.
451 API d_task_md; // (4) Downlink Monitoring (FB/SB) task command.
452 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
453 API d_background; // (5) Background tasks
454 #else
455 API d_reserved; // (5) Reserved
456 #endif
457 API d_debug; // (6) Debug/Acknowledge/general purpose word.
458 API d_task_ra; // (7) RA task command.
459
460 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
461 API a_serv_demod[4]; // ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
462 API a_pm[3]; // (12..14) Power measurement results, array of 3 words.
463 API a_sch[5]; // (15..19) Header + SB information, array of 5 words.
464 #else
465 API a_pm[3]; // ( 8..10) Power measurement results, array of 3 words.
466 API a_serv_demod[4]; // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
467 API a_sch[5]; // (15..19) Header + SB information, array of 5 words.
468 #endif
469 }
470 T_DB_DSP_TO_MCU;
471
472 #if (DSP == 34) || (DSP == 35) || (DSP == 36) // NDB GSM
473 typedef struct
474 {
475 // MISC Tasks
476 API d_dsp_page;
477
478 // DSP status returned (DSP --> MCU).
479 API d_error_status;
480
481 // RIF control (MCU -> DSP).
482 API d_spcx_rif;
483
484 API d_tch_mode; // TCH mode register.
485 // bit [0..1] -> b_dai_mode.
486 // bit [2] -> b_dtx.
487
488 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
489
490 API d_dsp_test;
491
492 // Words dedicated to Software version (DSP code + Patch)
493 API d_version_number1;
494 API d_version_number2;
495
496 API d_debug_ptr;
497 API d_debug_bk;
498
499 API d_pll_config;
500
501 // GSM/GPRS DSP Debug trace support
502 API p_debug_buffer;
503 API d_debug_buffer_size;
504 API d_debug_trace_type;
505
506 #if (W_A_DSP_IDLE3 == 1)
507 // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
508 API d_dsp_state;
509 // 5 words are reserved for any possible mapping modification
510 API d_hole1_ndb[2];
511 #else
512 // 6 words are reserved for any possible mapping modification
513 API d_hole1_ndb[3];
514 #endif
515
516 #if (AMR == 1)
517 API p_debug_amr;
518 #else
519 API d_hole_debug_amr;
520 #endif
521
522 #if (CHIPSET == 12)
523 #if (DSP == 35) || (DSP == 36)
524 API d_hole2_ndb[1];
525 API d_mcsi_select;
526 #else
527 API d_hole2_ndb[2];
528 #endif
529 #else
530 API d_hole2_ndb[2];
531 #endif
532
533 // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
534 API d_apcdel1_bis;
535 API d_apcdel2_bis;
536
537
538 // New registers due to IOTA analog base band
539 API d_apcdel2;
540 API d_vbctrl2;
541 API d_bulgcal;
542
543 // Analog Based Band
544 API d_afcctladd;
545
546 API d_vbuctrl;
547 API d_vbdctrl;
548 API d_apcdel1;
549 API d_apcoff;
550 API d_bulioff;
551 API d_bulqoff;
552 API d_dai_onoff;
553 API d_auxdac;
554
555 #if (ANLG_FAM == 1)
556 API d_vbctrl;
557 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
558 API d_vbctrl1;
559 #endif
560
561 API d_bbctrl;
562
563 // Monitoring tasks control (MCU <- DSP)
564 // FB task
565 API d_fb_det; // FB detection result. (1 for FOUND).
566 API d_fb_mode; // Mode for FB detection algorithm.
567 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
568
569 // SB Task
570 API a_sch26[5]; // Header + SB information, array of 5 words.
571
572 API d_audio_gain_ul;
573 API d_audio_gain_dl;
574
575 // Controller of the melody E2 audio compressor
576 API d_audio_compressor_ctrl;
577
578 // AUDIO module
579 API d_audio_init;
580 API d_audio_status;
581
582 // Audio tasks
583 // TONES (MCU -> DSP)
584 API d_toneskb_init;
585 API d_toneskb_status;
586 API d_k_x1_t0;
587 API d_k_x1_t1;
588 API d_k_x1_t2;
589 API d_pe_rep;
590 API d_pe_off;
591 API d_se_off;
592 API d_bu_off;
593 API d_t0_on;
594 API d_t0_off;
595 API d_t1_on;
596 API d_t1_off;
597 API d_t2_on;
598 API d_t2_off;
599 API d_k_x1_kt0;
600 API d_k_x1_kt1;
601 API d_dur_kb;
602 API d_shiftdl;
603 API d_shiftul;
604
605 API d_aec_ctrl;
606
607 API d_es_level_api;
608 API d_mu_api;
609
610 // Melody Ringer module
611 API d_melo_osc_used;
612 API d_melo_osc_active;
613 API a_melo_note0[4];
614 API a_melo_note1[4];
615 API a_melo_note2[4];
616 API a_melo_note3[4];
617 API a_melo_note4[4];
618 API a_melo_note5[4];
619 API a_melo_note6[4];
620 API a_melo_note7[4];
621
622 // selection of the melody format
623 API d_melody_selection;
624
625 // Holes due to the format melody E1
626 API a_melo_holes[3];
627
628 // Speech Recognition module
629 API d_sr_status; // status of the DSP speech reco task
630 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
631 API d_sr_bit_exact_test; // bit exact test
632 API d_sr_nb_words; // number of words used in the speech recognition task
633 API d_sr_db_level; // estimate voice level in dB
634 API d_sr_db_noise; // estimate noise in dB
635 API d_sr_mod_size; // size of the model
636 API a_n_best_words[4]; // array of the 4 best words
637 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
638
639 // Audio buffer
640 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
641 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
642
643 // V42bis module
644 API d_v42b_nego0;
645 API d_v42b_nego1;
646 API d_v42b_control;
647 API d_v42b_ratio_ind;
648 API d_mcu_control;
649 API d_mcu_control_sema;
650
651 // Background tasks
652 API d_background_enable;
653 API d_background_abort;
654 API d_background_state;
655 API d_max_background;
656 API a_background_tasks[16];
657 API a_back_task_io[16];
658
659 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
660 API d_gea_mode_ovly;
661 API a_gea_kc_ovly[4];
662
663 #if (ANLG_FAM == 3)
664 // SYREN specific registers
665 API d_vbpop;
666 API d_vau_delay_init;
667 API d_vaud_cfg;
668 API d_vauo_onoff;
669 API d_vaus_vol;
670 API d_vaud_pll;
671 API d_hole3_ndb[1];
672 #elif ((ANLG_FAM == 1) || (ANLG_FAM == 2))
673
674 API d_hole3_ndb[7];
675
676 #endif
677
678 // word used for the init of USF threshold
679 API d_thr_usf_detect;
680
681 // Encryption module
682 API d_a5mode; // Encryption Mode.
683
684 API d_sched_mode_gprs_ovly;
685
686 // 7 words are reserved for any possible mapping modification
687 API d_hole4_ndb[5];
688
689 // Ramp definition for Omega device
690 API a_ramp[16];
691
692 // CCCH/SACCH downlink information...(!!)
693 API a_cd[15]; // Header + CCCH/SACCH downlink information.
694
695 // FACCH downlink information........(!!)
696 API a_fd[15]; // Header + FACCH downlink information.
697
698 // Traffic downlink data frames......(!!)
699 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
700
701 // CCCH/SACCH uplink information.....(!!)
702 API a_cu[15]; // Header + CCCH/SACCH uplink information.
703
704 // FACCH downlink information........(!!)
705 API a_fu[15]; // Header + FACCH uplink information
706
707 // Traffic downlink data frames......(!!)
708 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
709
710 // Random access.....................(MCU -> DSP).
711 API d_rach; // RACH information.
712
713 //...................................(MCU -> DSP).
714 API a_kc[4]; // Encryption Key Code.
715
716 // Integrated Data Services module
717 API d_ra_conf;
718 API d_ra_act;
719 API d_ra_test;
720 API d_ra_statu;
721 API d_ra_statd;
722 API d_fax;
723 API a_data_buf_ul[21];
724 API a_data_buf_dl[37];
725
726 // GTT API mapping for DSP code 34 (for test only)
727 #if (L1_GTT == 1)
728 API d_tty_status;
729 API d_tty_detect_thres;
730 API d_ctm_detect_shift;
731 API d_tty_fa_thres;
732 API d_tty_mod_norm;
733 API d_tty_reset_buffer_ul;
734 API d_tty_loop_ctrl;
735 API p_tty_loop_buffer;
736 #else
737 API a_tty_holes[8];
738 #endif
739
740 API a_sr_holes0[414];
741
742 #if (L1_NEW_AEC)
743 // new AEC
744 API d_cont_filter;
745 API d_granularity_att;
746 API d_coef_smooth;
747 API d_es_level_max;
748 API d_fact_vad;
749 API d_thrs_abs;
750 API d_fact_asd_fil;
751 API d_fact_asd_mut;
752 API d_far_end_pow_h;
753 API d_far_end_pow_l;
754 API d_far_end_noise_h;
755 API d_far_end_noise_l;
756 #else
757 API a_new_aec_holes[12];
758 #endif // L1_NEW_AEC
759
760 // Speech recognition model
761 API a_sr_holes1[145];
762 API d_cport_init;
763 API d_cport_ctrl;
764 API a_cport_cfr[2];
765 API d_cport_tcl_tadt;
766 API d_cport_tdat;
767 API d_cport_tvs;
768 API d_cport_status;
769 API d_cport_reg_value;
770
771 API a_cport_holes[1011];
772
773 API a_model[1041];
774
775 // EOTD buffer
776 #if (L1_EOTD==1)
777 API d_eotd_first;
778 API d_eotd_max;
779 API d_eotd_nrj_high;
780 API d_eotd_nrj_low;
781 API a_eotd_crosscor[18];
782 #else
783 API a_eotd_holes[22];
784 #endif
785 // AMR ver 1.0 buffers
786 API a_amr_config[4];
787 API a_ratscch_ul[6];
788 API a_ratscch_dl[6];
789 API d_amr_snr_est; // estimation of the SNR of the AMR speech block
790 #if (L1_VOICE_MEMO_AMR)
791 API d_amms_ul_voc;
792 #else
793 API a_voice_memo_amr_holes[1];
794 #endif
795 API d_thr_onset_afs; // thresh detection ONSET AFS
796 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
797 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS
798 API d_thr_update_afs; // thresh detection SID_UPDATE AFS
799 API d_thr_onset_ahs; // thresh detection ONSET AHS
800 API d_thr_sid_ahs; // thresh detection SID frames AHS
801 API d_thr_ratscch_marker;// thresh detection RATSCCH MARKER
802 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA
803 API d_thr_soft_bits;
804 #if (MELODY_E2)
805 API d_melody_e2_osc_stop;
806 API d_melody_e2_osc_active;
807 API d_melody_e2_semaphore;
808 API a_melody_e2_osc[16][3];
809 API d_melody_e2_globaltimefactor;
810 API a_melody_e2_instrument_ptr[8];
811 API d_melody_e2_deltatime;
812
813 #if (AMR_THRESHOLDS_WORKAROUND)
814 API a_d_macc_thr_afs[8];
815 API a_d_macc_thr_ahs[6];
816 #else
817 API a_melody_e2_holes0[14];
818 #endif
819
820 API a_melody_e2_holes1[693];
821 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
822 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
823 #else
824 API d_holes[61];
825 #if (AMR_THRESHOLDS_WORKAROUND)
826 API a_d_macc_thr_afs[8];
827 API a_d_macc_thr_ahs[6];
828 #endif
829 #endif
830
831 }
832 T_NDB_MCU_DSP;
833 #elif (DSP == 33) // NDB GSM
834 typedef struct
835 {
836 // MISC Tasks
837 API d_dsp_page;
838
839 // DSP status returned (DSP --> MCU).
840 API d_error_status;
841
842 // RIF control (MCU -> DSP).
843 API d_spcx_rif;
844
845 API d_tch_mode; // TCH mode register.
846 // bit [0..1] -> b_dai_mode.
847 // bit [2] -> b_dtx.
848
849 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
850
851 API d_dsp_test;
852
853 // Words dedicated to Software version (DSP code + Patch)
854 API d_version_number1;
855 API d_version_number2;
856
857 API d_debug_ptr;
858 API d_debug_bk;
859
860 API d_pll_config;
861
862 // GSM/GPRS DSP Debug trace support
863 API p_debug_buffer;
864 API d_debug_buffer_size;
865 API d_debug_trace_type;
866
867 #if (W_A_DSP_IDLE3 == 1)
868 // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
869 API d_dsp_state;
870 // 10 words are reserved for any possible mapping modification
871 API d_hole1_ndb[5];
872 #else
873 // 11 words are reserved for any possible mapping modification
874 API d_hole1_ndb[6];
875 #endif
876
877 // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
878 API d_apcdel1_bis;
879 API d_apcdel2_bis;
880
881
882 // New registers due to IOTA analog base band
883 API d_apcdel2;
884 API d_vbctrl2;
885 API d_bulgcal;
886
887 // Analog Based Band
888 API d_afcctladd;
889
890 API d_vbuctrl;
891 API d_vbdctrl;
892 API d_apcdel1;
893 API d_apcoff;
894 API d_bulioff;
895 API d_bulqoff;
896 API d_dai_onoff;
897 API d_auxdac;
898
899 #if (ANLG_FAM == 1)
900 API d_vbctrl;
901 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
902 API d_vbctrl1;
903 #endif
904
905 API d_bbctrl;
906
907 // Monitoring tasks control (MCU <- DSP)
908 // FB task
909 API d_fb_det; // FB detection result. (1 for FOUND).
910 API d_fb_mode; // Mode for FB detection algorithm.
911 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
912
913 // SB Task
914 API a_sch26[5]; // Header + SB information, array of 5 words.
915
916 API d_audio_gain_ul;
917 API d_audio_gain_dl;
918
919 // Controller of the melody E2 audio compressor
920 API d_audio_compressor_ctrl;
921
922 // AUDIO module
923 API d_audio_init;
924 API d_audio_status;
925
926 // Audio tasks
927 // TONES (MCU -> DSP)
928 API d_toneskb_init;
929 API d_toneskb_status;
930 API d_k_x1_t0;
931 API d_k_x1_t1;
932 API d_k_x1_t2;
933 API d_pe_rep;
934 API d_pe_off;
935 API d_se_off;
936 API d_bu_off;
937 API d_t0_on;
938 API d_t0_off;
939 API d_t1_on;
940 API d_t1_off;
941 API d_t2_on;
942 API d_t2_off;
943 API d_k_x1_kt0;
944 API d_k_x1_kt1;
945 API d_dur_kb;
946 API d_shiftdl;
947 API d_shiftul;
948
949 API d_aec_ctrl;
950
951 API d_es_level_api;
952 API d_mu_api;
953
954 // Melody Ringer module
955 API d_melo_osc_used;
956 API d_melo_osc_active;
957 API a_melo_note0[4];
958 API a_melo_note1[4];
959 API a_melo_note2[4];
960 API a_melo_note3[4];
961 API a_melo_note4[4];
962 API a_melo_note5[4];
963 API a_melo_note6[4];
964 API a_melo_note7[4];
965
966 // selection of the melody format
967 API d_melody_selection;
968
969 // Holes due to the format melody E1
970 API a_melo_holes[3];
971
972 // Speech Recognition module
973 API d_sr_status; // status of the DSP speech reco task
974 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
975 API d_sr_bit_exact_test; // bit exact test
976 API d_sr_nb_words; // number of words used in the speech recognition task
977 API d_sr_db_level; // estimate voice level in dB
978 API d_sr_db_noise; // estimate noise in dB
979 API d_sr_mod_size; // size of the model
980 API a_n_best_words[4]; // array of the 4 best words
981 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
982
983 // Audio buffer
984 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
985 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
986
987 // V42bis module
988 API d_v42b_nego0;
989 API d_v42b_nego1;
990 API d_v42b_control;
991 API d_v42b_ratio_ind;
992 API d_mcu_control;
993 API d_mcu_control_sema;
994
995 // Background tasks
996 API d_background_enable;
997 API d_background_abort;
998 API d_background_state;
999 API d_max_background;
1000 API a_background_tasks[16];
1001 API a_back_task_io[16];
1002
1003 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
1004 API d_gea_mode_ovly;
1005 API a_gea_kc_ovly[4];
1006
1007 API d_hole3_ndb[8];
1008
1009 // Encryption module
1010 API d_a5mode; // Encryption Mode.
1011
1012 API d_sched_mode_gprs_ovly;
1013
1014 // 7 words are reserved for any possible mapping modification
1015 API d_hole4_ndb[5];
1016
1017 // Ramp definition for Omega device
1018 API a_ramp[16];
1019
1020 // CCCH/SACCH downlink information...(!!)
1021 API a_cd[15]; // Header + CCCH/SACCH downlink information.
1022
1023 // FACCH downlink information........(!!)
1024 API a_fd[15]; // Header + FACCH downlink information.
1025
1026 // Traffic downlink data frames......(!!)
1027 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
1028
1029 // CCCH/SACCH uplink information.....(!!)
1030 API a_cu[15]; // Header + CCCH/SACCH uplink information.
1031
1032 // FACCH downlink information........(!!)
1033 API a_fu[15]; // Header + FACCH uplink information
1034
1035 // Traffic downlink data frames......(!!)
1036 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
1037
1038 // Random access.....................(MCU -> DSP).
1039 API d_rach; // RACH information.
1040
1041 //...................................(MCU -> DSP).
1042 API a_kc[4]; // Encryption Key Code.
1043
1044 // Integrated Data Services module
1045 API d_ra_conf;
1046 API d_ra_act;
1047 API d_ra_test;
1048 API d_ra_statu;
1049 API d_ra_statd;
1050 API d_fax;
1051 API a_data_buf_ul[21];
1052 API a_data_buf_dl[37];
1053
1054 #if (L1_NEW_AEC)
1055 // new AEC
1056 API a_new_aec_holes[422];
1057 API d_cont_filter;
1058 API d_granularity_att;
1059 API d_coef_smooth;
1060 API d_es_level_max;
1061 API d_fact_vad;
1062 API d_thrs_abs;
1063 API d_fact_asd_fil;
1064 API d_fact_asd_mut;
1065 API d_far_end_pow_h;
1066 API d_far_end_pow_l;
1067 API d_far_end_noise_h;
1068 API d_far_end_noise_l;
1069 #endif
1070
1071 // Speech recognition model
1072 #if (L1_NEW_AEC)
1073 API a_sr_holes[1165];
1074 #else
1075 API a_sr_holes[1599];
1076 #endif // L1_NEW_AEC
1077 API a_model[1041];
1078
1079 // EOTD buffer
1080 #if (L1_EOTD==1)
1081 API d_eotd_first;
1082 API d_eotd_max;
1083 API d_eotd_nrj_high;
1084 API d_eotd_nrj_low;
1085 API a_eotd_crosscor[18];
1086 #else
1087 API a_eotd_holes[22];
1088 #endif
1089
1090 #if (MELODY_E2)
1091 API a_melody_e2_holes0[27];
1092 API d_melody_e2_osc_used;
1093 API d_melody_e2_osc_active;
1094 API d_melody_e2_semaphore;
1095 API a_melody_e2_osc[16][3];
1096 API d_melody_e2_globaltimefactor;
1097 API a_melody_e2_instrument_ptr[8];
1098 API a_melody_e2_holes1[708];
1099 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
1100 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
1101 #endif
1102 }
1103 T_NDB_MCU_DSP;
1104
1105 #elif ((DSP == 32) || (DSP == 31))
1106 typedef struct
1107 {
1108 // Monitoring tasks control..........(MCU <- DSP)
1109 API d_fb_det; // FB detection result. (1 for FOUND).
1110 API d_fb_mode; // Mode for FB detection algorithm.
1111 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
1112
1113 // CCCH/SACCH downlink information...(!!)
1114 API a_cd[15]; // Header + CCCH/SACCH downlink information.
1115
1116 // FACCH downlink information........(!!)
1117 API a_fd[15]; // Header + FACCH downlink information.
1118
1119 // Traffic downlink data frames......(!!)
1120 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
1121 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
1122
1123 // CCCH/SACCH uplink information.....(!!)
1124 API a_cu[15]; // Header + CCCH/SACCH uplink information.
1125
1126 #if (SPEECH_RECO)
1127 // FACCH downlink information........(!!)
1128 API a_fu[3]; // Header + FACCH uplink information
1129 // The size of this buffer is 15 word but some speech reco words
1130 // are overlayer with this buffer. This is the reason why the size is 3 instead of 15.
1131 API d_sr_status; // status of the DSP speech reco task
1132 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
1133 API sr_hole1; // hole
1134 API d_sr_bit_exact_test; // bit exact test
1135 API d_sr_nb_words; // number of words used in the speech recognition task
1136 API d_sr_db_level; // estimate voice level in dB
1137 API d_sr_db_noise; // estimate noise in dB
1138 API d_sr_mod_size; // size of the model
1139 API sr_holes_1[4]; // hole
1140 #else
1141 // FACCH downlink information........(!!)
1142 API a_fu[15]; // Header + FACCH uplink information
1143 #endif
1144
1145 // Traffic uplink data frames........(!!)
1146 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
1147 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
1148
1149 // Random access.....................(MCU -> DSP).
1150 API d_rach; // RACH information.
1151
1152 //...................................(MCU -> DSP).
1153 API d_a5mode; // Encryption Mode.
1154 API a_kc[4]; // Encryption Key Code.
1155 API d_tch_mode; // TCH mode register.
1156 // bit [0..1] -> b_dai_mode.
1157 // bit [2] -> b_dtx.
1158
1159 // OMEGA...........................(MCU -> DSP).
1160 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
1161 API a_ramp[16];
1162 #if (MELODY_E1)
1163 API d_melo_osc_used;
1164 API d_melo_osc_active;
1165 API a_melo_note0[4];
1166 API a_melo_note1[4];
1167 API a_melo_note2[4];
1168 API a_melo_note3[4];
1169 API a_melo_note4[4];
1170 API a_melo_note5[4];
1171 API a_melo_note6[4];
1172 API a_melo_note7[4];
1173 #if (DSP==31)
1174 // selection of the melody format
1175 API d_melody_selection;
1176 API holes[9];
1177 #else // DSP==32
1178 API d_dco_type; // Tide
1179 API p_start_IQ;
1180 API d_level_off;
1181 API d_dco_dbg;
1182 API d_tide_resa;
1183 API d_asynch_margin; // Perseus Asynch Audio Workaround
1184 API hole[4];
1185 #endif // DSP 32
1186
1187 #else // NO MELODY E1
1188 #if (DSP==31)
1189 // selection of the melody format
1190 API d_melody_selection;
1191 API holes[43]; // 43 unused holes.
1192 #else // DSP==32
1193 API holes[34]; // 34 unused holes.
1194 API d_dco_type; // Tide
1195 API p_start_IQ;
1196 API d_level_off;
1197 API d_dco_dbg;
1198 API d_tide_resa;
1199 API d_asynch_margin; // Perseus Asynch Audio Workaround
1200 API hole[4];
1201 #endif //DSP == 32
1202 #endif // NO MELODY E1
1203
1204 API d_debug3;
1205 API d_debug2;
1206 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
1207 API d_afcctladd;
1208 API d_vbuctrl;
1209 API d_vbdctrl;
1210 API d_apcdel1;
1211 API d_aec_ctrl;
1212 API d_apcoff;
1213 API d_bulioff;
1214 API d_bulqoff;
1215 API d_dai_onoff;
1216 API d_auxdac;
1217
1218 #if (ANLG_FAM == 1)
1219 API d_vbctrl;
1220 #elif (ANLG_FAM == 2)
1221 API d_vbctrl1;
1222 #endif
1223
1224 API d_bbctrl;
1225 #else
1226 #error DSPCODE not supported with given ANALOG
1227 #endif //(ANALOG)1, 2
1228 //...................................(MCU -> DSP).
1229 API a_sch26[5]; // Header + SB information, array of 5 words.
1230
1231 // TONES.............................(MCU -> DSP)
1232 API d_toneskb_init;
1233 API d_toneskb_status;
1234 API d_k_x1_t0;
1235 API d_k_x1_t1;
1236 API d_k_x1_t2;
1237 API d_pe_rep;
1238 API d_pe_off;
1239 API d_se_off;
1240 API d_bu_off;
1241 API d_t0_on;
1242 API d_t0_off;
1243 API d_t1_on;
1244 API d_t1_off;
1245 API d_t2_on;
1246 API d_t2_off;
1247 API d_k_x1_kt0;
1248 API d_k_x1_kt1;
1249 API d_dur_kb;
1250
1251 // PLL...............................(MCU -> DSP).
1252 API d_pll_clkmod1;
1253 API d_pll_clkmod2;
1254
1255 // DSP status returned..........(DSP --> MCU).
1256 API d_error_status;
1257
1258 // RIF control.......................(MCU -> DSP).
1259 API d_spcx_rif;
1260
1261 API d_shiftdl;
1262 API d_shiftul;
1263
1264 API p_saec_prog;
1265 API p_aec_prog;
1266 API p_spenh_prog;
1267
1268 API a_ovly[75];
1269 API d_ra_conf;
1270 API d_ra_act;
1271 API d_ra_test;
1272 API d_ra_statu;
1273 API d_ra_statd;
1274 API d_fax;
1275 #if (SPEECH_RECO)
1276 API a_data_buf_ul[3];
1277 API a_n_best_words[4]; // array of the 4 best words
1278 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
1279 API sr_holes_2[6];
1280 API a_data_buf_dl[37];
1281
1282 API a_hole[24];
1283
1284 API d_sched_mode_gprs_ovly;
1285
1286 API fir_holes1[384];
1287 API a_fir31_uplink[31];
1288 API a_fir31_downlink[31];
1289 API d_audio_init;
1290 API d_audio_status;
1291
1292 API a_model[1041]; // array of the speech reco model
1293 #else
1294 API a_data_buf_ul[21];
1295 API a_data_buf_dl[37];
1296
1297 API a_hole[24];
1298
1299 API d_sched_mode_gprs_ovly;
1300
1301 API fir_holes1[384];
1302 API a_fir31_uplink[31];
1303 API a_fir31_downlink[31];
1304 API d_audio_init;
1305 API d_audio_status;
1306
1307 #if (L1_EOTD ==1)
1308 API a_eotd_hole[369];
1309
1310 API d_eotd_first;
1311 API d_eotd_max;
1312 API d_eotd_nrj_high;
1313 API d_eotd_nrj_low;
1314 API a_eotd_crosscor[18];
1315 #endif
1316 #endif
1317 }
1318 T_NDB_MCU_DSP;
1319
1320
1321 #else // OTHER DSP CODE like 17
1322
1323 typedef struct
1324 {
1325 // Monitoring tasks control..........(MCU <- DSP)
1326 API d_fb_det; // FB detection result. (1 for FOUND).
1327 API d_fb_mode; // Mode for FB detection algorithm.
1328 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
1329
1330 // CCCH/SACCH downlink information...(!!)
1331 API a_cd[15]; // Header + CCCH/SACCH downlink information.
1332
1333 // FACCH downlink information........(!!)
1334 API a_fd[15]; // Header + FACCH downlink information.
1335
1336 // Traffic downlink data frames......(!!)
1337 #if (DATA14_4 == 0)
1338 API a_dd_0[20]; // Header + DATA traffic downlink information, sub. chan. 0.
1339 API a_dd_1[20]; // Header + DATA traffic downlink information, sub. chan. 1.
1340 #endif
1341 #if (DATA14_4 == 1)
1342 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
1343 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
1344 #endif
1345
1346 // CCCH/SACCH uplink information.....(!!)
1347 API a_cu[15]; // Header + CCCH/SACCH uplink information.
1348
1349 #if (SPEECH_RECO)
1350 // FACCH downlink information........(!!)
1351 API a_fu[3]; // Header + FACCH uplink information
1352 // The size of this buffer is 15 word but some speech reco words
1353 // are overlayer with this buffer. This is the reason why the size is 3 instead of 15.
1354 API d_sr_status; // status of the DSP speech reco task
1355 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
1356 API sr_hole1; // hole
1357 API d_sr_bit_exact_test; // bit exact test
1358 API d_sr_nb_words; // number of words used in the speech recognition task
1359 API d_sr_db_level; // estimate voice level in dB
1360 API d_sr_db_noise; // estimate noise in dB
1361 API d_sr_mod_size; // size of the model
1362 API sr_holes_1[4]; // hole
1363 #else
1364 // FACCH downlink information........(!!)
1365 API a_fu[15]; // Header + FACCH uplink information
1366 #endif
1367
1368 // Traffic uplink data frames........(!!)
1369 #if (DATA14_4 == 0)
1370 API a_du_0[20]; // Header + DATA traffic uplink information, sub. chan. 0.
1371 API a_du_1[20]; // Header + DATA traffic uplink information, sub. chan. 1.
1372 #endif
1373 #if (DATA14_4 == 1)
1374 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
1375 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
1376 #endif
1377
1378 // Random access.....................(MCU -> DSP).
1379 API d_rach; // RACH information.
1380
1381 //...................................(MCU -> DSP).
1382 API d_a5mode; // Encryption Mode.
1383 API a_kc[4]; // Encryption Key Code.
1384 API d_tch_mode; // TCH mode register.
1385 // bit [0..1] -> b_dai_mode.
1386 // bit [2] -> b_dtx.
1387
1388 // OMEGA...........................(MCU -> DSP).
1389
1390 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
1391 API a_ramp[16];
1392 #if (MELODY_E1)
1393 API d_melo_osc_used;
1394 API d_melo_osc_active;
1395 API a_melo_note0[4];
1396 API a_melo_note1[4];
1397 API a_melo_note2[4];
1398 API a_melo_note3[4];
1399 API a_melo_note4[4];
1400 API a_melo_note5[4];
1401 API a_melo_note6[4];
1402 API a_melo_note7[4];
1403 #if (DSP == 17)
1404 // selection of the melody format
1405 API d_dco_type; // Tide
1406 API p_start_IQ;
1407 API d_level_off;
1408 API d_dco_dbg;
1409 API d_tide_resa;
1410 API d_asynch_margin; // Perseus Asynch Audio Workaround
1411 API hole[4];
1412 #else
1413 API d_melody_selection;
1414 API holes[9];
1415 #endif
1416 #else // NO MELODY E1
1417 // selection of the melody format
1418 #if (DSP == 17)
1419 API holes[34]; // 34 unused holes.
1420 API d_dco_type; // Tide
1421 API p_start_IQ;
1422 API d_level_off;
1423 API d_dco_dbg;
1424 API d_tide_resa;
1425 API d_asynch_margin; // Perseus Asynch Audio Workaround
1426 API hole[4]
1427 #else
1428 // selection of the melody format
1429 API d_melody_selection;
1430 API holes[43]; // 43 unused holes.
1431 #endif
1432 #endif
1433 API d_debug3;
1434 API d_debug2;
1435 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
1436 API d_afcctladd;
1437 API d_vbuctrl;
1438 API d_vbdctrl;
1439 API d_apcdel1;
1440 API d_aec_ctrl;
1441 API d_apcoff;
1442 API d_bulioff;
1443 API d_bulqoff;
1444 API d_dai_onoff;
1445 API d_auxdac;
1446 #if (ANLG_FAM == 1)
1447 API d_vbctrl;
1448 #elif (ANLG_FAM == 2)
1449 API d_vbctrl1;
1450 #endif
1451 API d_bbctrl;
1452
1453 #else
1454 #error DSPCODE not supported with given ANALOG
1455 #endif //(ANALOG)1, 2
1456 //...................................(MCU -> DSP).
1457 API a_sch26[5]; // Header + SB information, array of 5 words.
1458
1459 // TONES.............................(MCU -> DSP)
1460 API d_toneskb_init;
1461 API d_toneskb_status;
1462 API d_k_x1_t0;
1463 API d_k_x1_t1;
1464 API d_k_x1_t2;
1465 API d_pe_rep;
1466 API d_pe_off;
1467 API d_se_off;
1468 API d_bu_off;
1469 API d_t0_on;
1470 API d_t0_off;
1471 API d_t1_on;
1472 API d_t1_off;
1473 API d_t2_on;
1474 API d_t2_off;
1475 API d_k_x1_kt0;
1476 API d_k_x1_kt1;
1477 API d_dur_kb;
1478
1479 // PLL...............................(MCU -> DSP).
1480 API d_pll_clkmod1;
1481 API d_pll_clkmod2;
1482
1483 // DSP status returned..........(DSP --> MCU).
1484 API d_error_status;
1485
1486 // RIF control.......................(MCU -> DSP).
1487 API d_spcx_rif;
1488
1489 API d_shiftdl;
1490 API d_shiftul;
1491
1492 #if (AEC == 1)
1493 // AEC control.......................(MCU -> DSP).
1494 #if (VOC == FR_EFR)
1495 API p_aec_init;
1496 API p_aec_prog;
1497 API p_spenh_init;
1498 API p_spenh_prog;
1499 #endif
1500
1501 #if (VOC == FR_HR_EFR)
1502 API p_saec_prog;
1503 API p_aec_prog;
1504 API p_spenh_prog;
1505 #endif
1506 #endif
1507
1508 API a_ovly[75];
1509 API d_ra_conf;
1510 API d_ra_act;
1511 API d_ra_test;
1512 API d_ra_statu;
1513 API d_ra_statd;
1514 API d_fax;
1515 #if (SPEECH_RECO)
1516 API a_data_buf_ul[3];
1517 API a_n_best_words[4]; // array of the 4 best words
1518 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
1519 API sr_holes_2[6];
1520 API a_data_buf_dl[37];
1521
1522 API fir_holes1[409];
1523 API a_fir31_uplink[31];
1524 API a_fir31_downlink[31];
1525 API d_audio_init;
1526 API d_audio_status;
1527 API a_model[1041]; // array of the speech reco model
1528 #else
1529 API a_data_buf_ul[21];
1530 API a_data_buf_dl[37];
1531
1532 API fir_holes1[409];
1533 API a_fir31_uplink[31];
1534 API a_fir31_downlink[31];
1535 API d_audio_init;
1536 API d_audio_status;
1537 #endif
1538 }
1539 T_NDB_MCU_DSP;
1540 #endif
1541
1542 #if (DSP == 34) || (DSP == 35) || (DSP == 36)
1543 typedef struct
1544 {
1545 API_SIGNED d_transfer_rate;
1546
1547 // Common GSM/GPRS
1548 // These words specified the latencies to applies on some peripherics
1549 API_SIGNED d_lat_mcu_bridge;
1550 API_SIGNED d_lat_mcu_hom2sam;
1551 API_SIGNED d_lat_mcu_bef_fast_access;
1552 API_SIGNED d_lat_dsp_after_sam;
1553
1554 // DSP Start address
1555 API_SIGNED d_gprs_install_address;
1556
1557 API_SIGNED d_misc_config;
1558
1559 API_SIGNED d_cn_sw_workaround;
1560
1561 API_SIGNED d_hole2_param[4];
1562
1563 //...................................Frequency Burst.
1564 API_SIGNED d_fb_margin_beg;
1565 API_SIGNED d_fb_margin_end;
1566 API_SIGNED d_nsubb_idle;
1567 API_SIGNED d_nsubb_dedic;
1568 API_SIGNED d_fb_thr_det_iacq;
1569 API_SIGNED d_fb_thr_det_track;
1570 //...................................Demodulation.
1571 API_SIGNED d_dc_off_thres;
1572 API_SIGNED d_dummy_thres;
1573 API_SIGNED d_dem_pond_gewl;
1574 API_SIGNED d_dem_pond_red;
1575
1576 //...................................TCH Full Speech.
1577 API_SIGNED d_maccthresh1;
1578 API_SIGNED d_mldt;
1579 API_SIGNED d_maccthresh;
1580 API_SIGNED d_gu;
1581 API_SIGNED d_go;
1582 API_SIGNED d_attmax;
1583 API_SIGNED d_sm;
1584 API_SIGNED d_b;
1585
1586 // V42Bis module
1587 API_SIGNED d_v42b_switch_hyst;
1588 API_SIGNED d_v42b_switch_min;
1589 API_SIGNED d_v42b_switch_max;
1590 API_SIGNED d_v42b_reset_delay;
1591
1592 //...................................TCH Half Speech.
1593 API_SIGNED d_ldT_hr;
1594 API_SIGNED d_maccthresh_hr;
1595 API_SIGNED d_maccthresh1_hr;
1596 API_SIGNED d_gu_hr;
1597 API_SIGNED d_go_hr;
1598 API_SIGNED d_b_hr;
1599 API_SIGNED d_sm_hr;
1600 API_SIGNED d_attmax_hr;
1601
1602 //...................................TCH Enhanced FR Speech.
1603 API_SIGNED c_mldt_efr;
1604 API_SIGNED c_maccthresh_efr;
1605 API_SIGNED c_maccthresh1_efr;
1606 API_SIGNED c_gu_efr;
1607 API_SIGNED c_go_efr;
1608 API_SIGNED c_b_efr;
1609 API_SIGNED c_sm_efr;
1610 API_SIGNED c_attmax_efr;
1611
1612 //...................................CHED
1613 API_SIGNED d_sd_min_thr_tchfs;
1614 API_SIGNED d_ma_min_thr_tchfs;
1615 API_SIGNED d_md_max_thr_tchfs;
1616 API_SIGNED d_md1_max_thr_tchfs;
1617
1618 API_SIGNED d_sd_min_thr_tchhs;
1619 API_SIGNED d_ma_min_thr_tchhs;
1620 API_SIGNED d_sd_av_thr_tchhs;
1621 API_SIGNED d_md_max_thr_tchhs;
1622 API_SIGNED d_md1_max_thr_tchhs;
1623
1624 API_SIGNED d_sd_min_thr_tchefs;
1625 API_SIGNED d_ma_min_thr_tchefs;
1626 API_SIGNED d_md_max_thr_tchefs;
1627 API_SIGNED d_md1_max_thr_tchefs;
1628
1629 API_SIGNED d_wed_fil_ini;
1630 API_SIGNED d_wed_fil_tc;
1631 API_SIGNED d_x_min;
1632 API_SIGNED d_x_max;
1633 API_SIGNED d_slope;
1634 API_SIGNED d_y_min;
1635 API_SIGNED d_y_max;
1636 API_SIGNED d_wed_diff_threshold;
1637 API_SIGNED d_mabfi_min_thr_tchhs;
1638
1639 // FACCH module
1640 API_SIGNED d_facch_thr;
1641
1642 // IDS module
1643 API_SIGNED d_max_ovsp_ul;
1644 API_SIGNED d_sync_thres;
1645 API_SIGNED d_idle_thres;
1646 API_SIGNED d_m1_thres;
1647 API_SIGNED d_max_ovsp_dl;
1648 API_SIGNED d_gsm_bgd_mgt;
1649
1650 // FIR coefficients
1651 API a_fir_holes[4];
1652 API a_fir31_uplink[31];
1653 API a_fir31_downlink[31];
1654 }
1655 T_PARAM_MCU_DSP;
1656 #elif (DSP == 33)
1657 typedef struct
1658 {
1659 API_SIGNED d_transfer_rate;
1660
1661 // Common GSM/GPRS
1662 // These words specified the latencies to applies on some peripherics
1663 API_SIGNED d_lat_mcu_bridge;
1664 API_SIGNED d_lat_mcu_hom2sam;
1665 API_SIGNED d_lat_mcu_bef_fast_access;
1666 API_SIGNED d_lat_dsp_after_sam;
1667
1668 // DSP Start address
1669 API_SIGNED d_gprs_install_address;
1670
1671 API_SIGNED d_misc_config;
1672
1673 API_SIGNED d_cn_sw_workaround;
1674
1675 #if DCO_ALGO
1676 API_SIGNED d_cn_dco_param;
1677
1678 API_SIGNED d_hole2_param[3];
1679 #else
1680 API_SIGNED d_hole2_param[4];
1681 #endif
1682
1683 //...................................Frequency Burst.
1684 API_SIGNED d_fb_margin_beg;
1685 API_SIGNED d_fb_margin_end;
1686 API_SIGNED d_nsubb_idle;
1687 API_SIGNED d_nsubb_dedic;
1688 API_SIGNED d_fb_thr_det_iacq;
1689 API_SIGNED d_fb_thr_det_track;
1690 //...................................Demodulation.
1691 API_SIGNED d_dc_off_thres;
1692 API_SIGNED d_dummy_thres;
1693 API_SIGNED d_dem_pond_gewl;
1694 API_SIGNED d_dem_pond_red;
1695
1696 //...................................TCH Full Speech.
1697 API_SIGNED d_maccthresh1;
1698 API_SIGNED d_mldt;
1699 API_SIGNED d_maccthresh;
1700 API_SIGNED d_gu;
1701 API_SIGNED d_go;
1702 API_SIGNED d_attmax;
1703 API_SIGNED d_sm;
1704 API_SIGNED d_b;
1705
1706 // V42Bis module
1707 API_SIGNED d_v42b_switch_hyst;
1708 API_SIGNED d_v42b_switch_min;
1709 API_SIGNED d_v42b_switch_max;
1710 API_SIGNED d_v42b_reset_delay;
1711
1712 //...................................TCH Half Speech.
1713 API_SIGNED d_ldT_hr;
1714 API_SIGNED d_maccthresh_hr;
1715 API_SIGNED d_maccthresh1_hr;
1716 API_SIGNED d_gu_hr;
1717 API_SIGNED d_go_hr;
1718 API_SIGNED d_b_hr;
1719 API_SIGNED d_sm_hr;
1720 API_SIGNED d_attmax_hr;
1721
1722 //...................................TCH Enhanced FR Speech.
1723 API_SIGNED c_mldt_efr;
1724 API_SIGNED c_maccthresh_efr;
1725 API_SIGNED c_maccthresh1_efr;
1726 API_SIGNED c_gu_efr;
1727 API_SIGNED c_go_efr;
1728 API_SIGNED c_b_efr;
1729 API_SIGNED c_sm_efr;
1730 API_SIGNED c_attmax_efr;
1731
1732 //...................................CHED
1733 API_SIGNED d_sd_min_thr_tchfs;
1734 API_SIGNED d_ma_min_thr_tchfs;
1735 API_SIGNED d_md_max_thr_tchfs;
1736 API_SIGNED d_md1_max_thr_tchfs;
1737
1738 API_SIGNED d_sd_min_thr_tchhs;
1739 API_SIGNED d_ma_min_thr_tchhs;
1740 API_SIGNED d_sd_av_thr_tchhs;
1741 API_SIGNED d_md_max_thr_tchhs;
1742 API_SIGNED d_md1_max_thr_tchhs;
1743
1744 API_SIGNED d_sd_min_thr_tchefs;
1745 API_SIGNED d_ma_min_thr_tchefs;
1746 API_SIGNED d_md_max_thr_tchefs;
1747 API_SIGNED d_md1_max_thr_tchefs;
1748
1749 API_SIGNED d_wed_fil_ini;
1750 API_SIGNED d_wed_fil_tc;
1751 API_SIGNED d_x_min;
1752 API_SIGNED d_x_max;
1753 API_SIGNED d_slope;
1754 API_SIGNED d_y_min;
1755 API_SIGNED d_y_max;
1756 API_SIGNED d_wed_diff_threshold;
1757 API_SIGNED d_mabfi_min_thr_tchhs;
1758
1759 // FACCH module
1760 API_SIGNED d_facch_thr;
1761
1762 // IDS module
1763 API_SIGNED d_max_ovsp_ul;
1764 API_SIGNED d_sync_thres;
1765 API_SIGNED d_idle_thres;
1766 API_SIGNED d_m1_thres;
1767 API_SIGNED d_max_ovsp_dl;
1768 API_SIGNED d_gsm_bgd_mgt;
1769
1770 // FIR coefficients
1771 API a_fir_holes[4];
1772 API a_fir31_uplink[31];
1773 API a_fir31_downlink[31];
1774 }
1775 T_PARAM_MCU_DSP;
1776
1777 #else
1778
1779 typedef struct
1780 {
1781 //...................................Frequency Burst.
1782 API_SIGNED d_nsubb_idle;
1783 API_SIGNED d_nsubb_dedic;
1784 API_SIGNED d_fb_thr_det_iacq;
1785 API_SIGNED d_fb_thr_det_track;
1786 //...................................Demodulation.
1787 API_SIGNED d_dc_off_thres;
1788 API_SIGNED d_dummy_thres;
1789 API_SIGNED d_dem_pond_gewl;
1790 API_SIGNED d_dem_pond_red;
1791 API_SIGNED hole[1];
1792 API_SIGNED d_transfer_rate;
1793 //...................................TCH Full Speech.
1794 API_SIGNED d_maccthresh1;
1795 API_SIGNED d_mldt;
1796 API_SIGNED d_maccthresh;
1797 API_SIGNED d_gu;
1798 API_SIGNED d_go;
1799 API_SIGNED d_attmax;
1800 API_SIGNED d_sm;
1801 API_SIGNED d_b;
1802
1803 #if (VOC == FR_HR) || (VOC == FR_HR_EFR)
1804 //...................................TCH Half Speech.
1805 API_SIGNED d_ldT_hr;
1806 API_SIGNED d_maccthresh_hr;
1807 API_SIGNED d_maccthresh1_hr;
1808 API_SIGNED d_gu_hr;
1809 API_SIGNED d_go_hr;
1810 API_SIGNED d_b_hr;
1811 API_SIGNED d_sm_hr;
1812 API_SIGNED d_attmax_hr;
1813 #endif
1814
1815 #if (VOC == FR_EFR) || (VOC == FR_HR_EFR)
1816 //...................................TCH Enhanced FR Speech.
1817 API_SIGNED c_mldt_efr;
1818 API_SIGNED c_maccthresh_efr;
1819 API_SIGNED c_maccthresh1_efr;
1820 API_SIGNED c_gu_efr;
1821 API_SIGNED c_go_efr;
1822 API_SIGNED c_b_efr;
1823 API_SIGNED c_sm_efr;
1824 API_SIGNED c_attmax_efr;
1825 #endif
1826
1827 //...................................TCH Full Speech.
1828 API_SIGNED d_sd_min_thr_tchfs;
1829 API_SIGNED d_ma_min_thr_tchfs;
1830 API_SIGNED d_md_max_thr_tchfs;
1831 API_SIGNED d_md1_max_thr_tchfs;
1832
1833 #if (VOC == FR) || (VOC == FR_HR) || (VOC == FR_HR_EFR)
1834 //...................................TCH Half Speech.
1835 API_SIGNED d_sd_min_thr_tchhs;
1836 API_SIGNED d_ma_min_thr_tchhs;
1837 API_SIGNED d_sd_av_thr_tchhs;
1838 API_SIGNED d_md_max_thr_tchhs;
1839 API_SIGNED d_md1_max_thr_tchhs;
1840 #endif
1841
1842 #if (VOC == FR_EFR) || (VOC == FR_HR_EFR)
1843 //...................................TCH Enhanced FR Speech.
1844 API_SIGNED d_sd_min_thr_tchefs; //(24L *C_POND_RED)
1845 API_SIGNED d_ma_min_thr_tchefs; //(1200L *C_POND_RED)
1846 API_SIGNED d_md_max_thr_tchefs; //(2000L *C_POND_RED)
1847 API_SIGNED d_md1_max_thr_tchefs; //(160L *C_POND_RED)
1848 API_SIGNED d_hole1;
1849 #endif
1850
1851 API_SIGNED d_wed_fil_ini;
1852 API_SIGNED d_wed_fil_tc;
1853 API_SIGNED d_x_min;
1854 API_SIGNED d_x_max;
1855 API_SIGNED d_slope;
1856 API_SIGNED d_y_min;
1857 API_SIGNED d_y_max;
1858 API_SIGNED d_wed_diff_threshold;
1859 API_SIGNED d_mabfi_min_thr_tchhs;
1860 API_SIGNED d_facch_thr;
1861 API_SIGNED d_dsp_test;
1862
1863
1864 #if (DATA14_4 == 0 ) || (VOC == FR_HR_EFR)
1865 API_SIGNED d_patch_addr1;
1866 API_SIGNED d_patch_data1;
1867 API_SIGNED d_patch_addr2;
1868 API_SIGNED d_patch_data2;
1869 API_SIGNED d_patch_addr3;
1870 API_SIGNED d_patch_data3;
1871 API_SIGNED d_patch_addr4;
1872 API_SIGNED d_patch_data4;
1873 #endif
1874
1875 //...................................
1876 API_SIGNED d_version_number; // DSP patch version
1877 API_SIGNED d_ti_version; // customer number. No more used since 1.5
1878
1879 API_SIGNED d_dsp_page;
1880
1881 #if IDS
1882 API_SIGNED d_max_ovsp_ul;
1883 API_SIGNED d_sync_thres;
1884 API_SIGNED d_idle_thres;
1885 API_SIGNED d_m1_thres;
1886 API_SIGNED d_max_ovsp_dl;
1887 #endif
1888
1889
1890 }
1891 T_PARAM_MCU_DSP;
1892 #endif
1893
1894 #if (DSP_DEBUG_TRACE_ENABLE == 1)
1895 typedef struct
1896 {
1897 API d_debug_ptr_begin;
1898 API d_debug_ptr_end;
1899 }
1900 T_DB2_DSP_TO_MCU;
1901 #endif
1902
1903 /*************************************************************/
1904 /* Time informations... */
1905 /*************************************************************/
1906 /* */
1907 /*************************************************************/
1908 typedef struct
1909 {
1910 UWORD32 fn; // FN count
1911 UWORD16 t1; // FN div (26*51), (0..2047).
1912 UWORD8 t2; // FN modulo 26.
1913 UWORD8 t3; // FN modulo 51.
1914 UWORD8 tc; // Scell: TC
1915 UWORD8 fn_in_report; // FN modulo 102 or 104.
1916 UWORD16 fn_mod42432; // FN modulo 42432.
1917 UWORD8 fn_mod13; // FN modulo 13.
1918 #if L1_GPRS
1919 UWORD8 fn_mod52; // FN modulo 52.
1920 UWORD8 fn_mod104; // FN modulo 104.
1921 UWORD8 fn_mod13_mod4; // FN modulo 13 modulo 4.
1922 UWORD32 block_id; // Block ID
1923 #endif
1924 }
1925 T_TIME_INFO;
1926
1927 /*************************************************************/
1928 /* Idle mode tasks information... */
1929 /*************************************************************/
1930 /* must be filled according to Idle parameters... */
1931 /* ... */
1932 /*************************************************************/
1933 typedef struct
1934 {
1935 UWORD8 pg_position; // Paging block starting frame.
1936 UWORD8 extpg_position; // Extended Paging block starting frame.
1937 }
1938 T_IDLE_TASK_INFO;
1939
1940 /*************************************************************/
1941 /* SDCCH information structure. */
1942 /*************************************************************/
1943 /* */
1944 /* */
1945 /*************************************************************/
1946 typedef struct
1947 {
1948 UWORD8 dl_sdcch_position;
1949 UWORD8 dl_sacch_position;
1950 UWORD8 ul_sdcch_position;
1951 UWORD8 ul_sacch_position;
1952 UWORD8 mon_area_position;
1953 }
1954 T_SDCCH_DESC;
1955
1956 /*************************************************************/
1957 /* Random Access Task information structure. */
1958 /*************************************************************/
1959 /* */
1960 /* */
1961 /*************************************************************/
1962 typedef struct
1963 {
1964 WORD32 rand; // 16 bit signed !!
1965 UWORD8 channel_request;
1966 UWORD8 ra_to_ctrl;
1967 UWORD8 ra_num;
1968 }
1969 T_RA_TASK_INFO;
1970
1971 /***************************************************************************************/
1972 /* Measurement info element for last input level table */
1973 /***************************************************************************************/
1974 typedef struct
1975 {
1976 UWORD8 lna_off; // 1 if lna switch is off.
1977 UWORD8 input_level; // last measured input level in dbm.
1978 }
1979 T_INPUT_LEVEL;
1980
1981 /***************************************************************************************/
1982 /* Measurement info element for Neighbor cell lists. */
1983 /***************************************************************************************/
1984 typedef struct
1985 {
1986 UWORD16 radio_freq; // carrier id.
1987 WORD32 acc; // Accumulation of measurements already performed.
1988 UWORD8 nbr_meas;
1989 }
1990 T_MEAS_INFO;
1991
1992 typedef struct
1993 {
1994 UWORD16 bcch_freq;
1995 WORD16 rxlev_acc;
1996 UWORD8 rxlev_nbr_meas;
1997 }
1998 T5_CELL_MEAS;
1999
2000 typedef struct
2001 {
2002 T5_CELL_MEAS A[33];
2003 }
2004 T5_NCELL_MEAS;
2005
2006 /***************************************************************************************/
2007 /* Measurement info element serving cell in dedicated mode */
2008 /***************************************************************************************/
2009 typedef struct
2010 {
2011 WORD32 acc_sub; // Subset: accu. rxlev meas.
2012 UWORD32 nbr_meas_sub; // Subset: nbr meas. of rxlev.
2013 UWORD32 qual_acc_full; // Fullset: accu. rxqual meas.
2014 UWORD32 qual_acc_sub; // Subset: accu. rxqual meas.
2015 UWORD32 qual_nbr_meas_full; // Fullset: nbr meas. of rxqual.
2016 UWORD32 qual_nbr_meas_sub; // Subset: nbr meas. of rxqual.
2017 UWORD8 dtx_used; // Set when DTX as been used in current reporting period.
2018 }
2019 T_SMEAS;
2020
2021 /***************************************************************************************/
2022 /* */
2023 /***************************************************************************************/
2024 typedef struct
2025 {
2026 UWORD8 new_status;
2027 UWORD8 current_status;
2028 WORD32 time_to_exec;
2029 }
2030 T_TASK_STATUS;
2031
2032 /***************************************************************************************/
2033 /* Cell/Carrier info: identity, RX level measurement, time info, gain controle info. */
2034 /***************************************************************************************/
2035 typedef struct
2036 {
2037 // Carrier/Cell Identity.
2038 UWORD16 radio_freq; // carrier id.
2039 WORD32 bsic; // BSIC.
2040
2041 // Time difference information.
2042 UWORD32 fn_offset; // offset between fn of this NCELL and the SCELL fn.
2043 UWORD32 time_alignmt; // time alignment.
2044
2045 // Receive Level Measurement info. structure.
2046 T_MEAS_INFO meas;
2047 T_INPUT_LEVEL traffic_meas;
2048 T_INPUT_LEVEL traffic_meas_beacon;
2049
2050 // Beacon frequency FIFO
2051 UWORD8 buff_beacon[4];
2052
2053 #if L1_GPRS
2054 // Receive Level measurements in packet transfer mode
2055 // Daughter frequencies info.
2056 T_INPUT_LEVEL transfer_meas;
2057
2058 // Power reduction on serving cell PCCCH / PBCCH
2059 UWORD8 pb;
2060 #endif
2061
2062 // Number of unsuccessfull attempt on SB reading.
2063 UWORD8 attempt_count;
2064
2065 // System information bitmap.
2066 UWORD32 si_bit_map; // System info. bitmap used for BCCH reading.
2067 }
2068 T_CELL_INFO;
2069
2070
2071 typedef struct
2072 {
2073 UWORD16 A[32+1];
2074 }
2075 TC_CHAN_LIST;
2076
2077
2078 typedef struct
2079 {
2080 UWORD8 num_of_chans;
2081 TC_CHAN_LIST chan_list;
2082 BOOL pwrc;
2083 BOOL dtx_allowed;
2084 UWORD8 ba_id;
2085 }
2086 T_NEW_BA_LIST;
2087
2088
2089 typedef struct
2090 {
2091 UWORD8 ba_id; // BA list identifier.
2092
2093 UWORD32 nbr_carrier; // number of carriers in the BA list.
2094 UWORD8 np_ctrl; // Tels the meas_manager which PCH burst has been controled.
2095
2096 UWORD8 first_index; // First BA index measured in current session.
2097
2098 UWORD8 next_to_ctrl; // Carrier for next power measurement result.
2099 UWORD8 next_to_read; // Measurement session time spent.
2100
2101 UWORD8 ms_ctrl;
2102 UWORD8 ms_ctrl_d;
2103 UWORD8 ms_ctrl_dd;
2104
2105 UWORD8 used_il [2];
2106 UWORD8 used_il_d [2];
2107 UWORD8 used_il_dd[2];
2108
2109 UWORD8 used_lna [2];
2110 UWORD8 used_lna_d [2];
2111 UWORD8 used_lna_dd[2];
2112
2113 T_MEAS_INFO A[32+1]; // list of 32 neighbors + 1 serving.
2114
2115 BOOL new_list_present;
2116 T_NEW_BA_LIST new_list;
2117 }
2118 T_BA_LIST;
2119
2120 typedef struct
2121 {
2122 UWORD16 radio_freq;
2123 WORD16 accum_power_result;
2124 }
2125 T_POWER_ARRAY;
2126
2127 typedef struct
2128 {
2129 UWORD16 power_array_size;
2130 T_POWER_ARRAY power_array[NBMAX_CARRIER];
2131 }
2132 T_FULL_LIST_MEAS;
2133
2134 typedef struct
2135 {
2136 UWORD32 nbr_sat_carrier_ctrl; // Nb of saturated carriers after a pm session in ctrl.
2137 UWORD32 nbr_sat_carrier_read; // Nb of saturated carriers after a pm session in read.
2138
2139 UWORD8 meas_1st_pass_ctrl; // flag for 1st pass during a pm session in ctrl.
2140 UWORD8 meas_1st_pass_read; // flag for 1st pass during a pm session in read.
2141
2142 UWORD32 next_to_ctrl; // Carrier for next power measurement result.
2143 UWORD32 next_to_read; // Measurement session time spent.
2144
2145 UWORD8 ms_ctrl;
2146 UWORD8 ms_ctrl_d;
2147 UWORD8 ms_ctrl_dd;
2148
2149 UWORD8 sat_flag[NBMAX_CARRIER];
2150 // last measure was saturated, so not valid
2151 }
2152 T_FULL_LIST;
2153
2154 /*************************************************************/
2155 /* Dedicated channel information structure... */
2156 /*************************************************************/
2157 /* */
2158 /*************************************************************/
2159 typedef struct
2160 {
2161 T_CHANNEL_DESCRIPTION *desc_ptr; // Ptr to the Active channel description
2162 T_CHANNEL_DESCRIPTION desc; // Channel description for AFTER STI.
2163 T_CHANNEL_DESCRIPTION desc_bef_sti; // Channel description for BEFORE STI.
2164 UWORD8 mode; // Channel mode.
2165 UWORD8 tch_loop; // TCH loop mode.
2166 }
2167 T_CHANNEL_INFO;
2168
2169 /*************************************************************/
2170 /* Mobile allocation information structure... */
2171 /*************************************************************/
2172 /* */
2173 /*************************************************************/
2174 typedef struct
2175 {
2176 T_MOBILE_ALLOCATION *alist_ptr; // Ptr to the Active frequency list
2177 T_MOBILE_ALLOCATION freq_list;
2178 T_MOBILE_ALLOCATION freq_list_bef_sti;
2179 }
2180 T_MA_INFO;
2181
2182 /*************************************************************/
2183 /* Dedicated channel parameter structure... */
2184 /*************************************************************/
2185 /* */
2186 /*************************************************************/
2187 typedef struct
2188 {
2189 T_CHANNEL_INFO *achan_ptr; // Ptr to the Active channel (chan1 or chan2)
2190 T_CHANNEL_INFO chan1;
2191 T_CHANNEL_INFO chan2;
2192
2193 T_MA_INFO ma;
2194
2195 WORD32 serv_sti_fn; // Chan. desc. change time, serving domain.(-1 for not in use).
2196 WORD32 neig_sti_fn; // Chan. desc. change time, neighbor domain.(-1 for not in use).
2197
2198 // Frequency redefinition ongoing flag.
2199 //-------------------------------------
2200 UWORD8 freq_redef_flag; // Set to TRUE when a Freq. Redef. must be confirmed.
2201
2202 // Timing Advance management.
2203 //---------------------------
2204 UWORD8 timing_advance; // Currently used TA.
2205 UWORD8 new_timing_advance; // New timing advance value to be used on 1st frame
2206 // of the next reporting period.
2207 // TXPWR management.
2208 //-------------------
2209 UWORD8 new_target_txpwr; // New Target value for TXPWR control algo.
2210
2211
2212 T_CELL_INFO cell_desc; // Ptr to the new serving cell to download.
2213
2214 // DAI test mode... DTX allowed...
2215 UWORD8 dai_mode; // Dai test mode.
2216 BOOL dtx_allowed; // DTX allowed (flag).
2217
2218 // Encryption...
2219 T_ENCRYPTION_KEY ciph_key;
2220 UWORD8 a5mode;
2221
2222 // For handover...
2223 UWORD8 ho_acc; // Handover access (part of HO reference)
2224 WORD32 ho_acc_to_send; // Set to 4 for SYNC HO and to -1 for ASYNC HO.
2225 UWORD8 t3124; // Timer used in Async. Ho.
2226
2227 // For DPAGC algorithms purpose
2228 UWORD8 G_all[DPAGC_FIFO_LEN];
2229 UWORD8 G_DTX[DPAGC_FIFO_LEN];
2230 #if (AMR == 1)
2231 UWORD8 G_amr[DPAGC_AMR_FIFO_LEN];
2232 #endif
2233
2234 #if IDS
2235 // IDS mode configuration
2236 UWORD8 ids_mode; // Information transfert capability coded on 2 bits
2237 // 0: speech
2238 // 1: data service
2239 // 2: fax service
2240 #endif
2241 #if (AMR == 1)
2242 T_AMR_CONFIGURATION amr_configuration;
2243 UWORD8 cmip;
2244 #endif
2245 }
2246 T_DEDIC_SET;
2247
2248 /*************************************************************/
2249 /* Dedicated channel parameter structure... */
2250 /*************************************************************/
2251 /* */
2252 /*************************************************************/
2253 typedef struct
2254 {
2255 T_DEDIC_SET *aset; // Ptr to the Active parameter set
2256 T_DEDIC_SET *fset; // Ptr to the Free parameter set
2257 T_DEDIC_SET set[2]; // Table of parameter set
2258
2259 T_MPHC_CHANNEL_MODE_MODIFY_REQ mode_modif; // New mode for a given subchannel.
2260 WORD32 SignalCode; // Message name, set when a new param. set is given
2261
2262 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
2263 UWORD8 reset_sacch; // Flag to control SACCH reset (set during CHAN ASSIGN and Hand-overs)
2264 UWORD8 vocoder_on; // Flag to control execution of vocoder
2265 UWORD8 start_vocoder; // Flag to trigger start of vocoder (vocoder must be started with a synchro start)
2266 #endif
2267
2268 UWORD8 sync_tch; // Flag used to synchronize TCH/F or TCH/H.
2269 UWORD8 reset_facch; // Flag used to reset FACCH buffer header on new IAS/CAS/handover
2270 UWORD8 stop_tch; // Flag used to stop TCH/F or TCH/H (VEGA pwrdown).
2271
2272 UWORD16 radio_freq; // ARFCN buffer (returned by hopping algo).
2273 UWORD16 radio_freq_d; // 1 frame delayed ARFCN.
2274 UWORD16 radio_freq_dd; // 2 frames delayed ARFCN.
2275
2276 BOOL pwrc; // Flag used to reject serving pwr meas. on beacon.
2277
2278 BOOL handover_fail_mode; // Flag used to indicate that the L1 wait for an handover fail request
2279 #if (AMR == 1)
2280 BOOL sync_amr; // Flag used to tell to the DSP that a new AMR paramters is ready in the NDB.
2281 #endif
2282 }
2283 T_DEDIC_PARAM;
2284
2285 /*************************************************************/
2286 /* Power Management structure... */
2287 /*************************************************************/
2288 typedef struct
2289 {
2290 // fields of TST_SLEEP_REQ primitive ....
2291 UWORD8 mode_authorized; // NONE,SMALL,BIG,DEEP,ALL
2292 UWORD32 clocks; // clocks disabled in Big sleep
2293
2294 // 32 Khz gauging ....
2295 UWORD8 gauging_task; // ACTIVE, INACTIVE,WAIT-IQ
2296 UWORD8 gaug_duration; // gauging task duration
2297 UWORD8 gaug_count; // gauging task duration compteur
2298 UWORD32 histo[SIZE_HIST][2];// gauging histogram
2299 UWORD8 enough_gaug; // enough good gauging
2300 UWORD8 paging_scheduled; // first Paging Frame
2301
2302 // flags and variables for wake-up ....
2303 UWORD8 Os_ticks_required; // TRUE : Os ticks to recover
2304 UWORD8 frame_adjust; // TRUE : adjust 1 frame
2305 UWORD32 sleep_duration; // sleep duration computed at wakeup
2306
2307 // flag for sleep ....
2308 UWORD8 sleep_performed; // NONE,SMALL,BIG,DEEP,ALL
2309
2310 // status of clocks modules ....
2311 UWORD32 modules_status; // modules clocks status
2312
2313 // constantes for 32Khz filtering
2314 UWORD32 c_clk_min; // INIT state
2315 UWORD32 c_clk_init_min; // INIT state
2316 UWORD32 c_clk_max; // INIT state
2317 UWORD32 c_clk_init_max; // INIT state
2318 UWORD32 c_delta_hf_acquis; // ACQUIS state
2319 UWORD32 c_delta_hf_update; // UPDATE state
2320
2321 // trace gauging parameters
2322 UWORD8 state; // state of the gauging
2323 UWORD32 lf; // Number of the 32KHz
2324 UWORD32 hf; // HF: nb_hf( Number of the 13MHz *6 )
2325 UWORD32 root; // root & frac: the ratio of the HF & LF in each state.
2326 UWORD32 frac;
2327
2328 }
2329 T_POWER_MNGT;
2330
2331 /*************************************************************/
2332 /* code version structure... */
2333 /*************************************************************/
2334 typedef struct
2335 {
2336 // DSP versions & checksum
2337 UWORD16 dsp_code_version;
2338 UWORD16 dsp_patch_version;
2339 UWORD16 dsp_checksum; // DSP checksum : patch+code
2340
2341 // MCU versions
2342 UWORD16 mcu_tcs_program_release;
2343 UWORD16 mcu_tcs_official;
2344 UWORD16 mcu_tcs_internal;
2345 UWORD16 mcu_tm_version;
2346 }
2347 T_VERSION;
2348
2349 #if L1_RECOVERY
2350 typedef struct
2351 {
2352 UWORD32 frame_count;
2353 }
2354 T_L1S_RECOVER;
2355 #endif
2356
2357 /***************************************************************************************/
2358 /* L1S global variable structure... */
2359 /***************************************************************************************/
2360 typedef struct
2361 {
2362 //++++++++++++++++++++
2363 // Power Management...
2364 //++++++++++++++++++++
2365
2366 T_POWER_MNGT pw_mgr; // data base for power management
2367
2368 // Time for debug & Simulation purpose...
2369 // -> used as base time for BTS simulation.
2370 //-----------------------------------------
2371 UWORD32 debug_time; // time counter used by L3 scenario...
2372
2373 // L1S Tasks management...
2374 //-----------------------------------------
2375 T_TASK_STATUS task_status[NBR_DL_L1S_TASKS]; // ...in L1S, scheduler.
2376 UWORD8 frame_count; // ...nb frames to go.
2377 UWORD8 forbid_meas; // ...frames where meas. ctrl is not allowed.
2378
2379 // MFTAB management variables...
2380 //-----------------------------------------
2381 UWORD8 afrm; // active frame ID.
2382 T_MFTAB FAR mftab; // Multiframe table.
2383
2384 // Control parameters...
2385 //-----------------------------------------
2386 UWORD32 afc_frame_count; // AFC, Frame count between 2 calls to afc control function.
2387 WORD16 afc; // AFC, Common Frequency controle.
2388 WORD16 toa_shift; // TOA, value used to update the TOA
2389 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results.
2390
2391 UWORD16 toa_period_count; // TOA frame period used in PACKET TRANSFER MODE
2392 BOOL toa_update; // TOA, is set at the end of the update period, toa update occurs on next valid frame
2393
2394 // Flag registers for RF task controle...
2395 //-----------------------------------------
2396 // Made these control registers short's as more than 8-bits required.
2397 UWORD16 tpu_ctrl_reg; // (x,x,x,x,SYNC,RX,TX,MS) RX/TX/MS/SYNC bit ON whenever an
2398 // according "controle" has been setup in the current frame.
2399 UWORD16 dsp_ctrl_reg; // (x,x,x,x,x,RX,TX,MS) RX/TX/MS bit ON whenever an
2400 // according "controle" has been setup in the current frame.
2401
2402 //+++++++++++++++++++
2403 // Serving...
2404 //+++++++++++++++++++
2405
2406 // Serving frame number management.
2407 //---------------------------------
2408 T_TIME_INFO actual_time; // Time info: current FN, T1, T2, T3...
2409 T_TIME_INFO next_time; // Time info: next FN, T1, T2, T3...
2410 T_TIME_INFO next_plus_time; // Time info: next FN, T1, T2, T3...
2411
2412 // TXPWR management.
2413 //-------------------
2414 UWORD8 reported_txpwr; // Reported value for TXPWR.
2415 UWORD8 applied_txpwr; // Current value for TXPWR.
2416
2417 // Last RXQUAL value.
2418 //-------------------
2419 UWORD8 rxqual; // last rxqual value.
2420
2421 // Hardware info.
2422 //---------------
2423 UWORD32 tpu_offset; // Current TPU offset register value safeguard.
2424 UWORD32 tpu_offset_hw; // Current TPU offset register value copied in the TPU.
2425 UWORD16 tpu_win; // tpu window identifier inside a TDMA.
2426
2427 // code versions
2428 T_VERSION version;
2429
2430 #if (L1_GTT == 1)
2431 UWORD8 tty_state; // state for L1S GTT manager.
2432 #if L2_L3_SIMUL
2433 // GTT test
2434 T_GTT_TEST_L1S gtt_test;
2435 #endif
2436 #endif
2437
2438 #if (L1_DYN_DSP_DWNLD == 1)
2439 UWORD8 dyn_dwnld_state; // state for L1S DYN DWNLD manager
2440 #endif
2441 #if (AUDIO_TASK == 1)
2442 // Audio task.
2443 //-----------------------------------------
2444 BOOL l1_audio_it_com; // Flag to enable the ITCOM.
2445 UWORD8 audio_state[NBR_AUDIO_MANAGER]; // state for L1S audio manager.
2446 #if (MELODY_E1)
2447 T_L1S_MELODY_TASK melody0;
2448 T_L1S_MELODY_TASK melody1;
2449 #endif
2450 #if (VOICE_MEMO)
2451 T_L1S_VM_TASK voicememo;
2452 #endif
2453 #if (L1_VOICE_MEMO_AMR)
2454 T_L1S_VM_AMR_TASK voicememo_amr;
2455 #endif
2456 #if (SPEECH_RECO)
2457 T_L1S_SR_TASK speechreco;
2458 #endif
2459 #if (AEC)
2460 T_L1S_AEC_TASK aec;
2461 #endif
2462 #if (MELODY_E2)
2463 T_L1S_MELODY_E2_COMMON_VAR melody_e2;
2464 T_L1S_MELODY_E2_TASK melody0_e2;
2465 T_L1S_MELODY_E2_TASK melody1_e2;
2466 #endif
2467 #endif
2468
2469 UWORD8 last_used_txpwr;
2470
2471 #if L1_GPRS
2472 BOOL ctrl_synch_before; //control of synchro for CCCH reading en TN-2
2473 #endif
2474
2475 #if L1_RECOVERY
2476 T_L1S_RECOVER recovery;
2477 #endif
2478 BOOL spurious_fb_detected;
2479
2480 // Handling DTX mode
2481 BOOL dtx_ul_on;
2482 WORD8 facch_bursts;
2483
2484 // DTX mode in AMR
2485 BOOL dtx_amr_dl_on; // set to TRUE when the AMR is in DTX mode in downlink
2486
2487 }
2488 T_L1S_GLOBAL;
2489
2490 /***************************************************************************************/
2491 /* L1A global variable structure... */
2492 /***************************************************************************************/
2493 typedef struct
2494 {
2495 // State for L1A state machines...
2496 //-----------------------------------------
2497 UWORD8 state[NBR_L1A_PROCESSES];
2498
2499 // Measurement tasks management...
2500 //-----------------------------------------
2501 UWORD32 l1a_en_meas[NBR_L1A_PROCESSES];
2502
2503 // Flag for forward/delete message management.
2504 //---------------------------------------------
2505 UWORD8 l1_msg_forwarded;
2506
2507 #if (L1_DYN_DSP_DWNLD == 1)
2508 // Dynamic donload global variables
2509 T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld;
2510 #endif
2511
2512 // signal code indicating the reason of L1C_DEDIC_DONE
2513 UWORD32 confirm_SignalCode;
2514
2515 // Trace the best frequencies reported in MPHC_RXLEV_IND
2516 #if (L1_MPHC_RXLEV_IND_REPORT_SORT==1)
2517 UWORD16 tab_index[MAX_MEAS_RXLEV_IND_TRACE];
2518 UWORD16 max_report; //max number of fq reported, can be < MAX_MEAS_RXLEV_IND_TRACE if list is smaller
2519 #endif
2520 }
2521 T_L1A_GLOBAL;
2522
2523 /***************************************************************************************/
2524 /* L1A -> L1S communication structure... */
2525 /***************************************************************************************/
2526 typedef struct
2527 {
2528 //+++++++++++++++++++
2529 // Serving Cell...
2530 //+++++++++++++++++++
2531
2532 // Serving Cell identity and information.
2533 //---------------------------------------
2534 T_CELL_INFO Scell_info;
2535 T_SMEAS Smeas_dedic;
2536
2537 UWORD8 Scell_IL_for_rxlev;
2538 T_INPUT_LEVEL Scell_used_IL;
2539 T_INPUT_LEVEL Scell_used_IL_d;
2540 T_INPUT_LEVEL Scell_used_IL_dd;
2541
2542 T_BCCHS nbcchs;
2543 T_BCCHS ebcchs;
2544
2545 // Synchro information.
2546 //---------------------------------------
2547 WORD8 tn_difference; // Timeslot difference for next synchro.
2548 UWORD8 dl_tn; // Current timeslot for downlink stuffs.
2549 #if L1_GPRS
2550 UWORD8 dsp_scheduler_mode; // DSP Scheduler mode (GPRS or GSM).
2551 #endif
2552
2553 // Idle parameters.
2554 //-----------------
2555 BOOL bcch_combined; // BS_CCCH_SDCCH_COMB flag.
2556 UWORD8 bs_pa_mfrms; // BS_PA_MFRMS parameter.
2557 UWORD8 bs_ag_blks_res; // BS_AG_BLKS_RES parameter.
2558 UWORD8 ccch_group; // CCCH_GROUP parameter.
2559 UWORD8 page_group; // PAGING_GROUP parameter.
2560 UWORD8 page_block_index; // Paging block index paramter.
2561 T_IDLE_TASK_INFO idle_task_info; // Idle task positions...
2562 UWORD8 nb_pch_per_mf51; // nbr paging blocks per mf51.
2563
2564 // CBCH parameters.
2565 // ----------------
2566 UWORD32 offset_tn0; // TPU offset for TN=0 (used for SMSCB only).
2567 T_CHANNEL_DESCRIPTION cbch_desc; // CBCH (SMSCB) channel description.
2568 T_MOBILE_ALLOCATION cbch_freq_list; // CBCH frequency list (hopping freq list).
2569 UWORD32 mf51_fn; // Starting FN (for CBCH reading.
2570 UWORD8 cbch_start_in_mf51; // Starting position of CBCH in the MF51.
2571 T_CBCH_HEAD_SCHEDULE norm_cbch_schedule; // Normal CBCH scheduling structure.
2572 T_CBCH_HEAD_SCHEDULE ext_cbch_schedule; // Extended CBCH scheduling structure.
2573 T_CBCH_INFO_SCHEDULE cbch_info_req;
2574 BOOL pre_scheduled_cbch; // CBCH task has to be scheduled 1 FN in advance
2575 BOOL change_synchro_cbch;// A Pseudo Synchro is needed to read CBCH block
2576 UWORD8 tn_smscb; // CBCH TN taking into account new Synchro
2577
2578 // Random Access information.
2579 // ----------------------------
2580 T_RA_TASK_INFO ra_info;
2581
2582 // ADC management.
2583 //-------------------
2584 UWORD16 adc_mode;
2585 UWORD8 adc_idle_period;
2586 UWORD8 adc_traffic_period;
2587 UWORD8 adc_cpt;
2588
2589 // TXPWR management.
2590 //-------------------
2591 UWORD8 powerclass_band1; // Power class for the MS, given in ACCESS LINK mode (GSM Band).
2592 UWORD8 powerclass_band2; // Power class for the MS, given in ACCESS LINK mode (DCS Band).
2593
2594 // Dedicated parameters.
2595 //----------------------
2596 T_DEDIC_PARAM dedic_set; // Dedicated channel parameters.
2597
2598 //+++++++++++++++++++
2599 // Neighbour Cells...
2600 //+++++++++++++++++++
2601
2602 T_BCCHN_LIST bcchn;
2603 T_NSYNC_LIST nsync;
2604
2605 // BA list / FULL list.
2606 //---------------------
2607 T_BA_LIST ba_list;
2608 T_FULL_LIST full_list;
2609 T_FULL_LIST_MEAS *full_list_ptr;
2610
2611 //+++++++++++++++++++
2612 // L1S scheduler...
2613 //+++++++++++++++++++
2614
2615 // L1S tasks management...
2616 //-----------------------------------------
2617 BOOL task_param[NBR_DL_L1S_TASKS]; // ...synchro semaphores.
2618 BOOL l1s_en_task[NBR_DL_L1S_TASKS]; // ...enable register.
2619 UWORD32 time_to_next_l1s_task; // time to wait to reach starting frame of next task.
2620 UWORD8 l1a_activity_flag; // Activity flag.
2621
2622 // Measurement tasks management...
2623 //-----------------------------------------
2624 UWORD32 meas_param; // Synchro semaphore bit register.
2625 UWORD32 l1s_en_meas; // Enable task bit register.
2626
2627 // L1 mode...
2628 //-----------------------------------------
2629 UWORD32 mode; // functional mode: CS_MODE, I_MODE...
2630
2631 //++++++++++++++++++++++++
2632 // Controle parameters...
2633 //++++++++++++++++++++++++
2634 UWORD32 fb_mode; // Mode for fb detection algorithm.
2635 UWORD8 toa_reset; // Flag for TOA algo. reset.
2636
2637 // Input level memory for AGC management.
2638 //---------------------------------------
2639 T_INPUT_LEVEL last_input_level[NBMAX_CARRIER+1];
2640
2641 BOOL recovery_flag; // in case of the system is down and needs to be recovered
2642
2643 //++++++++++++++++++++++++
2644 // Audio task...
2645 //++++++++++++++++++++++++
2646 #if (AUDIO_TASK == 1)
2647 #if (KEYBEEP)
2648 T_KEYBEEP_TASK keybeep_task;
2649 #endif
2650 #if (TONE)
2651 T_TONE_TASK tone_task;
2652 #endif
2653 #if (MELODY_E1)
2654 T_MELODY_TASK melody0_task;
2655 T_MELODY_TASK melody1_task;
2656 #endif
2657 #if (VOICE_MEMO)
2658 T_VM_TASK voicememo_task;
2659 #endif
2660 #if (L1_VOICE_MEMO_AMR)
2661 T_VM_AMR_TASK voicememo_amr_task;
2662 #endif
2663 #if (SPEECH_RECO)
2664 T_SR_TASK speechreco_task;
2665 #endif
2666 #if (AEC)
2667 T_AEC_TASK aec_task;
2668 #endif
2669 #if (FIR)
2670 T_FIR_TASK fir_task;
2671 #endif
2672 #if (AUDIO_MODE)
2673 T_AUDIO_MODE_TASK audio_mode_task;
2674 #endif
2675 #if (MELODY_E2)
2676 T_MELODY_E2_TASK melody0_e2_task;
2677 T_MELODY_E2_TASK melody1_e2_task;
2678 #endif
2679 #if (L1_CPORT == 1)
2680 T_CPORT_TASK cport_task;
2681 #endif
2682 #endif
2683
2684 //+++++++++++++
2685 // GTT task
2686 //+++++++++++++
2687
2688 #if (L1_GTT == 1)
2689 T_GTT_TASK gtt_task;
2690 #endif
2691
2692 // Dynamic DSP download task
2693 #if (L1_DYN_DSP_DWNLD == 1)
2694 T_DYN_DWNLD_TASK_COMMAND dyn_dwnld_task;
2695 #endif
2696
2697 }
2698 T_L1A_L1S_COM;
2699
2700 /***************************************************************************************/
2701 /* L1A -> DSP communication structure... */
2702 /***************************************************************************************/
2703 typedef struct
2704 {
2705 UWORD8 dsp_w_page; // Active page for ARM "writting" to DSP {0,1}.
2706 UWORD8 dsp_r_page; // Active page for ARM "reading" from DSP {0,1}.
2707 UWORD8 dsp_r_page_used; // Used in "l1_synch" to know if the read page must be chged.
2708
2709 T_DB_DSP_TO_MCU *dsp_db_r_ptr; // MCU<->DSP comm. read page (Double Buffered comm. memory).
2710 T_DB_MCU_TO_DSP *dsp_db_w_ptr; // MCU<->DSP comm. write page (Double Buffered comm. memory).
2711 T_NDB_MCU_DSP *dsp_ndb_ptr; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
2712
2713 T_PARAM_MCU_DSP *dsp_param_ptr; // MCU<->DSP comm. read/write (Param comm. memory).
2714
2715 #if (DSP_DEBUG_TRACE_ENABLE == 1)
2716 T_DB2_DSP_TO_MCU *dsp_db2_current_r_ptr;
2717 T_DB2_DSP_TO_MCU *dsp_db2_other_r_ptr;
2718 #endif
2719 }
2720 T_L1S_DSP_COM;
2721
2722 /***************************************************************************************/
2723 /* L1A -> TPU communication structure... */
2724 /***************************************************************************************/
2725 typedef struct
2726 {
2727 UWORD8 tpu_w_page; // Active page for ARM "writting" to TPU {0,1}.
2728 UWORD32 *tpu_page_ptr; // Current Pointer within the active "tpu_page".
2729 #if (CODE_VERSION == SIMULATION)
2730 T_reg_cmd *reg_cmd; // command register for TPU & DSP enabling and pages pgmation
2731 #else
2732 UWORD16 *reg_cmd; // command register for TPU & DSP enabling and pages pgmation
2733 #endif
2734 UWORD32 *reg_com_int; // communication int. register
2735 UWORD32 *offset; // offset register
2736 }
2737 T_L1S_TPU_COM;
2738
2739 /***************************************************************************************/
2740 /* L1 configuration structure */
2741 /***************************************************************************************/
2742
2743 typedef struct
2744 {
2745 UWORD8 id; //standard identifier
2746
2747
2748
2749 UWORD16 radio_band_support;
2750
2751
2752 UWORD8 swap_iq_band1;
2753 UWORD8 swap_iq_band2;
2754
2755 UWORD32 first_radio_freq;
2756 UWORD32 first_radio_freq_band2;
2757 UWORD32 radio_freq_index_offset;
2758 UWORD32 nbmax_carrier;
2759 UWORD32 nbmeas;
2760 UWORD32 max_txpwr_band1;
2761 UWORD32 max_txpwr_band2;
2762 UWORD32 txpwr_turning_point;
2763
2764 UWORD16 cal_freq1_band1;
2765 UWORD16 cal_freq1_band2;
2766 UWORD16 g_magic_band1;
2767 UWORD16 g_magic_band2;
2768 UWORD16 lna_att_band1;
2769 UWORD16 lna_att_band2;
2770 UWORD16 lna_switch_thr_low_band1;
2771 UWORD16 lna_switch_thr_low_band2;
2772 UWORD16 lna_switch_thr_high_band1;
2773 UWORD16 lna_switch_thr_high_band2;
2774 }
2775 T_L1_STD_CNFG;
2776
2777 //RF dependent parameter definitions
2778 typedef struct
2779 {
2780 UWORD16 rx_synth_setup_time;
2781 UWORD8 rx_synth_load_split;
2782 WORD16 rx_synth_start_time;
2783 WORD16 rx_change_offset_time;
2784 WORD16 rx_change_synchro_time;
2785 UWORD8 rx_tpu_scenario_ending;
2786
2787 UWORD16 tx_synth_setup_time;
2788 UWORD8 tx_synth_load_split;
2789 WORD16 tx_synth_start_time;
2790 WORD16 tx_change_offset_time;
2791 WORD16 tx_nb_duration;
2792 WORD16 tx_ra_duration;
2793 UWORD8 tx_nb_load_split;
2794 UWORD8 tx_ra_load_split;
2795 UWORD8 tx_tpu_scenario_ending;
2796
2797 WORD16 fb26_anchoring_time;
2798 WORD16 fb26_change_offset_time;
2799
2800 UWORD32 prg_tx_gsm;
2801 UWORD32 prg_tx_dcs;
2802
2803 UWORD16 low_agc_noise_thr;
2804 UWORD16 high_agc_sat_thr;
2805
2806 UWORD16 low_agc;
2807 UWORD16 high_agc;
2808
2809 UWORD16 il_min;
2810
2811 UWORD16 fixed_txpwr;
2812 WORD16 eeprom_afc;
2813 WORD8 setup_afc_and_rf;
2814
2815 UWORD32 psi_sta_inv;
2816 UWORD32 psi_st;
2817 UWORD32 psi_st_32;
2818 UWORD32 psi_st_inv;
2819
2820 #if (VCXO_ALGO==1)
2821 WORD16 afc_dac_center;
2822 WORD16 afc_dac_min;
2823 WORD16 afc_dac_max;
2824 WORD16 afc_snr_thr;
2825 UWORD8 afc_algo;
2826 UWORD8 afc_win_avg_size_M;
2827 UWORD8 rgap_algo;
2828 UWORD8 rgap_bad_snr_count_B;
2829 #endif
2830
2831 UWORD8 guard_bits;
2832
2833 #if DCO_ALGO
2834 BOOL dco_enabled;
2835 #endif
2836
2837 #if (ANLG_FAM == 1)
2838 UWORD16 debug1;
2839 UWORD16 afcctladd;
2840 UWORD16 vbuctrl;
2841 UWORD16 vbdctrl;
2842 UWORD16 bbctrl;
2843 UWORD16 apcoff;
2844 UWORD16 bulioff;
2845 UWORD16 bulqoff;
2846 UWORD16 dai_onoff;
2847 UWORD16 auxdac;
2848 UWORD16 vbctrl;
2849 UWORD16 apcdel1;
2850 #endif
2851 #if (ANLG_FAM == 2)
2852 UWORD16 debug1;
2853 UWORD16 afcctladd;
2854 UWORD16 vbuctrl;
2855 UWORD16 vbdctrl;
2856 UWORD16 bbctrl;
2857 UWORD16 bulgcal;
2858 UWORD16 apcoff;
2859 UWORD16 bulioff;
2860 UWORD16 bulqoff;
2861 UWORD16 dai_onoff;
2862 UWORD16 auxdac;
2863 UWORD16 vbctrl1;
2864 UWORD16 vbctrl2;
2865 UWORD16 apcdel1;
2866 UWORD16 apcdel2;
2867 #endif
2868 #if (ANLG_FAM == 3)
2869 UWORD16 debug1;
2870 UWORD16 afcctladd;
2871 UWORD16 vbuctrl;
2872 UWORD16 vbdctrl;
2873 UWORD16 bbctrl;
2874 UWORD16 bulgcal;
2875 UWORD16 apcoff;
2876 UWORD16 bulioff;
2877 UWORD16 bulqoff;
2878 UWORD16 dai_onoff;
2879 UWORD16 auxdac;
2880 UWORD16 vbctrl1;
2881 UWORD16 vbctrl2;
2882 UWORD16 apcdel1;
2883 UWORD16 apcdel2;
2884 UWORD16 vbpop;
2885 UWORD16 vau_delay_init;
2886 UWORD16 vaud_cfg;
2887 UWORD16 vauo_onoff;
2888 UWORD16 vaus_vol;
2889 UWORD16 vaud_pll;
2890 #endif
2891
2892 #if L1_GPRS
2893 UWORD16 toa_pm_thres; // PM threshold for TOA algorithm feeding in packet transfer mode
2894 #endif
2895 }
2896 T_L1_PARAMS;
2897
2898 typedef struct
2899 {
2900 T_L1_STD_CNFG std; //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT
2901 UWORD8 pwr_mngt; //power management active
2902 UWORD8 tx_pwr_code;
2903 UWORD16 dwnld;
2904 T_L1_PARAMS params;
2905 double dpll; //dpll factor
2906
2907 #if TESTMODE
2908 //Define the TestMode flag and TestMode parameters
2909 UWORD8 TestMode;
2910
2911 UWORD8 agc_enable;
2912 UWORD8 afc_enable;
2913 UWORD8 adc_enable;
2914
2915 T_TM_PARAMS tmode; //TestMode parameters structure
2916 #endif
2917
2918 }
2919 T_L1_CONFIG;
2920
2921 /***************************************************************************************/
2922 /* API HISR -> L1A communication structure... Defined in case dynamic download is defined */
2923 /***************************************************************************************/
2924 /***************************************************************************************/
2925 /* Global API HISR -Defined in case dynamic download is defined
2926 /***************************************************************************************/
2927
2928
2929 #if(L1_DYN_DSP_DWNLD==1)
2930 typedef struct
2931 {
2932 T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld;
2933 } T_L1A_API_HISR_COM;
2934
2935 typedef struct
2936 {
2937 T_L1_DYN_DWNLD_API_HISR dyn_dwnld;
2938 } T_L1_API_HISR;
2939 #endif