FreeCalypso > hg > fc-tourmaline
comparison src/cs/layer1/tpu_drivers/source0/tpudrv10.h @ 0:4e78acac3d88
src/{condat,cs,gpf,nucleus}: import from Selenite
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Fri, 16 Oct 2020 06:23:26 +0000 |
| parents | |
| children |
comparison
equal
deleted
inserted
replaced
| -1:000000000000 | 0:4e78acac3d88 |
|---|---|
| 1 /****************** Revision Controle System Header *********************** | |
| 2 * GSM Layer 1 software | |
| 3 * Copyright (c) Texas Instruments 1998 | |
| 4 * | |
| 5 * Filename tpudrv10.h | |
| 6 * Copyright 2003 (C) Texas Instruments | |
| 7 * | |
| 8 ****************** Revision Controle System Header ***********************/ | |
| 9 | |
| 10 #define BIT_0 0x000001 | |
| 11 #define BIT_1 0x000002 | |
| 12 #define BIT_2 0x000004 | |
| 13 #define BIT_3 0x000008 | |
| 14 #define BIT_4 0x000010 | |
| 15 #define BIT_5 0x000020 | |
| 16 #define BIT_6 0x000040 | |
| 17 #define BIT_7 0x000080 | |
| 18 #define BIT_8 0x000100 | |
| 19 #define BIT_9 0x000200 | |
| 20 #define BIT_10 0x000400 | |
| 21 #define BIT_11 0x000800 | |
| 22 #define BIT_12 0x001000 | |
| 23 #define BIT_13 0x002000 | |
| 24 #define BIT_14 0x004000 | |
| 25 #define BIT_15 0x008000 | |
| 26 #define BIT_16 0x010000 | |
| 27 #define BIT_17 0x020000 | |
| 28 #define BIT_18 0x040000 | |
| 29 #define BIT_19 0x080000 | |
| 30 #define BIT_20 0x100000 | |
| 31 #define BIT_21 0x200000 | |
| 32 #define BIT_22 0x400000 | |
| 33 #define BIT_23 0x800000 | |
| 34 | |
| 35 | |
| 36 //TRF6150 definitions | |
| 37 #define MODE0 0x000000 | |
| 38 #define MODE1 0x000001 | |
| 39 #define MODE2 0x000002 | |
| 40 #define MODE3 0x000003 | |
| 41 #define MODE4 0x000004 | |
| 42 #define MODE5 0x000005 | |
| 43 #define MODE6 0x000006 | |
| 44 #define MODE7 0x000007 | |
| 45 | |
| 46 #define REGUL_ON BIT_3 //MODE0 | |
| 47 #define BG_SPEEDUP BIT_4 //MODE0 | |
| 48 #define RX_ON_CLARA BIT_5 //MODE0 | |
| 49 #define TX_ON_CLARA BIT_6 //MODE0 | |
| 50 #define PA_CTRLR_ON BIT_7 //MODE0 | |
| 51 #define AUX_SYNTH_ON BIT_8 //MODE0 | |
| 52 #define MAIN_SYNTH_OFF 0x000000 //MODE0 | |
| 53 #define MAIN_SYNTH_ON_RX BIT_9 //MODE0 | |
| 54 #define MAIN_SYNTH_ON_TX BIT_10 //MODE0 | |
| 55 #define DCO_COMP_ON BIT_11 //MODE0 | |
| 56 #define DCO_COMP_RUN BIT_12 //MODE0 | |
| 57 #define BAND_SELECT_GSM BIT_13 //MODE0 | |
| 58 #define BAND_SELECT_850 BIT_13 //MODE0 | |
| 59 #define BAND_SELECT_PCS BIT_14 //MODE0 | |
| 60 #define BAND_SELECT_DCS (BIT_14 | BIT_13) | |
| 61 | |
| 62 #define RX_RF_GAIN BIT_15 //MODE0 | |
| 63 | |
| 64 // MODE1 is only for Receiver gain programming (AGC) | |
| 65 | |
| 66 #define AUX_SHDW_ADD(arfcn) ((arfcn >= 822) && (arfcn <= 885)) ? BIT_3 : 0 //MODE2 | |
| 67 #define AUX_SHDW_RCL BIT_4 //MODE2 | |
| 68 #define MAIN_FCU_REG_100 BIT_7 //MODE2 | |
| 69 #define PA_CTRL_I_DIOD BIT_23 //MODE2 | |
| 70 | |
| 71 //MODE3 | |
| 72 #define TEST_MODE BIT_3 //MODE3 | |
| 73 #define HB_OPLL_PRECHARGE BIT_4 //MODE3 | |
| 74 | |
| 75 #define HB_OPLL_CP_CUR_0_125MA 0x000000 //0.125 mA | |
| 76 #define HB_OPLL_CP_CUR_0_25MA BIT_5 //0.25 mA | |
| 77 #define HB_OPLL_CP_CUR_0_5MA BIT_6 //0.5 mA | |
| 78 #define HB_OPLL_CP_CUR_1MA (BIT_6 | BIT_5) //1 mA | |
| 79 #define HB_OPLL_CP_CUR_2MA BIT_7 //2 mA | |
| 80 | |
| 81 #define LB_OPLL_PRECHARGE BIT_8 //MODE3 | |
| 82 | |
| 83 #define LB_OPLL_CP_CUR_0_125MA 0x000000 //0.125 mA | |
| 84 #define LB_OPLL_CP_CUR_0_25MA BIT_9 //0.25 mA | |
| 85 #define LB_OPLL_CP_CUR_0_5MA BIT_10 //0.5 mA | |
| 86 #define LB_OPLL_CP_CUR_1MA (BIT_10 | BIT_9) //1 mA | |
| 87 #define LB_OPLL_CP_CUR_2MA BIT_11 //2 mA | |
| 88 | |
| 89 #define CLK_REF BIT_17 //MODE3 | |
| 90 #define MAIN_VCO_EN BIT_18 //MODE3 | |
| 91 #define AUX_VCO_EN BIT_19 //MODE3 | |
| 92 #define EXT_VCO_CONTROL BIT_20 //MODE3 | |
| 93 #define TEMP_SENSOR_EN BIT_21 //MODE3 | |
| 94 | |
| 95 //MODE4 | |
| 96 #define MAIN_TIMER_RX_49_2US BIT_6 //MODE4 | |
| 97 #define MAIN_TIMER_RX_55_35US ( 8 << 3) //added 30.01.02 | |
| 98 #define MAIN_TIMER_RX_61_5US (10 << 3) | |
| 99 #define MAIN_TIMER_RX_78_9US (13 << 3) | |
| 100 #define MAIN_TIMER_RX_91_9US (15 << 3) | |
| 101 #define MAIN_TIMER_RX_98_4US (16 << 3) | |
| 102 #define MAIN_TIMER_RX_159_9US (26 << 3) //added 21.08 CR | |
| 103 | |
| 104 | |
| 105 #define MAIN_TIMER_TX_49_2US BIT_11 //MODE4 | |
| 106 #define MAIN_TIMER_TX_61_5US (10 << 8) //added 30.01.02 | |
| 107 #define MAIN_TIMER_TX_104US (17 << 8) //added for RS | |
| 108 #define MAIN_TIMER_TX_98_4US (16 << 8) | |
| 109 #define MAIN_TIMER_TX_123US (20 << 8) //added 21.08 CR | |
| 110 | |
| 111 #define MAIN_CP_CUR_0 0x000000 //MODE4 400uA, 1.6mA | |
| 112 #define MAIN_CP_CUR_1 BIT_21 //MODE4 400uA, 3.2mA | |
| 113 #define MAIN_CP_CUR_2 BIT_22 //MODE4 800uA, 3.2mA | |
| 114 #define MAIN_CP_CUR_3 (BIT_22 | BIT_21)//MODE4 same as 2 | |
| 115 | |
| 116 #define FC_60 (60 << 13) | |
| 117 #define FC_63 (63 << 13) | |
| 118 #define FC_70 (70 << 13) | |
| 119 #define FC_100 (100 << 13) | |
| 120 #define FC_109 (109 << 13) | |
| 121 #define FC_110 (110 << 13) | |
| 122 | |
| 123 //MODE5 | |
| 124 #define SHDW_LOAD BIT_3 //MODE5 | |
| 125 #define AUX_PRG_MOD BIT_4 //MODE5 | |
| 126 #define AUX_PFD BIT_14 //MODE5 | |
| 127 | |
| 128 //MODE6 | |
| 129 #define FREQ_CAL_ON BIT_4 //MODE6 | |
| 130 #define FREQ_CAL_MODE BIT_5 //MODE6 | |
| 131 | |
| 132 //MODE7 | |
| 133 #define FREQ_CAL_DATA (0xd << 19) // 6.15 (00000)-8.88 (01101)-12.66 pF (11111)- modified CR 11.09.01, was (0xb << 19) | |
| 134 | |
| 135 | |
| 136 // RF signals connected to TSPACT [0..7] | |
| 137 //#define RESET_RF BIT_0 // act0 | |
| 138 #define CLA_SER_ON BIT_0 // act0 | |
| 139 #define CLA_SER_OFF 0 | |
| 140 #define TXVCO_ON 0 // act3 inverted | |
| 141 #define TXVCO_OFF BIT_3 | |
| 142 #define TX_ON BIT_5 // act5 | |
| 143 #define TX_OFF 0 | |
| 144 | |
| 145 // RF signals connected to TSPACT for Titanium v2.2 | |
| 146 #if 0 | |
| 147 //B-Sample | |
| 148 #define PA900_ON BIT_2 // signals are inverted therefore PA900_ON act1 | |
| 149 #define PA1800_ON BIT_1 // and PA1800_ON act2 | |
| 150 #define PA900_OFF BIT_1 // | |
| 151 #define PA1800_OFF BIT_2 // | |
| 152 #endif | |
| 153 | |
| 154 #if 0 | |
| 155 //C-Sample | |
| 156 #define PA900_ON BIT_1 // signals are inverted therefore PA900_ON act1 | |
| 157 #define PA1800_ON BIT_2 // and PA1800_ON act2 | |
| 158 #define PA900_OFF BIT_2 // | |
| 159 #define PA1800_OFF BIT_1 // | |
| 160 #endif | |
| 161 | |
| 162 #if 1 | |
| 163 //D-Sample | |
| 164 #define PA900_ON BIT_1 // signals are inverted therefore PA900_ON act1 | |
| 165 #define PA1800_ON BIT_2 // and PA1800_ON act2 | |
| 166 #define RX1900_ON 0 | |
| 167 #define PA900_OFF BIT_2 // | |
| 168 #define PA1800_OFF BIT_1 // | |
| 169 #define RX1900_OFF BIT_4 | |
| 170 | |
| 171 //RX_UP/DOWN and TX_UP/DOWN | |
| 172 #define RU_900 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 173 #define RD_900 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 174 #define TU_900 (PA900_ON | PA1800_OFF | RX1900_OFF) | |
| 175 #define TD_900 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 176 #define TU_REV_900 (PA900_OFF | PA1800_ON | RX1900_OFF) | |
| 177 | |
| 178 #define RU_850 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 179 #define RD_850 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 180 #define TU_850 (PA900_ON | PA1800_OFF | RX1900_OFF) | |
| 181 #define TD_850 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 182 #define TU_REV_850 (PA900_OFF | PA1800_ON | RX1900_OFF) | |
| 183 | |
| 184 #define RU_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 185 #define RD_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 186 #define TU_1800 (PA900_OFF | PA1800_ON | RX1900_OFF) | |
| 187 #define TD_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 188 #define TU_REV_1800 (PA900_ON | PA1800_OFF | RX1900_OFF) | |
| 189 | |
| 190 #define RU_1900 (PA900_OFF | PA1800_OFF | RX1900_ON) | |
| 191 #define RD_1900 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 192 #define TU_1900 (PA900_OFF | PA1800_ON | RX1900_OFF) | |
| 193 #define TD_1900 (PA900_OFF | PA1800_OFF | RX1900_OFF) | |
| 194 #define TU_REV_1900 (PA900_ON | PA1800_OFF | RX1900_OFF) | |
| 195 | |
| 196 | |
| 197 #endif | |
| 198 | |
| 199 #define TC1_DEVICE_ABB TC1_DEVICE0 | |
| 200 #define TC1_DEVICE_RF TC1_DEVICE2 | |
| 201 | |
| 202 | |
| 203 #define SL_SU_DELAY1 4 // No. bits to send + load data to shift + send write cmd + 1 | |
| 204 #define SL_SU_DELAY2 3 // load data to shift + send write cmd + 1 | |
| 205 #define SL_SU_DELAY3 5 // SL_SU_DELAY1 + serialization | |
| 206 | |
| 207 #define DLT 20 // (TRF6150) DownLoadTime | |
| 208 | |
| 209 #define DLT_1 1 // 1 tpu instruction = 1 qbit | |
| 210 #define DLT_2 2 | |
| 211 #define DLT_3 3 | |
| 212 | |
| 213 #define DLT_1B 4 // 3*move + 1*byte (download) | |
| 214 #define DLT_2B 6 // 4*move + 2*byte | |
| 215 #define DLT_3B 8 // 5*move + 3*byte | |
| 216 | |
| 217 //#define crch_timing 420//250//420//0 // CR d.07.08.01 - Temperary movement of Rx and Tx timing for Titanium. Will be set to 0 when new LF is ready. | |
| 218 #define rdt 0//359 // rx delta timing | |
| 219 #define tdt 0//293 // tx delta timing | |
| 220 | |
| 221 /*------------------------------------------*/ | |
| 222 /* Download delay values */ | |
| 223 /*------------------------------------------*/ | |
| 224 // 0.9230769 usec ~ 1 qbit i.e. 200 usec is ~ 217 qbit | |
| 225 | |
| 226 #define T TPU_CLOCK_RANGE | |
| 227 | |
| 228 #define TRF_I7 334 //qbit | |
| 229 #define TRF_I8 378 //qbit | |
| 230 | |
| 231 // time below are offset to when BDLENA goes low | |
| 232 #define TRF_R15 ( 0 - DLT_1B) // 0, BDLENA low, needs DLT_1B to execute | |
| 233 #define TRF_R13 ( - 32 - DLT_1B) // 8 right after, power off transceiver | |
| 234 | |
| 235 //burst data comes here | |
| 236 // time below are offset to when BDLENA goes high | |
| 237 #define TRF_R12 (PROVISION_TIME - 0 - DLT_1B) // BDLENA i/q comes 32qbit later | |
| 238 #define TRF_R10 (PROVISION_TIME - 8 - DLT_1B) // Set RX/TX switch (not really necessary as the default setting is RX mode) | |
| 239 #define TRF_R9 (PROVISION_TIME - 16 - DLT_2B) // RX_ON_CLARA | |
| 240 #define TRF_R7 (PROVISION_TIME - 66 - DLT_1B) // 67qbit duration BDLON + BDLCAL | |
| 241 #define TRF_R6 (PROVISION_TIME - 83 - DLT_1B) // BDLON, RX_ON_CLARA | |
| 242 #define TRF_R5 (PROVISION_TIME - 172 - DLT_2B - rdt) // DC offset comp. start LNA ON | |
| 243 //#define TRF_R4 (PROVISION_TIME - 172 - DLT_2B - rdt) // DC offset comp. LNA | |
| 244 #define TRF_R3 (PROVISION_TIME - 177 - DLT_2B - rdt) // DC offset comp. GAIN | |
| 245 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst | |
| 246 //#define TRF_R2_1 (PROVISION_TIME - 199 - DLT_2B - rdt) // fc | |
| 247 //#define TRF_R2 (PROVISION_TIME - 199 - DLT_2B - rdt) // select band | |
| 248 #define TRF_R1 (PROVISION_TIME - 209 - DLT_3B - rdt) // Main PLL + set of Main PLL FC & CP current | |
| 249 | |
| 250 | |
| 251 // time below are offset to when BULENA goes low | |
| 252 #define TRF_T17 ( 32 - SL_SU_DELAY2) // right after, BULON low | |
| 253 //#define TRF_T17 ( 32 ) // right after, BULON low | |
| 254 #define TRF_T16 ( 26 - DLT_1B) // Power down Clara | |
| 255 #define TRF_T15 ( 14 - DLT_1) // disable TX_ON | |
| 256 #define TRF_T14 ( 0 - DLT_1B) // BULENA off | |
| 257 #define TRF_T13_3 (- 40 - DLT_1B) // ADC read | |
| 258 //burst data comes here | |
| 259 // time below are offset to when BULENA goes high | |
| 260 #define TRF_T13_2 ( 25 - DLT_1) // TX_ON | |
| 261 #define TRF_T13_1 ( 17 - DLT_1) // set rf switch | |
| 262 #define TRF_T12 (- 0 - DLT_1B) // BULENA Start of TX burst | |
| 263 #define TRF_T10 (- 70 - DLT_3B - tdt) // normal speed | |
| 264 #define TRF_T9 (- 121 - DLT_2B - tdt) // Power up TXVCO | |
| 265 #define TRF_T8 (- 127 - DLT_1B - tdt) // BULON, disable BULCAL | |
| 266 #define TRF_T7 (- 127 - DLT_1B - tdt) // 131 BULON, disable BULCAL | |
| 267 #define TRF_T6 (- 137 - DLT_3B - tdt) // Speed up | |
| 268 #define TRF_T4 (- 249 - DLT_1B - tdt) // prog AUX PLL & detector polarity | |
| 269 #define TRF_T3_1 (- 258 - DLT_2B - tdt) // fc | |
| 270 #define TRF_T3 (- 258 - DLT_2B - tdt) // 20 BULON + BULCAL + select band | |
| 271 #define TRF_T2 (- 267 - DLT_3B - tdt) // set of Main PLL FC & CP current | |
| 272 #define TRF_T1 (- 277 - DLT_3B - tdt) // BULON + Main PLL | |
| 273 | |
| 274 | |
| 275 /*------------------------------------------*/ | |
| 276 /* Is arfcn in the DCS band (512-885) ? */ | |
| 277 /*------------------------------------------*/ | |
| 278 // is working only for GSM and DCS (not PCN) | |
| 279 #define IS_DCS_HIGH(arfcn) (((arfcn >= 576) && (arfcn <= 885))? 1 : 0) //Changed by CR 30.08.01, was (((arfcn >= 822) && (arfcn <= 885))? 1 : 0) | |
| 280 | |
| 281 #ifdef TPUDRV10_C | |
| 282 | |
| 283 #endif | |
| 284 | |
| 285 |