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comparison src/cs/system/main/gcc/bootentry.S @ 0:4e78acac3d88

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src/{condat,cs,gpf,nucleus}: import from Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 16 Oct 2020 06:23:26 +0000
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-1:000000000000 0:4e78acac3d88
1 /*
2 * This assembly module is our counterpart to TI's int.s: all boot entry
3 * point code that needs to be at the beginning of the flash resides here.
4 */
5
6 #include "asm_defs.h"
7 #include "fc-target.h"
8 #include "rf.cfg"
9
10 #if defined(FLASH) && !defined(CONFIG_TARGET_COMPAL)
11 /*
12 * Put something sensible in the boot ROM overlay area, just for the
13 * heck of it, or for extra robustness.
14 */
15 .section bootrom.overlay,"ax",%progbits
16 .code 32
17 .org 0
18 b BootROM_disabled_entry
19 #include "vectors.S"
20 BootROM_disabled_entry:
21 /* copy the boot ROM switch code to IRAM and jump to it */
22 ldr r4, =__romswitch_flash_addr
23 ldr r5, =__romswitch_ram_addr
24 ldr r2, =__romswitch_size
25 1: ldr r0, [r4], #4
26 str r0, [r5], #4
27 subs r2, r2, #4
28 bhi 1b
29 ldr pc, =__romswitch_ram_addr
30
31 .section bootrom.switch,"ax",%progbits
32 .code 32
33 .org 0
34 @ enable the Calypso boot ROM
35 ldr r1, =0xFFFFFB10
36 mov r2, #0x0100
37 strh r2, [r1]
38 @ jump to it!
39 mov pc, #0
40 #endif
41
42 .section .inttext,"ax",%progbits
43 .code 32
44
45 #ifdef FLASH
46 .org 0
47 #ifndef CONFIG_TARGET_COMPAL
48 /* sane targets with Calypso boot ROM enabled by the PCB wiring */
49 /* provide the necessary magic words for the boot ROM */
50 .word 0
51 .word _Firmware_boot_entry
52 #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \
53 defined(CONFIG_TARGET_J100)
54 /*
55 * On this target we'll put a patched version of Compal's boot code in
56 * flash sector 0 (the brickable one); the main fw images will then be
57 * flashed starting at 0x10000, which is where our modified boot code
58 * expects them to be. The interface between our hacked boot code and
59 * the main fw has been made to mimic TI's TCS211 reference fw.
60 */
61 #include "vectors.S"
62 .org 0x58 /* entry point at 0x10058 */
63 b _Firmware_boot_entry
64 #elif defined(CONFIG_TARGET_C155)
65 /*
66 * On this target the hand-off point between the bootloader and the main
67 * fw image coincides with a flash erase block boundary, thus we can reuse
68 * the original bootloader without having to reflash the brickable sector
69 * at all. The following bits will appear at 0x20000.
70 */
71 .asciz "FreeCalypso firmware for C155/156 target"
72 .org 0xE0
73 /* C155/156 bootloader jumps here */
74 b _Firmware_boot_entry
75 #include "vectors.S"
76 #else
77 #error "Unsupported flash boot configuration"
78 #endif
79 #endif
80
81 /* definitions from TI's int.s */
82
83 #define IRQ_STACK_SIZE 128
84 #define FIQ_STACK_SIZE 512
85 #define SYSTEM_SIZE 1024
86 #define TIMER_SIZE 1024
87 #define TIMER_PRIORITY 2
88
89 @ TI's literal pool before the entry point
90
91 addrCS0: .word 0xfffffb00 @ CS0 address space
92
93 EX_MPU_CONF_REG: .word 0xFFFEF006 @ Extended MPU configuration register address
94 EX_FLASH_VALUE: .short 0x0008 @ set bit to enable A22
95
96 .balign 4
97
98 CNTL_ARM_CLK_REG: .word 0xFFFFFD00 @ CNTL_ARM_CLK register address
99 DPLL_CNTRL_REG: .word 0xFFFF9800 @ DPLL control register address
100 EXTRA_CONTROL_REG: .word 0xFFFFFB10 @ Extra Control register CONF address
101 MPU_CTL_REG: .word 0xFFFFFF08 @ MPU_CTL register address
102
103 CNTL_ARM_CLK_RST: .short 0x1081 @ Initialization of CNTL_ARM_CLK register
104 @ Use DPLL, Divide by 1
105 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state
106 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module
107 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module
108 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled
109
110 @ FreeCalypso change, please see MEMIF-wait-states document
111 @ in the freecalypso-docs repository for the explanation.
112
113 #if (RF_FAM == 12)
114 CS0_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
115 CS1_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
116 CS2_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
117 #else
118 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
119 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
120 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
121 #endif
122 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable
123 CS4_MEM_REG: .short 0xe85 @ default reset value
124 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable
125 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
126 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation
127
128 .balign 4
129
130 .globl _Firmware_boot_entry
131 _Firmware_boot_entry:
132 @ TI's code from int.s follows
133
134 @
135 @ Configure DPLL register with reset value
136 @
137 ldr r1,DPLL_CNTRL_REG @ Load address of DPLL register in R1
138 ldrh r2,DPLL_CONTROL_RST @ Load DPLL reset value in R2
139 strh r2,[r1] @ Store DPLL reset value in DPLL register
140
141 @
142 @ Wait that DPLL goes in BYPASS mode
143 @
144 Wait_DPLL_Bypass:
145 ldr r2,[r1] @ Load DPLL register
146 and r2,r2,#1 @ Perform a mask on bit 0
147 cmp r2,#1 @ Compare DPLL lock bit
148 beq Wait_DPLL_Bypass @ Wait Bypass mode (i.e. bit[0]='0')
149
150 @
151 @ Configure CNTL_ARM_CLK register with reset value: DPLL is used to
152 @ generate ARM clock with division factor of 1.
153 @
154 ldr r1,CNTL_ARM_CLK_REG @ Load address of CNTL_ARM_CLK register in R1
155 ldrh r2,CNTL_ARM_CLK_RST @ Load CNTL_ARM_CLK reset value in R2
156 strh r2,[r1] @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
157
158 @
159 @ Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
160 @
161 ldr r1,EXTRA_CONTROL_REG @ Load address of Extra Control register CONF
162 ldrh r2,ENABLE_DU_MASK @ Load mask to write in Extra Control register CONF
163 ldrh r0,[r1] @ Load Extra Control register CONF in r0
164 and r0,r0,r2 @ Enable DU module
165 strh r0,[r1] @ Store configuration in Extra Control register CONF
166
167 @
168 @ Disable all MPU protections
169 @
170 ldr r1,MPU_CTL_REG @ Load address of MPU_CTL register
171 ldrh r2,MPU_CTL_RST @ Load reset value of MPU_CTL register
172 strh r2,[r1] @ Store reset value of MPU_CTL register
173
174 @ MEMIF timing setup
175
176 ldr r1,addrCS0
177 ldrh r2,CS0_MEM_REG @ ROM initialization
178 strh r2,[r1] @ CS0
179
180 ldrh r2,CS1_MEM_REG @ RAM Initialization
181 strh r2,[r1,#2] @ CS1
182
183 ldrh r2,CS2_MEM_REG @ RAM Initialization
184 strh r2,[r1,#4] @ CS2
185
186 ldrh r2,CS3_MEM_REG @ Parallel I/O on B-Sample
187 strh r2,[r1,#6] @ CS3 (unused on EVA4?)
188
189 ldrh r2,CS4_MEM_REG @ Latch on B-Sample
190 strh r2,[r1,#0xa] @ CS4 (unused on EVA4)
191
192 ldrh r2,CS6_MEM_REG @ Internal SRAM initialization
193 strh r2,[r1,#0xc] @ CS6 Internal RAM
194
195 ldrh r2,CS7_MEM_REG @ Internal SRAM initialization
196 strh r2,[r1,#0x8] @ CS7 Internal Boot ROM
197
198 ldrh r2,CTL_MEM_REG @ API-RHEA configuration
199 strh r2,[r1,#0xe]
200
201 @ enable ADD22
202
203 ldr r1,EX_MPU_CONF_REG
204 ldrh r2,[r1]
205 ldr r0,EX_FLASH_VALUE
206 orr r0, r0, r2
207 strh r0,[r1]
208
209 /* Ensure that the processor is in supervisor mode. */
210
211 MRS a1,CPSR @ Pickup current CPSR
212 BIC a1,a1,#MODE_MASK @ Clear the mode bits
213 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
214 ORR a1,a1,#LOCKOUT @ Ensure IRQ and FIQ interrupts are
215 @ locked out
216 MSR CPSR,a1 @ Setup the new CPSR
217
218 /*
219 * FreeCalypso Selenite: if this is a flash build,
220 * copy IRAM code and .data from flash to RAM.
221 */
222
223 #ifdef FLASH
224 /* copy iram.text to where it's supposed to be */
225 ldr r8, =__iramtext_flash_addr
226 ldr r9, =__iramtext_ram_addr
227 ldr r10, =__iramtext_size
228 1: ldmia r8!, {r0-r7}
229 stmia r9!, {r0-r7}
230 subs r10, r10, #0x20
231 bhi 1b
232 /* likewise copy .data from flash to XRAM */
233 ldr r8, =__initdata_flash_addr
234 ldr r9, =__initdata_ram_addr
235 ldr r10, =__initdata_size
236 1: ldmia r8!, {r0-r7}
237 stmia r9!, {r0-r7}
238 subs r10, r10, #0x20
239 bhi 1b
240 #endif
241
242 /* Both flash and XRAM builds: zero .bss */
243
244 ldr r0, =__intbss_start
245 ldr r1, =__intbss_size
246 bl bzero
247 ldr r0, =__extbss_start
248 ldr r1, =__extbss_size
249 bl bzero
250
251 @ TI's int.s code continues
252
253 @
254 @ Initialize the system stack pointers. This is done after the BSS is
255 @ cleared because the TCD_System_Stack pointer is a BSS variable! It is
256 @ assumed that the .cmd file is written to direct where these stacks should
257 @ be allocated and to align them on double word boundaries.
258 @
259 LDR a1,StackSegment @ Pickup the begining address from .cmd file
260 @ (is aligned on 8 byte boundary)
261 MOV a2,#SYSTEM_SIZE @ Pickup system stack size
262 SUB a2,a2,#4 @ Subtract one word for first addr
263 ADD a3,a1,a2 @ Build start of system stack area
264 MOV v7,a1 @ Setup initial stack limit
265 LDR a4,System_Limit @ Pickup system stack limit address
266 STR v7,[a4, #0] @ Save stack limit
267 MOV sp,a3 @ Setup initial stack pointer
268 LDR a4,System_Stack @ Pickup system stack address
269 STR sp,[a4, #0] @ Save stack pointer
270 MOV a2,#IRQ_STACK_SIZE @ Pickup IRQ stack size in bytes
271 ADD a3,a3,a2 @ Allocate IRQ stack area
272 MRS a1,CPSR @ Pickup current CPSR
273 BIC a1,a1,#MODE_MASK @ Clear the mode bits
274 ORR a1,a1,#IRQ_MODE @ Set the IRQ mode bits
275 MSR CPSR,a1 @ Move to IRQ mode
276 MOV sp,a3 @ Setup IRQ stack pointer
277 MOV a2,#FIQ_STACK_SIZE @ Pickup FIQ stack size in bytes
278 ADD a3,a3,a2 @ Allocate FIQ stack area
279 MRS a1,CPSR @ Pickup current CPSR
280 BIC a1,a1,#MODE_MASK @ Clear the mode bits
281 ORR a1,a1,#FIQ_MODE @ Set the FIQ mode bits
282 MSR CPSR,a1 @ Move to the FIQ mode
283 MOV sp,a3 @ Setup FIQ stack pointer
284
285 MRS a1,CPSR @ Pickup current CPSR
286 BIC a1,a1,#MODE_MASK @ Clear the mode bits
287 ORR a1,a1,#ABORT_MODE @ Set the Abort mode bits
288 MSR CPSR,a1 @ Move to the Abort mode
289 LDR sp,Exception_Stack @ Setup Abort stack pointer
290
291 MRS a1,CPSR @ Pickup current CPSR
292 BIC a1,a1,#MODE_MASK @ Clear the mode bits
293 ORR a1,a1,#UNDEF_MODE @ Set the Undefined mode bits
294 MSR CPSR,a1 @ Move to the Undefined mode
295 LDR sp,Exception_Stack @ Setup Undefined stack pointer
296 @ (should never be used)
297
298 @ go to Supervisor Mode
299 MRS a1,CPSR @ Pickup current CPSR
300 BIC a1,a1,#MODE_MASK @ Clear mode bits
301 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
302 MSR CPSR,a1 @ All interrupt stacks are setup,
303 @ return to supervisor mode
304 @
305 @ /* Define the global data structures that need to be initialized by this
306 @ routine. These structures are used to define the system timer
307 @ management HISR. */
308 @ TMD_HISR_Stack_Ptr = (VOID *) a3;
309 @ TMD_HISR_Stack_Size = TIMER_SIZE;
310 @ TMD_HISR_Priority = TIMER_PRIORITY;
311 @
312 @ TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated
313 @ area. The Timer HISR (called "SYSTEM H") and its related stack will be created
314 @ in TMI_Initialize(). The current stack pointer will be set at the bottom (the
315 @ lowest address) of the expected area.
316
317 LDR a4,HISR_Stack_Ptr @ Pickup variable's address
318 ADD a3,a3,#4 @ Increment to next available word
319 STR a3,[a4, #0] @ Setup timer HISR stack pointer
320 MOV a2,#TIMER_SIZE @ Pickup the timer HISR stack size
321 BIC a2,a2,#3 @ Insure word alignment
322 ADD a3,a3,a2 @ Allocate the timer HISR stack
323 @ from available memory
324 LDR a4,HISR_Stack_Size @ Pickup variable's address
325 STR a2,[a4, #0] @ Setup timer HISR stack size
326 MOV a2,#TIMER_PRIORITY @ Pickup timer HISR priority (0-2)
327 LDR a4,HISR_Priority @ Pickup variable's address
328 STR a2,[a4, #0] @ Setup timer HISR priority
329
330 /* TI's original code called f_load_int_mem() at this point */
331 /* let's do our internal ROM enable step here */
332
333 ldr r1, EXTRA_CONTROL_REG
334 ldrh r0, [r1, #0]
335 bic r0, #0x0300
336 orr r0, #0x0100
337 strh r0, [r1, #0]
338
339 @ We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for
340 @ checking the status of the stacks later.
341 @ inputs:
342 @ a3 still has the bottom of all four stacks and is aligned.
343 @ algorithm:
344 @ We start from the top of all four stacks (*System_Limit), which is
345 @ necessarily aligned. We store 0xFEFEFEFE until we have filled the
346 @ bottom of the fourth stack
347 @ outputs:
348 @ memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR
349 @ a3 still has the bottom of all four stacks
350
351 LDR a2,System_Limit @ pickup system stack limit address
352 LDR a1,[a2] @ a1 = StackSegment
353 LDR a4,=0xFEFEFEFE
354
355 fill_stack:
356 STR a4,[a1],#4 @ store a word and increment by four
357 CMP a1,a3 @ is this the last address?
358 BLT fill_stack @ if not, loop back
359
360 @
361 @ /* Call INC_Initialize with a pointer to the first available memory
362 @ address after the compiler's global data. This memory may be used
363 @ by the application. */
364 @ INC_Initialize(first_available_memory);
365 @
366 MOV a1,a3 @ Pass the first available memory
367 B INC_Initialize @ to high-level initialization
368
369 @ literal pool from int.s (after the code)
370
371 StackSegment:
372 .word _Stack_segment_start
373
374 System_Limit:
375 .word TCT_System_Limit
376
377 System_Stack:
378 .word TCD_System_Stack
379
380 HISR_Stack_Ptr:
381 .word TMD_HISR_Stack_Ptr
382
383 HISR_Stack_Size:
384 .word TMD_HISR_Stack_Size
385
386 HISR_Priority:
387 .word TMD_HISR_Priority
388
389 Exception_Stack:
390 .word _Except_Stack_SP