comparison src/cs/drivers/drv_app/sim/sim.c @ 191:c1205c437943

../drv_app/sim/sim.c: white space fixes
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 30 Jan 2021 07:34:00 +0000
parents b37e6c916df1
children
comparison
equal deleted inserted replaced
190:2e4afc93045d 191:c1205c437943
42 //current voltage mode 3V or 5V, or 1.8V 42 //current voltage mode 3V or 5V, or 1.8V
43 SYS_UWORD8 CurrentVolt; 43 SYS_UWORD8 CurrentVolt;
44 44
45 /* FreeCalypso addition */ 45 /* FreeCalypso addition */
46 SYS_UWORD8 SIM_allow_speed_enhancement = 1; 46 SYS_UWORD8 SIM_allow_speed_enhancement = 1;
47
48 47
49 48
50 #ifdef SIM_DEBUG_TRACE 49 #ifdef SIM_DEBUG_TRACE
51 50
52 #ifdef SIM_RETRY 51 #ifdef SIM_RETRY
82 /* Add variables to support sim retry */ 81 /* Add variables to support sim retry */
83 SYS_UWORD8 SimRetries; 82 SYS_UWORD8 SimRetries;
84 #endif 83 #endif
85 84
86 85
87
88
89
90
91 /* 86 /*
92 * Low level routines : mapped to hardware 87 * Low level routines : mapped to hardware
93 * SIM_WriteBuffer 88 * SIM_WriteBuffer
94 * SIM_Command 89 * SIM_Command
95 * SIM_Reset 90 * SIM_Reset
96 * 91 *
97 */ 92 */
98
99 93
100 94
101 /* 95 /*
102 * SIM_WriteBuffer 96 * SIM_WriteBuffer
103 * 97 *
158 return (SIM_ERR_XMIT); 152 return (SIM_ERR_XMIT);
159 153
160 len = p->rx_index; 154 len = p->rx_index;
161 *lenP = len - offset; 155 *lenP = len - offset;
162 if ((*lenP == 0) && (p->apdu_ans_length == 256)) 156 if ((*lenP == 0) && (p->apdu_ans_length == 256))
163 *lenP = 256; 157 *lenP = 256;
164 158
165 if (p->expected_data == 256) 159 if (p->expected_data == 256)
166 { 160 {
167 verdict = SIM_Memcpy(rP, ((p->rbuf) + offset), 256 - offset); 161 verdict = SIM_Memcpy(rP, ((p->rbuf) + offset), 256 - offset);
168 if (verdict != 0) 162 if (verdict != 0)
185 179
186 return((sw1 << 8) | sw2); 180 return((sw1 << 8) | sw2);
187 } 181 }
188 182
189 183
190
191
192
193 /* 184 /*
194 * SIM_Command_base 185 * SIM_Command_base
195 * 186 *
196 * Perform a command with the SIM T=0 protocol 187 * Perform a command with the SIM T=0 protocol
197 * 188 *
202 * Returns an error code : 193 * Returns an error code :
203 * SIM_ERR_READ : no answer from the card to a command 194 * SIM_ERR_READ : no answer from the card to a command
204 * SIM_ERR_LEN : the answer is not corresponding to a 195 * SIM_ERR_LEN : the answer is not corresponding to a
205 * correct answer of T=0 protocol 196 * correct answer of T=0 protocol
206 * 06/11/2002 JYT 197 * 06/11/2002 JYT
207 * Modified to be base command function. New SIM_Command() created to call it 198 * Modified to be base command function. New SIM_Command() created to call it
208 * with wrapper. Created to manage retries on Internals errors of the driver. 199 * with wrapper. Created to manage retries on Internals errors of the driver.
209 */ 200 */
210 201
211 SYS_UWORD16 SIM_Command_Base(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *dP, SYS_UWORD16 *lP) 202 SYS_UWORD16 SIM_Command_Base(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *dP, SYS_UWORD16 *lP)
212 { 203 {
213 SYS_UWORD16 res; 204 SYS_UWORD16 res;
312 } 303 }
313 } 304 }
314 305
315 res = SIM_Result(p, dP, lP, 0); 306 res = SIM_Result(p, dP, lP, 0);
316 307
317 if ((SIM_sleep_status == SIM_SLEEP_DESACT) || (SIM_sleep_status == SIM_SLEEP_ACT)) 308 if ((SIM_sleep_status == SIM_SLEEP_DESACT) || (SIM_sleep_status == SIM_SLEEP_ACT))
318 { //enable to count 2.5s before entering in sleep mode 309 { //enable to count 2.5s before entering in sleep mode
319 status_os_sim = NU_Reset_Timer (&SIM_timer, SIM_SleepMode_In, 310 status_os_sim = NU_Reset_Timer (&SIM_timer, SIM_SleepMode_In,
320 SIM_SLEEP_WAITING_TIME, 311 SIM_SLEEP_WAITING_TIME,
321 0, NU_ENABLE_TIMER); 312 0, NU_ENABLE_TIMER);
322 } 313 }
324 return(res); 315 return(res);
325 } 316 }
326 317
327 318
328 /* Main function to manage the retry mechanism */ 319 /* Main function to manage the retry mechanism */
329 SYS_UWORD16 SIM_Command(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *dP, SYS_UWORD16 *lP) { 320 SYS_UWORD16 SIM_Command(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *dP, SYS_UWORD16 *lP)
330 int res; 321 {
322 int res;
331 323
332 #ifdef SIM_DEBUG_TRACE 324 #ifdef SIM_DEBUG_TRACE
333 memset(SIM_dbg_null, 0x00, SIM_DBG_NULL); 325 memset(SIM_dbg_null, 0x00, SIM_DBG_NULL);
334 SIM_dbg_tdma_diff = 0; 326 SIM_dbg_tdma_diff = 0;
335 #endif 327 #endif
336 328
337 // Issue initial SIM_Command() call 329 // Issue initial SIM_Command() call
338 res = SIM_Command_Base(p, n, dP, lP); 330 res = SIM_Command_Base(p, n, dP, lP);
339 /* Change from to 10 to 15 for specific SIM card (Racal) */ 331 /* Change from to 10 to 15 for specific SIM card (Racal) */
340 332
341 #ifdef SIM_RETRY 333 #ifdef SIM_RETRY
342 // While there is an error then retry NUM_SIM_RETRIES times 334 // While there is an error then retry NUM_SIM_RETRIES times
343 while ((res & 0xFF00) == 0) { // Reissue command 335 while ((res & 0xFF00) == 0) { // Reissue command
344 p->errorSIM = 0; 336 p->errorSIM = 0;
345 if(++SimRetries > NUM_SIM_RETRIES) { // return special retry failure 337 if(++SimRetries > NUM_SIM_RETRIES) { // return special retry failure
346 res = SIM_ERR_RETRY_FAILURE; 338 res = SIM_ERR_RETRY_FAILURE;
347 break; 339 break;
348 }
349 res = SIM_Command_Base(p, n, dP, lP);
350 } 340 }
341 res = SIM_Command_Base(p, n, dP, lP);
342 }
351 343
352 #ifdef SIM_DEBUG_TRACE 344 #ifdef SIM_DEBUG_TRACE
353 SIM_dbg_null[SIM_DBG_NULL-1] = SimRetries; 345 SIM_dbg_null[SIM_DBG_NULL-1] = SimRetries;
354 #endif 346 #endif
355 347
356 SimRetries = 0; 348 SimRetries = 0;
357 #endif 349 #endif
358 350
359 return(res); 351 return(res);
360 } 352 }
361
362
363
364
365 353
366 354
367 /* 355 /*
368 * SIM_ByteReverse 356 * SIM_ByteReverse
369 * 357 *
373 SYS_UWORD8 SIM_ByteReverse(SYS_UWORD8 b) 361 SYS_UWORD8 SIM_ByteReverse(SYS_UWORD8 b)
374 { 362 {
375 SYS_UWORD8 bh, bl; 363 SYS_UWORD8 bh, bl;
376 int i; 364 int i;
377 const SYS_UWORD8 Reverse[] = {0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE, 365 const SYS_UWORD8 Reverse[] = {0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
378 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF }; 366 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF };
379 367
380 // Up/Down 368 // Up/Down
381 b = ~ b; 369 b = ~ b;
382 370
383 // left / right (by nibble) 371 // left / right (by nibble)
384 bh = (b >> 4) & 0xF; 372 bh = (b >> 4) & 0xF;
385 bl = b & 0xF; 373 bl = b & 0xF;
386 374
387 b = (Reverse[bl]) << 4 | Reverse[bh]; 375 b = (Reverse[bl]) << 4 | Reverse[bh];
388 return(b); 376 return(b);
389
390 } 377 }
391 378
392 /* 379 /*
393 * SIM_TxParityErrors 380 * SIM_TxParityErrors
394 * 381 *
398 */ 385 */
399 SYS_UWORD16 SIM_TxParityErrors(void) 386 SYS_UWORD16 SIM_TxParityErrors(void)
400 { 387 {
401 SIM_PORT *p; 388 SIM_PORT *p;
402 389
403 p= &(Sim[0]); 390 p = &(Sim[0]);
404 391
405 return(p->txParityErr); 392 return(p->txParityErr);
406 } 393 }
407 394
408 395
427 { 414 {
428 return(SIM_Reset_Restart_Internal(cP, 1)); 415 return(SIM_Reset_Restart_Internal(cP, 1));
429 } 416 }
430 417
431 418
432
433
434
435
436
437 /* 419 /*
438 * SIM_Restart 420 * SIM_Restart
439 * 421 *
440 * Restart SIM card 422 * Restart SIM card
441 * 423 *
477 unsigned int ATR_Attempt; 459 unsigned int ATR_Attempt;
478 SYS_UWORD8 BackValue; 460 SYS_UWORD8 BackValue;
479 SYS_UWORD8 Result_ATR; 461 SYS_UWORD8 Result_ATR;
480 462
481 #ifdef SIM_DEBUG_TRACE 463 #ifdef SIM_DEBUG_TRACE
482 memset(SIM_dbg_null, 0x00, SIM_DBG_NULL); 464 memset(SIM_dbg_null, 0x00, SIM_DBG_NULL);
483 SIM_dbg_cmd_cmpt = 0; 465 SIM_dbg_cmd_cmpt = 0;
484 memset(SIM_dbg_cmd, 0x00, SIM_DBG_CMD); 466 memset(SIM_dbg_cmd, 0x00, SIM_DBG_CMD);
485 #endif 467 #endif
486 468
487 // Initialize pointers 469 // Initialize pointers
488 p = &(Sim[0]); 470 p = &(Sim[0]);
489 471
565 return (SIM_ERR_NOCARD); 547 return (SIM_ERR_NOCARD);
566 } 548 }
567 // ATR received but wrong characters value 549 // ATR received but wrong characters value
568 // Comply with Test 27.11.2.4.5 and Test 27.11.1.3 550 // Comply with Test 27.11.2.4.5 and Test 27.11.1.3
569 else if (BackValue == SIM_ERR_CARDREJECT) 551 else if (BackValue == SIM_ERR_CARDREJECT)
552 {
553 if (ATR_Attempt >= 3)
570 { 554 {
571 if (ATR_Attempt >= 3)
572 {
573 SIM_PowerOff (); 555 SIM_PowerOff ();
574 return ((SYS_UWORD16)BackValue); 556 return ((SYS_UWORD16)BackValue);
575 } 557 }
576 558
577 ATR_Attempt++; 559 ATR_Attempt++;
578 SIM_WARMReset(p); // assert a reset during at least 400 ETU 560 SIM_WARMReset(p); // assert a reset during at least 400 ETU
579 } 561 }
580 else if (BackValue != 0) //SIM_ERR_WAIT 562 else if (BackValue != 0) //SIM_ERR_WAIT
581 { 563 {
582 if (ATR_Attempt == 3) 564 if (ATR_Attempt == 3)
583 { // switch to 5V (ANALOG1) or 3V (ANALOG2) if card send wrong ATR 3 consecutive times 565 { // switch to 5V (ANALOG1) or 3V (ANALOG2) if card send wrong ATR 3 consecutive times
584 // Apply 3 consecutive resets at 5V (ANALOG1) or 3V (ANALOG2) 566 // Apply 3 consecutive resets at 5V (ANALOG1) or 3V (ANALOG2)
585 // fix prb for old chinese card not GSM compliant 567 // fix prb for old chinese card not GSM compliant
586 568
713 } 695 }
714 696
715 status_os_sim = NU_Control_Timer (&SIM_timer, NU_ENABLE_TIMER); 697 status_os_sim = NU_Control_Timer (&SIM_timer, NU_ENABLE_TIMER);
716 //enable starting of the os timer for sleep mode 698 //enable starting of the os timer for sleep mode
717 if (ResetFlag) { 699 if (ResetFlag) {
718 if (p->InsertFunc != NULL) 700 if (p->InsertFunc != NULL)
719 (p->InsertFunc)(cP); 701 (p->InsertFunc)(cP);
720 } 702 }
721 703
722 return(0); 704 return(0);
723 } 705 }
724
725
726
727
728
729
730
731
732
733 706
734 707
735 /* SIM manual start 708 /* SIM manual start
736 * 709 *
737 * purpose : manage manual start of the SIM interface 710 * purpose : manage manual start of the SIM interface
756 729
757 // Unmask interrupt controller 730 // Unmask interrupt controller
758 IQ_Unmask (IQ_SIM); 731 IQ_Unmask (IQ_SIM);
759 732
760 p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_STOP; 733 p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_STOP;
761 ind_os_sleep (4); //wait 5 TDMA due to SVCC falling down duration 734 ind_os_sleep (4); //wait 5 TDMA due to SVCC falling down duration
762 735
763 p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_SWRST; 736 p->c->cmd = (p->c->cmd & MASK_CMD) | SIM_CMD_SWRST;
764 ind_os_sleep (1); //wait 5 TDMA due to SVCC falling down duration 737 ind_os_sleep (1); //wait 5 TDMA due to SVCC falling down duration
765 738
766 739
767 p->c->conf2 = 0x0940; 740 p->c->conf2 = 0x0940;
768 741
769 i = p->c->it; 742 i = p->c->it;
855 { 828 {
856 SIM_PORT *p; 829 SIM_PORT *p;
857 volatile SYS_UWORD16 cmd; 830 volatile SYS_UWORD16 cmd;
858 831
859 832
860
861 // Initialize pointers 833 // Initialize pointers
862 p = &(Sim[0]); 834 p = &(Sim[0]);
863 835
864 836
865 // Reset and wait a while 837 // Reset and wait a while
1078 */ 1050 */
1079 SYS_UWORD16 SIM_Status_Extended(SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 1051 SYS_UWORD16 SIM_Status_Extended(SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
1080 { 1052 {
1081 SIM_PORT *p; 1053 SIM_PORT *p;
1082 int res; 1054 int res;
1083 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 1055 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
1084 1056
1085 p = &(Sim[0]); 1057 p = &(Sim[0]);
1086 1058
1087 p->xbuf[0] = GSM_CLASS; 1059 p->xbuf[0] = GSM_CLASS;
1088 p->xbuf[1] = SIM_STATUS; 1060 p->xbuf[1] = SIM_STATUS;
1118 */ 1090 */
1119 SYS_UWORD16 SIM_ReadBinary(SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 1091 SYS_UWORD16 SIM_ReadBinary(SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
1120 { 1092 {
1121 SIM_PORT *p; 1093 SIM_PORT *p;
1122 int res; 1094 int res;
1123 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 1095 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
1124 1096
1125 p = &(Sim[0]); 1097 p = &(Sim[0]);
1126 1098
1127 p->xbuf[0] = GSM_CLASS; 1099 p->xbuf[0] = GSM_CLASS;
1128 p->xbuf[1] = SIM_READ_BINARY; 1100 p->xbuf[1] = SIM_READ_BINARY;
1155 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); 1127 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff);
1156 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 1128 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
1157 #endif 1129 #endif
1158 1130
1159 return(res); 1131 return(res);
1160
1161 } 1132 }
1162 1133
1163 1134
1164 /* 1135 /*
1165 * SIM_VerifyChv 1136 * SIM_VerifyChv
1261 #endif 1232 #endif
1262 1233
1263 if(p->Freq_Algo) 1234 if(p->Freq_Algo)
1264 p->c->conf1 = p->conf1 |= SIM_CONF1_SCLKDIV; 1235 p->c->conf1 = p->conf1 |= SIM_CONF1_SCLKDIV;
1265 1236
1266
1267 return(res); 1237 return(res);
1268 } 1238 }
1269 1239
1270 1240
1271 /* 1241 /*
1277 */ 1247 */
1278 SYS_UWORD16 SIM_GetResponse(SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 1248 SYS_UWORD16 SIM_GetResponse(SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
1279 { 1249 {
1280 SIM_PORT *p; 1250 SIM_PORT *p;
1281 int res; 1251 int res;
1282 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 1252 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
1283 1253
1284 p = &(Sim[0]); 1254 p = &(Sim[0]);
1285 1255
1286 p->xbuf[0] = GSM_CLASS; 1256 p->xbuf[0] = GSM_CLASS;
1287 p->xbuf[1] = SIM_GET_RESPONSE; 1257 p->xbuf[1] = SIM_GET_RESPONSE;
1413 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); 1383 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff);
1414 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 1384 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
1415 #endif 1385 #endif
1416 1386
1417 return(res); 1387 return(res);
1418
1419 } 1388 }
1420 1389
1421 1390
1422 /* 1391 /*
1423 * SIM_EnableCHV 1392 * SIM_EnableCHV
1469 1438
1470 return(res); 1439 return(res);
1471 } 1440 }
1472 1441
1473 1442
1474
1475 /* 1443 /*
1476 * SIM_UnblockCHV 1444 * SIM_UnblockCHV
1477 * 1445 *
1478 * Unblock the specified CHV (chvType) and store a new CHV 1446 * Unblock the specified CHV (chvType) and store a new CHV
1479 */ 1447 */
1523 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 1491 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
1524 #endif 1492 #endif
1525 1493
1526 return(res); 1494 return(res);
1527 } 1495 }
1496
1528 /* 1497 /*
1529 * SIM_Invalidate 1498 * SIM_Invalidate
1530 * 1499 *
1531 * Invalidate the current EF 1500 * Invalidate the current EF
1532 */ 1501 */
1565 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 1534 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
1566 #endif 1535 #endif
1567 1536
1568 return(res); 1537 return(res);
1569 } 1538 }
1539
1570 /* 1540 /*
1571 * SIM_Rehabilitate 1541 * SIM_Rehabilitate
1572 * 1542 *
1573 * Rehabilitate the current EF 1543 * Rehabilitate the current EF
1574 */ 1544 */
1606 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); 1576 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff);
1607 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 1577 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
1608 #endif 1578 #endif
1609 1579
1610 return(res); 1580 return(res);
1611
1612 } 1581 }
1613 1582
1614 1583
1615 /* 1584 /*
1616 * SIM_UpdateBinary 1585 * SIM_UpdateBinary
1620 SYS_UWORD16 SIM_UpdateBinary(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 1589 SYS_UWORD16 SIM_UpdateBinary(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
1621 { 1590 {
1622 SIM_PORT *p; 1591 SIM_PORT *p;
1623 int i; 1592 int i;
1624 int res; 1593 int res;
1625 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 1594 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
1626 1595
1627 p = &(Sim[0]); 1596 p = &(Sim[0]);
1628 1597
1629 p->xbuf[0] = GSM_CLASS; 1598 p->xbuf[0] = GSM_CLASS;
1630 p->xbuf[1] = SIM_UPDATE_BINARY; 1599 p->xbuf[1] = SIM_UPDATE_BINARY;
1656 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); 1625 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff);
1657 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 1626 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
1658 #endif 1627 #endif
1659 1628
1660 return(res); 1629 return(res);
1661
1662 } 1630 }
1663 1631
1664 1632
1665 /* 1633 /*
1666 * SIM_ReadRecord 1634 * SIM_ReadRecord
1669 */ 1637 */
1670 SYS_UWORD16 SIM_ReadRecord(SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 1638 SYS_UWORD16 SIM_ReadRecord(SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
1671 { 1639 {
1672 SIM_PORT *p; 1640 SIM_PORT *p;
1673 int res; 1641 int res;
1674 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 1642 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
1675 1643
1676 p = &(Sim[0]); 1644 p = &(Sim[0]);
1677 1645
1678 p->xbuf[0] = GSM_CLASS; 1646 p->xbuf[0] = GSM_CLASS;
1679 p->xbuf[1] = SIM_READ_RECORD; 1647 p->xbuf[1] = SIM_READ_RECORD;
1701 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); 1669 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff);
1702 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 1670 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
1703 #endif 1671 #endif
1704 1672
1705 return(res); 1673 return(res);
1706
1707 } 1674 }
1708 1675
1709 #ifdef SIM_APDU_TEST 1676 #ifdef SIM_APDU_TEST
1710 SYS_UWORD8 snd[270]; 1677 SYS_UWORD8 snd[270];
1711 SYS_UWORD8 rec[270]; 1678 SYS_UWORD8 rec[270];
1728 SYS_UWORD16 SIM_UpdateRecord(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 1695 SYS_UWORD16 SIM_UpdateRecord(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
1729 { 1696 {
1730 SIM_PORT *p; 1697 SIM_PORT *p;
1731 int i; 1698 int i;
1732 int res; 1699 int res;
1733 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 1700 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
1734 1701
1735 #ifdef SIM_SAT_REFRESH_TEST 1702 #ifdef SIM_SAT_REFRESH_TEST
1736 // do 1000 times the following sequence 1703 // do 1000 times the following sequence
1737 for (i=0;i<1000;i++) { 1704 for (i=0;i<1000;i++) {
1738 SIM_PowerOff(); 1705 SIM_PowerOff();
1829 snd[1] = 0xB0; 1796 snd[1] = 0xB0;
1830 snd[2] = 0x00; 1797 snd[2] = 0x00;
1831 snd[3] = 0x00; 1798 snd[3] = 0x00;
1832 snd[4] = 0x00; 1799 snd[4] = 0x00;
1833 rescmd = SIM_XchTPDU(&snd[0], 5, &rec[0], 256, &recl); 1800 rescmd = SIM_XchTPDU(&snd[0], 5, &rec[0], 256, &recl);
1834
1835
1836 } 1801 }
1837 1802 #endif
1838 #endif
1839
1840 1803
1841 p = &(Sim[0]); 1804 p = &(Sim[0]);
1842 1805
1843 p->xbuf[0] = GSM_CLASS; 1806 p->xbuf[0] = GSM_CLASS;
1844 p->xbuf[1] = SIM_UPDATE_RECORD; 1807 p->xbuf[1] = SIM_UPDATE_RECORD;
1870 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8); 1833 SIM_dbg_tmp[0] = (SYS_UWORD8)(SIM_dbg_tdma_diff >> 8);
1871 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff); 1834 SIM_dbg_tmp[1] = (SYS_UWORD8)(SIM_dbg_tdma_diff);
1872 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 1835 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
1873 #endif 1836 #endif
1874 1837
1875
1876 #ifdef SIM_APDU_TEST 1838 #ifdef SIM_APDU_TEST
1877
1878 // send CLOSE LOGICAL CHANNEL 1839 // send CLOSE LOGICAL CHANNEL
1879 snd[0] = 0x00; 1840 snd[0] = 0x00;
1880 snd[1] = 0x70; 1841 snd[1] = 0x70;
1881 snd[2] = 0x80; 1842 snd[2] = 0x80;
1882 snd[3] = logchan; 1843 snd[3] = logchan;
1883 snd[4] = 0x00; 1844 snd[4] = 0x00;
1884 resclose = SIM_XchTPDU(&snd[0], 5, &rec[0], 0, &recl); 1845 resclose = SIM_XchTPDU(&snd[0], 5, &rec[0], 0, &recl);
1885
1886 #endif 1846 #endif
1887 1847
1888 return(res); 1848 return(res);
1889 } 1849 }
1890 1850
1897 SYS_UWORD16 SIM_Seek(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 1857 SYS_UWORD16 SIM_Seek(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
1898 { 1858 {
1899 SIM_PORT *p; 1859 SIM_PORT *p;
1900 int i; 1860 int i;
1901 int res; 1861 int res;
1902 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 1862 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
1903 1863
1904 p = &(Sim[0]); 1864 p = &(Sim[0]);
1905 1865
1906 p->xbuf[0] = GSM_CLASS; 1866 p->xbuf[0] = GSM_CLASS;
1907 p->xbuf[1] = SIM_SEEK; 1867 p->xbuf[1] = SIM_SEEK;
1997 SYS_UWORD16 SIM_TerminalProfile(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 1957 SYS_UWORD16 SIM_TerminalProfile(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
1998 { 1958 {
1999 SIM_PORT *p; 1959 SIM_PORT *p;
2000 int i; 1960 int i;
2001 int res; 1961 int res;
2002 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 1962 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
2003 1963
2004 p = &(Sim[0]); 1964 p = &(Sim[0]);
2005 1965
2006 p->xbuf[0] = GSM_CLASS; 1966 p->xbuf[0] = GSM_CLASS;
2007 p->xbuf[1] = SIM_TERMINAL_PROFILE; 1967 p->xbuf[1] = SIM_TERMINAL_PROFILE;
2043 SYS_UWORD16 SIM_Fetch(SYS_UWORD8 *result, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 2003 SYS_UWORD16 SIM_Fetch(SYS_UWORD8 *result, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
2044 { 2004 {
2045 SIM_PORT *p; 2005 SIM_PORT *p;
2046 int i; 2006 int i;
2047 int res; 2007 int res;
2048 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 2008 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
2049 2009
2050 p = &(Sim[0]); 2010 p = &(Sim[0]);
2051 2011
2052 p->xbuf[0] = GSM_CLASS; 2012 p->xbuf[0] = GSM_CLASS;
2053 p->xbuf[1] = SIM_FETCH; 2013 p->xbuf[1] = SIM_FETCH;
2054 p->xbuf[2] = 0; 2014 p->xbuf[2] = 0;
2055 p->xbuf[3] = 0; 2015 p->xbuf[3] = 0;
2056 p->xbuf[4] = (SYS_UWORD8)llen; 2016 p->xbuf[4] = (SYS_UWORD8)llen;
2057
2058 2017
2059 res = SIM_Command(p, 0, result, rcvSize); 2018 res = SIM_Command(p, 0, result, rcvSize);
2060 2019
2061 #ifdef SIM_DEBUG_TRACE 2020 #ifdef SIM_DEBUG_TRACE
2062 SIM_dbg_write_trace((SYS_UWORD8 *)"ATCMD", 5); 2021 SIM_dbg_write_trace((SYS_UWORD8 *)"ATCMD", 5);
2088 SYS_UWORD16 SIM_TerminalResponse(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 2047 SYS_UWORD16 SIM_TerminalResponse(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
2089 { 2048 {
2090 SIM_PORT *p; 2049 SIM_PORT *p;
2091 int i; 2050 int i;
2092 int res; 2051 int res;
2093 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 2052 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
2094 2053
2095 p = &(Sim[0]); 2054 p = &(Sim[0]);
2096 2055
2097 p->xbuf[0] = GSM_CLASS; 2056 p->xbuf[0] = GSM_CLASS;
2098 p->xbuf[1] = SIM_TERMINAL_RESPONSE; 2057 p->xbuf[1] = SIM_TERMINAL_RESPONSE;
2127 2086
2128 2087
2129 /* 2088 /*
2130 * SIM_Envelope 2089 * SIM_Envelope
2131 * 2090 *
2132 * Used by Network to tansfert data download to the SIM in a transparent way for user 2091 * Used by Network to transfer data download to the SIM in a transparent way for user
2133 */ 2092 */
2134 SYS_UWORD16 SIM_Envelope(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize) 2093 SYS_UWORD16 SIM_Envelope(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 len, SYS_UWORD16 *rcvSize)
2135 { 2094 {
2136 SIM_PORT *p; 2095 SIM_PORT *p;
2137 int i; 2096 int i;
2138 int res; 2097 int res;
2139 SYS_UWORD16 llen = len & SIM_UWORD16_MASK; 2098 SYS_UWORD16 llen = len & SIM_UWORD16_MASK;
2140 2099
2141 p = &(Sim[0]); 2100 p = &(Sim[0]);
2142 2101
2143 p->xbuf[0] = GSM_CLASS; 2102 p->xbuf[0] = GSM_CLASS;
2144 p->xbuf[1] = SIM_ENVELOPE; 2103 p->xbuf[1] = SIM_ENVELOPE;
2174 2133
2175 return(res); 2134 return(res);
2176 } 2135 }
2177 2136
2178 2137
2179
2180
2181
2182
2183
2184
2185
2186 /* 2138 /*
2187 * SIM_XchTPDU * 2139 * SIM_XchTPDU *
2188 * Used for ME to send generic command to WIM Card 2140 * Used for ME to send generic command to WIM Card
2189 */ 2141 */
2190 SYS_UWORD16 SIM_XchTPDU(SYS_UWORD8 *dat, SYS_UWORD16 trxLen, SYS_UWORD8 *result, 2142 SYS_UWORD16 SIM_XchTPDU(SYS_UWORD8 *dat, SYS_UWORD16 trxLen, SYS_UWORD8 *result,
2191 SYS_UWORD16 rcvLen, SYS_UWORD16 *rcvSize) 2143 SYS_UWORD16 rcvLen, SYS_UWORD16 *rcvSize)
2192 { 2144 {
2193 SIM_PORT *p; 2145 SIM_PORT *p;
2194 int i; 2146 int i;
2195 int res; 2147 int res;
2196 2148
2205 for (i=5;i<trxLen;i++) 2157 for (i=5;i<trxLen;i++)
2206 { 2158 {
2207 p->xbuf[i] = dat[i]; 2159 p->xbuf[i] = dat[i];
2208 } 2160 }
2209 2161
2210 // enable the WIM behavior of the sim driver 2162 // enable the WIM behavior of the sim driver
2211 p->apdu_ans_length = rcvLen; 2163 p->apdu_ans_length = rcvLen;
2212 2164
2213 res = SIM_Command(p, (trxLen - 5), result, rcvSize); 2165 res = SIM_Command(p, (trxLen - 5), result, rcvSize);
2214 2166
2215 // disable the WIM behavior of the sim driver 2167 // disable the WIM behavior of the sim driver
2216 p->apdu_ans_length = 0; 2168 p->apdu_ans_length = 0;
2217 2169
2218 #ifdef SIM_DEBUG_TRACE 2170 #ifdef SIM_DEBUG_TRACE
2219 SIM_dbg_write_trace((SYS_UWORD8 *)"AWCMD", 5); 2171 SIM_dbg_write_trace((SYS_UWORD8 *)"AWCMD", 5);
2220 SIM_dbg_write_trace(p->xbuf, trxLen); 2172 SIM_dbg_write_trace(p->xbuf, trxLen);
2221 SIM_dbg_write_trace((SYS_UWORD8 *)"AWANS", 5); 2173 SIM_dbg_write_trace((SYS_UWORD8 *)"AWANS", 5);
2234 SIM_dbg_write_trace(SIM_dbg_tmp, 2); 2186 SIM_dbg_write_trace(SIM_dbg_tmp, 2);
2235 #endif 2187 #endif
2236 2188
2237 return(res); 2189 return(res);
2238 } 2190 }
2239
2240
2241
2242
2243
2244
2245 2191
2246 2192
2247 /* 2193 /*
2248 * Use to detect end of characters reception 2194 * Use to detect end of characters reception
2249 * input: p pointer on sim structure 2195 * input: p pointer on sim structure
2255 */ 2201 */
2256 2202
2257 SYS_UWORD16 SIM_WaitReception(SIM_PORT *p) 2203 SYS_UWORD16 SIM_WaitReception(SIM_PORT *p)
2258 { 2204 {
2259 SYS_UWORD16 returncode; 2205 SYS_UWORD16 returncode;
2260
2261 2206
2262 //analyse the nature of the command to execute 2207 //analyse the nature of the command to execute
2263 2208
2264 if ( 2209 if (
2265 (p->xbuf[1] == 0x12) || 2210 (p->xbuf[1] == 0x12) ||
2298 } 2243 }
2299 return (0); 2244 return (0);
2300 } 2245 }
2301 2246
2302 2247
2303
2304 /* 2248 /*
2305 * Use to read file characteristics information 2249 * Use to read file characteristics information
2306 * input: p pointer on sim structure 2250 * input: p pointer on sim structure
2307 * 2251 *
2308 * output: return 0 if sucess 2252 * output: return 0 if sucess
2350 { 2294 {
2351 p->Freq_Algo = 1; 2295 p->Freq_Algo = 1;
2352 } 2296 }
2353 2297
2354 //interpret Clock stop behavior 2298 //interpret Clock stop behavior
2355 // modified by J. Yp-Tcha to integrate all the behaviors required by ETSI. 2299 // modified by J. Yp-Tcha to integrate all the behaviors required by ETSI.
2356 // 18/11/2002 : TI Chip always allowed low level, high level is hard dependant 2300 // 18/11/2002 : TI Chip always allowed low level, high level is hard dependant
2357 2301
2358 if ((p->FileC & SIM_CLK_STOP_MASK) == SIM_CLK_STOP_NOT_ALLWD) { 2302 if ((p->FileC & SIM_CLK_STOP_MASK) == SIM_CLK_STOP_NOT_ALLWD) {
2359 /* Sim Clock Stop Not Allowed */ 2303 /* Sim Clock Stop Not Allowed */
2304 SIM_sleep_status = SIM_SLEEP_NOT_ALLOWED;
2305 /* There is not need to modifiy p->conf1 */
2306 status_os_sim = NU_Delete_Timer (&SIM_timer);
2307 }
2308 else {
2309 if ((p->FileC & SIM_CLK_STOP_MASK) == SIM_CLK_STOP_ALLWD) {
2310 /* Sim Clock Stop Allowed, no prefered level */
2311 /* Default value for TI Chip shall always be Low Level */
2312 SIM_sleep_status = SIM_SLEEP_DESACT;
2313 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SCLKLEV;
2314 }
2315 else {
2316 /* Clock Stop is allowed, the level shall be checked */
2317 if ((p->FileC & SIM_CLK_STOP_HIGH) == SIM_CLK_STOP_HIGH) {
2318 /* high level is mandatory */
2319 /* OMEGA/NAUSICA can not handle sim stop clock at high level */
2320 #ifndef ANALOG1
2321 SIM_sleep_status = SIM_SLEEP_DESACT;
2322 p->c->conf1 = p->conf1 |= SIM_CONF1_SCLKLEV;
2323 #else
2324 /* Sim Clock Stop Not Allowed because the interface do not support this level */
2360 SIM_sleep_status = SIM_SLEEP_NOT_ALLOWED; 2325 SIM_sleep_status = SIM_SLEEP_NOT_ALLOWED;
2361 /* There is not need to modifiy p->conf1 */ 2326 /* There is not need to modifiy p->conf1 */
2362 status_os_sim = NU_Delete_Timer (&SIM_timer); 2327 status_os_sim = NU_Delete_Timer (&SIM_timer);
2328 #endif
2329 }
2330 else {
2331 /* by default, Low Level is allowed */
2332 SIM_sleep_status = SIM_SLEEP_DESACT;
2333 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SCLKLEV;
2334 }
2363 } 2335 }
2364 else { 2336 }
2365 if ((p->FileC & SIM_CLK_STOP_MASK) == SIM_CLK_STOP_ALLWD) {
2366 /* Sim Clock Stop Allowed, no prefered level */
2367 /* Default value for TI Chip shall always be Low Level */
2368 SIM_sleep_status = SIM_SLEEP_DESACT;
2369 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SCLKLEV;
2370 }
2371 else {
2372 /* Clock Stop is allowed, the level shall be checked */
2373 if ((p->FileC & SIM_CLK_STOP_HIGH) == SIM_CLK_STOP_HIGH) {
2374 /* high level is mandatory */
2375 /* OMEGA/NAUSICA can not handle sim stop clock at high level */
2376 #ifndef ANALOG1
2377 SIM_sleep_status = SIM_SLEEP_DESACT;
2378 p->c->conf1 = p->conf1 |= SIM_CONF1_SCLKLEV;
2379 #else
2380 /* Sim Clock Stop Not Allowed because the interface do not support this level */
2381 SIM_sleep_status = SIM_SLEEP_NOT_ALLOWED;
2382 /* There is not need to modifiy p->conf1 */
2383 status_os_sim = NU_Delete_Timer (&SIM_timer);
2384 #endif
2385 }
2386 else {
2387 /* by default, Low Level is allowed */
2388 SIM_sleep_status = SIM_SLEEP_DESACT;
2389 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SCLKLEV;
2390 }
2391 }
2392 }
2393 if (SIM_sleep_status == SIM_SLEEP_NONE) 2337 if (SIM_sleep_status == SIM_SLEEP_NONE)
2394 { 2338 {
2395 status_os_sim = NU_Delete_Timer (&SIM_timer); 2339 status_os_sim = NU_Delete_Timer (&SIM_timer);
2396 } 2340 }
2397 } 2341 }
2408 */ 2352 */
2409 2353
2410 2354
2411 SYS_UWORD16 SIM_PTSprocedure(SIM_CARD *cP, SIM_PORT *p) 2355 SYS_UWORD16 SIM_PTSprocedure(SIM_CARD *cP, SIM_PORT *p)
2412 { 2356 {
2413
2414 SYS_UWORD8 TA1; 2357 SYS_UWORD8 TA1;
2415 SYS_UWORD8 n; 2358 SYS_UWORD8 n;
2416 SYS_UWORD8 err; 2359 SYS_UWORD8 err;
2417 2360
2418 p->xbuf[0] = 0xFF; //character of PTS proc to send 2361 p->xbuf[0] = 0xFF; //character of PTS proc to send
2419 p->xbuf[1] = 0; 2362 p->xbuf[1] = 0;
2420 p->xbuf[2] = 0xFF; 2363 p->xbuf[2] = 0xFF;
2421 p->xbuf[3] = 0x7B; 2364 p->xbuf[3] = 0x7B;
2422 2365
2423 //TA1,TB1,TC1,TD1 present in ATR ? 2366 //TA1,TB1,TC1,TD1 present in ATR ?
2424 2367
2425 n = 3; 2368 n = 3;
2426 2369
2427 p->PTS_Try++; 2370 p->PTS_Try++;
2428 2371
2429 if (p->PTS_Try > 4) 2372 if (p->PTS_Try > 4)
2430 { 2373 {
2431 return (SIM_ERR_CARDREJECT); 2374 return (SIM_ERR_CARDREJECT);
2432 } // at the fourth attempt, PTS procedure is unusefull. Use default value. 2375 } // at the fourth attempt, PTS procedure is unusefull. Use default value.
2433 //TA1 present? Test 27.11.2.6 2376 //TA1 present? Test 27.11.2.6
2434 else if ( p->PTS_Try == 4) 2377 else if (p->PTS_Try == 4)
2435 { 2378 {
2436 SIM_Calcetu (p); 2379 SIM_Calcetu (p);
2437 return (0); 2380 return (0);
2438 } 2381 }
2439 2382
2440 if(cP->AtrData[1] & 0x10) 2383 if (cP->AtrData[1] & 0x10)
2441 { 2384 {
2442 TA1 = cP->AtrData[2]; 2385 TA1 = cP->AtrData[2];
2443 } 2386 }
2444 else //if TA1 not present, return 2387 else //if TA1 not present, return
2445 { 2388 {
2478 { 2421 {
2479 return (err); 2422 return (err);
2480 } 2423 }
2481 //should received same chars as PTS request 2424 //should received same chars as PTS request
2482 if ((p->rbuf[0] != p->xbuf[0]) || (p->rbuf[1] != p->xbuf[1]) || 2425 if ((p->rbuf[0] != p->xbuf[0]) || (p->rbuf[1] != p->xbuf[1]) ||
2483 (p->rbuf[2] != p->xbuf[2])) 2426 (p->rbuf[2] != p->xbuf[2]))
2484 { 2427 {
2485 return(SIM_ERR_READ); 2428 return(SIM_ERR_READ);
2486 } 2429 }
2487
2488 2430
2489 if (n == 4) 2431 if (n == 4)
2490 { 2432 {
2491 if (p->rbuf[3] != p->xbuf[3]) 2433 if (p->rbuf[3] != p->xbuf[3])
2492 { 2434 {
2497 p->c->conf1 = p->conf1 |= SIM_CONF1_ETU; //set F=512 D=8 2439 p->c->conf1 = p->conf1 |= SIM_CONF1_ETU; //set F=512 D=8
2498 } 2440 }
2499 2441
2500 SIM_Calcetu (p); 2442 SIM_Calcetu (p);
2501 return (0); 2443 return (0);
2502
2503 } 2444 }
2504 2445
2505 /* 2446 /*
2506 * procedure of WARM reset consists on asserting 2447 * procedure of WARM reset consists on asserting
2507 * reset signal at 0 during at least 400 ETU 2448 * reset signal at 0 during at least 400 ETU
2508 * input p pointer of type SIM_PORT 2449 * input p pointer of type SIM_PORT
2509 */ 2450 */
2510 2451
2511 void SIM_WARMReset (SIM_PORT *p) 2452 void SIM_WARMReset (SIM_PORT *p)
2512 { 2453 {
2513
2514 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SRSTLEV; 2454 p->c->conf1 = p->conf1 &= ~SIM_CONF1_SRSTLEV;
2515 ind_os_sleep (p->etu400); /// wait 400 ETU 2455 ind_os_sleep (p->etu400); /// wait 400 ETU
2516 p->c->conf1 = p->conf1 |= SIM_CONF1_SRSTLEV; 2456 p->c->conf1 = p->conf1 |= SIM_CONF1_SRSTLEV;
2517 p->rx_index = 0; 2457 p->rx_index = 0;
2518
2519 } 2458 }
2520 2459
2521 2460
2522 /* 2461 /*
2523 * procedure use to get out sleepMode 2462 * procedure use to get out sleepMode
2531 (&(Sim[0]))->c->conf1 &= ~SIM_CONF1_SCLKEN; //disabled the clock for the SIM card 2470 (&(Sim[0]))->c->conf1 &= ~SIM_CONF1_SCLKEN; //disabled the clock for the SIM card
2532 SIM_sleep_status = SIM_SLEEP_ACT; 2471 SIM_sleep_status = SIM_SLEEP_ACT;
2533 } 2472 }
2534 status_os_sim = NU_Control_Timer (&SIM_timer, NU_DISABLE_TIMER); 2473 status_os_sim = NU_Control_Timer (&SIM_timer, NU_DISABLE_TIMER);
2535 } 2474 }
2536
2537
2538 2475
2539 2476
2540 /* 2477 /*
2541 * procedure use to get out sleepMode 2478 * procedure use to get out sleepMode
2542 * input p pointer of type SIM_PORT 2479 * input p pointer of type SIM_PORT
2566 */ 2503 */
2567 2504
2568 2505
2569 SYS_UWORD16 SIM_ATRdynamictreatement (SIM_PORT *p, SIM_CARD *cP) 2506 SYS_UWORD16 SIM_ATRdynamictreatement (SIM_PORT *p, SIM_CARD *cP)
2570 { 2507 {
2571 2508 volatile SYS_UWORD8 HistChar;
2572 volatile SYS_UWORD8 HistChar; 2509 volatile SYS_UWORD8 InterfChar;
2573 volatile SYS_UWORD8 InterfChar;
2574 SYS_UWORD16 countT; 2510 SYS_UWORD16 countT;
2575 SYS_UWORD16 mask; 2511 SYS_UWORD16 mask;
2576 SYS_UWORD16 returncode; 2512 SYS_UWORD16 returncode;
2577 SYS_UWORD8 i; 2513 SYS_UWORD8 i;
2578 SYS_UWORD8 firstprotocol; 2514 SYS_UWORD8 firstprotocol;
2579 SYS_UWORD8 Tx,T; 2515 SYS_UWORD8 Tx,T;
2580 SYS_UWORD8 TDi; 2516 SYS_UWORD8 TDi;
2581 SYS_UWORD8 position_of_TC1, position_of_TB1; 2517 SYS_UWORD8 position_of_TC1, position_of_TB1;
2582 SYS_UWORD8 another_protocol_present; 2518 SYS_UWORD8 another_protocol_present;
2583 SYS_UWORD16 wait80000clk; 2519 SYS_UWORD16 wait80000clk;
2584 2520
2585 i = 0; 2521 i = 0;
2586 //wait for TS and T0 2522 //wait for TS and T0
2587 p->moderx = 0; 2523 p->moderx = 0;
2588 p->expected_data= 1; 2524 p->expected_data= 1;
2603 if (returncode = SIM_Waitforchars (p, p->etu9600)) 2539 if (returncode = SIM_Waitforchars (p, p->etu9600))
2604 { 2540 {
2605 return returncode; 2541 return returncode;
2606 } 2542 }
2607 2543
2608 ind_os_sleep(220); 2544 ind_os_sleep(220);
2609 2545
2610 if (((p->rbuf[0] & 0xF0) == 0x30) && (p->rx_index != 0)) 2546 if (((p->rbuf[0] & 0xF0) == 0x30) && (p->rx_index != 0))
2611 { 2547 {
2612 cP->Inverse = 0; 2548 cP->Inverse = 0;
2613 } 2549 }
2645 //wait for TC1 and save its position 2581 //wait for TC1 and save its position
2646 if ((firstprotocol == 0) && ((Tx & 0x40) == mask)) 2582 if ((firstprotocol == 0) && ((Tx & 0x40) == mask))
2647 { 2583 {
2648 position_of_TC1 = InterfChar - 1; 2584 position_of_TC1 = InterfChar - 1;
2649 } 2585 }
2650 if ((firstprotocol == 0) && ((Tx & 0x20) == mask)) 2586 if ((firstprotocol == 0) && ((Tx & 0x20) == mask))
2651 { 2587 {
2652 position_of_TB1 = InterfChar - 1; 2588 position_of_TB1 = InterfChar - 1;
2653 } 2589 }
2654 2590
2655 mask = mask << 1; 2591 mask = mask << 1;
2765 } 2701 }
2766 return (translated); 2702 return (translated);
2767 } 2703 }
2768 2704
2769 2705
2770
2771 /* 2706 /*
2772 * SIM_Waitforchars is used for waiting nbchar characters from SIM 2707 * SIM_Waitforchars is used for waiting nbchar characters from SIM
2773 * input p sim port 2708 * input p sim port
2774 * max_wait max number of TDMA to wait between 2 characters 2709 * max_wait max number of TDMA to wait between 2 characters
2775 * output 2710 * output
2816 2751
2817 if ((p->moderx != 6) && (p->moderx != 5)) //treatement of mode 0, 1, 2, 3, 4 2752 if ((p->moderx != 6) && (p->moderx != 5)) //treatement of mode 0, 1, 2, 3, 4
2818 { 2753 {
2819 countT = 0; 2754 countT = 0;
2820 old_nb_char = p->rx_index; 2755 old_nb_char = p->rx_index;
2821 //leave while if moderx == 5 2756 //leave while if moderx == 5
2822 while((p->rx_index < p->expected_data) && (p->moderx != 5)) 2757 while((p->rx_index < p->expected_data) && (p->moderx != 5))
2823 { 2758 {
2824 ind_os_sleep(1); 2759 ind_os_sleep(1);
2825 countT++; //implementation of software Waiting time overflow 2760 countT++; //implementation of software Waiting time overflow
2826 2761
2842 { 2777 {
2843 old_nb_char = p->rx_index; //if char received before max_wait TDMA, reset the counter 2778 old_nb_char = p->rx_index; //if char received before max_wait TDMA, reset the counter
2844 countT = 0; 2779 countT = 0;
2845 } 2780 }
2846 } //end while 2781 } //end while
2847 if (p->moderx == 0) 2782 if (p->moderx == 0)
2848 { 2783 {
2849 return (0); 2784 return (0);
2850 } 2785 }
2851 } 2786 }
2852 2787
2853 if (p->moderx == 5) //use for reception of SW1 SW2 2788 if (p->moderx == 5) //use for reception of SW1 SW2
2854 { 2789 {
2855 countT = 0; 2790 countT = 0;
2856 old_nb_char = p->SWcount; 2791 old_nb_char = p->SWcount;
2857 2792
2858 while(p->SWcount < 2) 2793 while (p->SWcount < 2)
2859 { //if p->moderx change from 6 to 5, need to wait for SW1 and SW2 2794 { //if p->moderx change from 6 to 5, need to wait for SW1 and SW2
2860 2795
2861 ind_os_sleep(1); 2796 ind_os_sleep(1);
2862 countT++; //implementation of software Waiting time overflow 2797 countT++; //implementation of software Waiting time overflow
2863 2798
2881 countT = 0; 2816 countT = 0;
2882 } 2817 }
2883 } 2818 }
2884 p->SWcount = 0; //reset SWcount buffer index when SW1 SW2 received 2819 p->SWcount = 0; //reset SWcount buffer index when SW1 SW2 received
2885 return (0); 2820 return (0);
2886 } 2821 }
2887 else //treatement of abnormal case of the asynchronous state machine 2822 else //treatement of abnormal case of the asynchronous state machine
2888 { 2823 {
2889 return (SIM_ERR_ABNORMAL_CASE1); 2824 return (SIM_ERR_ABNORMAL_CASE1);
2890 } 2825 }
2891 2826 }
2892 }
2893
2894 2827
2895 2828
2896 /* 2829 /*
2897 * SIM_Calcetu is used for calculating 9600 etu and 400 etu depending on sim clock freq 2830 * SIM_Calcetu is used for calculating 9600 etu and 400 etu depending on sim clock freq
2898 * and etu period 2831 * and etu period
2903 { 2836 {
2904 if (p->conf1 & SIM_CONF1_SCLKDIV) //clock input is 13/8 Mhz 2837 if (p->conf1 & SIM_CONF1_SCLKDIV) //clock input is 13/8 Mhz
2905 { 2838 {
2906 if (p->conf1 & SIM_CONF1_ETU) //etu period is 512/8*Tsclk 2839 if (p->conf1 & SIM_CONF1_ETU) //etu period is 512/8*Tsclk
2907 { 2840 {
2908 p->etu9600 = 319; // old = 88, increase of 363% 2841 p->etu9600 = 319; // old = 88, increase of 363%
2909 p->etu400 = 6; 2842 p->etu400 = 6;
2910 p->stopclock = 18; 2843 p->stopclock = 18;
2911 p->startclock = 8; 2844 p->startclock = 8;
2912 } 2845 }
2913 else //etu period is 372/1*Tsclk 2846 else //etu period is 372/1*Tsclk
2914 { 2847 {
2915 p->etu9600 = 1815; // old = 500, increase of 363% 2848 p->etu9600 = 1815; // old = 500, increase of 363%
2916 p->etu400 = 28; 2849 p->etu400 = 28;
2917 p->stopclock = 94; 2850 p->stopclock = 94;
2918 p->startclock = 38; 2851 p->startclock = 38;
2919 } 2852 }
2920 } 2853 }
2921 else //clock input is 13/4 Mhz 2854 else //clock input is 13/4 Mhz
2922 { 2855 {
2923 if (p->conf1 & SIM_CONF1_ETU) //etu period is 512/8*Tsclk 2856 if (p->conf1 & SIM_CONF1_ETU) //etu period is 512/8*Tsclk
2924 { 2857 {
2925 p->etu9600 = 159; // old = 44, increase of 363% 2858 p->etu9600 = 159; // old = 44, increase of 363%
2926 p->etu400 = 3; 2859 p->etu400 = 3;
2927 p->stopclock = 9; 2860 p->stopclock = 9;
2928 p->startclock = 4; 2861 p->startclock = 4;
2929 } 2862 }
2930 else //etu period is 372/1*Tsclk 2863 else //etu period is 372/1*Tsclk
2931 { 2864 {
2932 p->etu9600 = 907; // old = 250, increase of 363% 2865 p->etu9600 = 907; // old = 250, increase of 363%
2933 p->etu400 = 14; 2866 p->etu400 = 14;
2934 p->stopclock = 47; 2867 p->stopclock = 47;
2935 p->startclock = 19; 2868 p->startclock = 19;
2936 } 2869 }
2937 } 2870 }
2938 } 2871 }
2939 2872
2940 2873
2941
2942
2943
2944 /* 2874 /*
2945 * Set the level shifter voltage for start up sequence 2875 * Set the level shifter voltage for start up sequence
2946 * 2876 *
2947 */ 2877 */
2948 2878
2949 SYS_UWORD8 SIM_StartVolt (SYS_UWORD8 ResetFlag) 2879 SYS_UWORD8 SIM_StartVolt (SYS_UWORD8 ResetFlag)
2950 { 2880 {
2951 SYS_UWORD8 abbmask; 2881 SYS_UWORD8 abbmask;
2952 2882
2953 #if(ANLG_FAM == 1) 2883 #if(ANLG_FAM == 1)
2954 // we assume that in SIM_TYPE_5V there is nothing to do because it is the reset value 2884 // we assume that in SIM_TYPE_5V there is nothing to do because it is the reset value
2955 #if ((SIM_TYPE == SIM_TYPE_3V) || (SIM_TYPE == SIM_TYPE_3_5V)) // { shut down VCC from ABB and prepare to start at 3V mode 2885 #if ((SIM_TYPE == SIM_TYPE_3V) || (SIM_TYPE == SIM_TYPE_3_5V)) // { shut down VCC from ABB and prepare to start at 3V mode
2956 if (ResetFlag) { 2886 if (ResetFlag) {
2887 abbmask = MODE_INIT_OMEGA_3V;
2888 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning.
2889 }
2890 else {
2891 if (CurrentVolt == SIM_3V)
2957 abbmask = MODE_INIT_OMEGA_3V; 2892 abbmask = MODE_INIT_OMEGA_3V;
2958 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning. 2893 else
2959 } 2894 abbmask = MODE5V_OMEGA;
2960 else { 2895 }
2961 if (CurrentVolt == SIM_3V)
2962 abbmask = MODE_INIT_OMEGA_3V;
2963 else
2964 abbmask = MODE5V_OMEGA;
2965 }
2966 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) & 0xC0) | abbmask); 2896 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) & 0xC0) | abbmask);
2967 ind_os_sleep(1); //wait for charge pump regulation 2897 ind_os_sleep(1); //wait for charge pump regulation
2968 return(SIM_OK); 2898 return(SIM_OK);
2969 #endif 2899 #endif
2970 #endif 2900 #endif
2972 #if(ANLG_FAM == 2) 2902 #if(ANLG_FAM == 2)
2973 SYS_UWORD8 count = 0; 2903 SYS_UWORD8 count = 0;
2974 // code for Iota 2904 // code for Iota
2975 // reset value for IOTA is for 1.8V, but specific procedure is needed 2905 // reset value for IOTA is for 1.8V, but specific procedure is needed
2976 #if ((SIM_TYPE == SIM_TYPE_1_8V) || (SIM_TYPE == SIM_TYPE_1_8_3V)) // shut down VCC from ABB and prepare to start at 1.8V mode 2906 #if ((SIM_TYPE == SIM_TYPE_1_8V) || (SIM_TYPE == SIM_TYPE_1_8_3V)) // shut down VCC from ABB and prepare to start at 1.8V mode
2977 if (ResetFlag) { 2907 if (ResetFlag) {
2908 abbmask = MODE_INIT_IOTA_1_8V;
2909 CurrentVolt = SIM_1_8V; // we assume the sim is 1.8v tech. from beginning.
2910 }
2911 else {
2912 if (CurrentVolt == SIM_1_8V)
2978 abbmask = MODE_INIT_IOTA_1_8V; 2913 abbmask = MODE_INIT_IOTA_1_8V;
2979 CurrentVolt = SIM_1_8V; // we assume the sim is 1.8v tech. from beginning. 2914 else
2980 } 2915 abbmask = MODE_INIT_IOTA_3V;
2981 else { 2916 }
2982 if (CurrentVolt == SIM_1_8V)
2983 abbmask = MODE_INIT_IOTA_1_8V;
2984 else
2985 abbmask = MODE_INIT_IOTA_3V;
2986 }
2987 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask); 2917 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask);
2988 while(count++ < 5) 2918 while(count++ < 5)
2989 { 2919 {
2990 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04) // test RSIMRSU 2920 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04) // test RSIMRSU
2991 return(SIM_OK); 2921 return(SIM_OK);
2992 ind_os_sleep(1); 2922 ind_os_sleep(1);
2993 } 2923 }
2994 // IOTA failure activation 2924 // IOTA failure activation
2995 return(SIM_ERR_HARDWARE_FAIL); 2925 return(SIM_ERR_HARDWARE_FAIL);
2996 #endif 2926 #endif
2997 // 3V only 2927 // 3V only
2998 #if (SIM_TYPE == SIM_TYPE_3V) 2928 #if (SIM_TYPE == SIM_TYPE_3V)
2999 abbmask = MODE_INIT_IOTA_3V; 2929 abbmask = MODE_INIT_IOTA_3V;
3000 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning. 2930 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning.
3001 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask); 2931 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask);
3002 while(count++ < 5) 2932 while(count++ < 5)
3003 { 2933 {
3004 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04) // test RSIMRSU 2934 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04) // test RSIMRSU
3005 return(SIM_OK); 2935 return(SIM_OK);
3006 ind_os_sleep(1); 2936 ind_os_sleep(1);
3007 } 2937 }
3008 // IOTA failure activation 2938 // IOTA failure activation
3009 return(SIM_ERR_HARDWARE_FAIL); 2939 return(SIM_ERR_HARDWARE_FAIL);
3013 #if(ANLG_FAM == 3) 2943 #if(ANLG_FAM == 3)
3014 SYS_UWORD8 count = 0; 2944 SYS_UWORD8 count = 0;
3015 // code for Syren 2945 // code for Syren
3016 // reset value for SYREN is for 1.8V, but specific procedure is needed 2946 // reset value for SYREN is for 1.8V, but specific procedure is needed
3017 #if ((SIM_TYPE == SIM_TYPE_1_8V) || (SIM_TYPE == SIM_TYPE_1_8_3V)) // { shut down VCC from ABB and prepare to start at 1.8V mode 2947 #if ((SIM_TYPE == SIM_TYPE_1_8V) || (SIM_TYPE == SIM_TYPE_1_8_3V)) // { shut down VCC from ABB and prepare to start at 1.8V mode
3018 if (ResetFlag) { 2948 if (ResetFlag) {
2949 abbmask = MODE_INIT_SYREN_1_8V;
2950 CurrentVolt = SIM_1_8V; // we assume the sim is 1.8v tech. from beginning.
2951 }
2952 else {
2953 if (CurrentVolt == SIM_1_8V)
3019 abbmask = MODE_INIT_SYREN_1_8V; 2954 abbmask = MODE_INIT_SYREN_1_8V;
3020 CurrentVolt = SIM_1_8V; // we assume the sim is 1.8v tech. from beginning. 2955 else
3021 } 2956 abbmask = MODE_INIT_SYREN_3V;
3022 else { 2957 }
3023 if (CurrentVolt == SIM_1_8V) 2958 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x1F4) | abbmask);
3024 abbmask = MODE_INIT_SYREN_1_8V;
3025 else
3026 abbmask = MODE_INIT_SYREN_3V;
3027 }
3028 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x1F4) | abbmask);
3029 while(count++ < 5) 2959 while(count++ < 5)
3030 { 2960 {
3031 if (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x04) // test RSIMRSU 2961 if (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x04) // test RSIMRSU
3032 return(SIM_OK); 2962 return(SIM_OK);
3033 ind_os_sleep(1); 2963 ind_os_sleep(1);
3034 } 2964 }
3035 // SYREN failure activation 2965 // SYREN failure activation
3036 return(SIM_ERR_HARDWARE_FAIL); 2966 return(SIM_ERR_HARDWARE_FAIL);
3037 #endif 2967 #endif
3038 2968
3039 // 3V only 2969 // 3V only
3040 #if (SIM_TYPE == SIM_TYPE_3V) 2970 #if (SIM_TYPE == SIM_TYPE_3V)
3041 abbmask = MODE_INIT_SYREN_3V; 2971 abbmask = MODE_INIT_SYREN_3V;
3042 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning. 2972 CurrentVolt = SIM_3V; // we assume the sim is 3v tech. from beginning.
3043 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x1F4) | abbmask); 2973 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x1F4) | abbmask);
3044 while(count++ < 5) 2974 while(count++ < 5)
3045 { 2975 {
3046 if (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x04) // test RSIMRSU 2976 if (ABB_Read_Register_on_page(PAGE1,VRPCSIMR) & 0x04) // test RSIMRSU
3047 return(SIM_OK); 2977 return(SIM_OK);
3061 2991
3062 2992
3063 SYS_UWORD8 SIM_SwitchVolt (SYS_UWORD8 ResetFlag) 2993 SYS_UWORD8 SIM_SwitchVolt (SYS_UWORD8 ResetFlag)
3064 { 2994 {
3065 SYS_UWORD8 count = 0; 2995 SYS_UWORD8 count = 0;
3066 SYS_UWORD8 abbmask; 2996 SYS_UWORD8 abbmask;
3067 2997
3068 SIM_PowerOff(); 2998 SIM_PowerOff();
3069 2999
3070 #if(ANLG_FAM == 1) 3000 #if(ANLG_FAM == 1)
3071 #if (SIM_TYPE == SIM_TYPE_3_5V) // shut down VCC from ABB and prepare to start at 5V mode 3001 #if (SIM_TYPE == SIM_TYPE_3_5V) // shut down VCC from ABB and prepare to start at 5V mode
3072 if (ResetFlag) { 3002 if (ResetFlag) {
3073 abbmask = MODE5V_OMEGA; 3003 abbmask = MODE5V_OMEGA;
3074 CurrentVolt = SIM_5V; 3004 CurrentVolt = SIM_5V;
3075 } 3005 }
3076 else { 3006 else {
3077 if (CurrentVolt == SIM_3V) 3007 if (CurrentVolt == SIM_3V)
3078 abbmask = MODE_INIT_OMEGA_3V; 3008 abbmask = MODE_INIT_OMEGA_3V;
3079 else 3009 else
3080 abbmask = MODE5V_OMEGA; 3010 abbmask = MODE5V_OMEGA;
3081 } 3011 }
3082 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) & 0xC0) | abbmask); 3012 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCCTRL1) & 0xC0) | abbmask);
3083 return(SIM_OK); 3013 return(SIM_OK);
3084 #endif 3014 #endif
3085 #elif(ANLG_FAM == 2) 3015 #elif(ANLG_FAM == 2)
3086 #if (SIM_TYPE == SIM_TYPE_1_8_3V) // shut down VCC from ABB and prepare to start at 3V mode 3016 #if (SIM_TYPE == SIM_TYPE_1_8_3V) // shut down VCC from ABB and prepare to start at 3V mode
3087 if (ResetFlag) { 3017 if (ResetFlag) {
3088 abbmask = MODE_INIT_IOTA_3V; 3018 abbmask = MODE_INIT_IOTA_3V;
3089 CurrentVolt = SIM_3V; 3019 CurrentVolt = SIM_3V;
3090 } 3020 }
3091 else { 3021 else {
3092 if (CurrentVolt == SIM_1_8V) 3022 if (CurrentVolt == SIM_1_8V)
3093 abbmask = MODE_INIT_IOTA_1_8V; 3023 abbmask = MODE_INIT_IOTA_1_8V;
3094 else 3024 else
3095 abbmask = MODE_INIT_IOTA_3V; 3025 abbmask = MODE_INIT_IOTA_3V;
3096 } 3026 }
3097 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask); 3027 ABB_wa_VRPC ((ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0xF4) | abbmask);
3098 while(count++ < 5) 3028 while(count++ < 5)
3099 { 3029 {
3100 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04) 3030 if (ABB_Read_Register_on_page(PAGE1,VRPCSIM) & 0x04)
3101 return(SIM_OK); 3031 return(SIM_OK);
3102 ind_os_sleep(1); 3032 ind_os_sleep(1);
3103 } 3033 }
3104 // IOTA failure activation 3034 // IOTA failure activation
3105 return(SIM_ERR_HARDWARE_FAIL); 3035 return(SIM_ERR_HARDWARE_FAIL);
3106 #endif 3036 #endif
3107 #elif(ANLG_FAM == 3) 3037 #elif(ANLG_FAM == 3)
3108 #if (SIM_TYPE == SIM_TYPE_1_8_3V) // shut down VCC from ABB and prepare to start at 3V mode 3038 #if (SIM_TYPE == SIM_TYPE_1_8_3V) // shut down VCC from ABB and prepare to start at 3V mode
3109 if (ResetFlag) { 3039 if (ResetFlag) {
3110 abbmask = MODE_INIT_SYREN_3V; 3040 abbmask = MODE_INIT_SYREN_3V;
3111 CurrentVolt = SIM_3V; 3041 CurrentVolt = SIM_3V;
3112 } 3042 }
3113 else { 3043 else {
3114 if (CurrentVolt == SIM_1_8V) 3044 if (CurrentVolt == SIM_1_8V)
3115 abbmask = MODE_INIT_SYREN_1_8V; 3045 abbmask = MODE_INIT_SYREN_1_8V;
3116 else 3046 else
3125 } 3055 }
3126 // SYREN failure activation 3056 // SYREN failure activation
3127 return(SIM_ERR_HARDWARE_FAIL); 3057 return(SIM_ERR_HARDWARE_FAIL);
3128 #endif 3058 #endif
3129 #endif // ANLG_FAM == 1, 2, 3 3059 #endif // ANLG_FAM == 1, 2, 3
3130 3060 }
3131 }
3132
3133 3061
3134 3062
3135 SYS_UWORD8 SIM_Memcpy(SYS_UWORD8 *Buff_target, SYS_UWORD8 Buff_source[], SYS_UWORD16 len) 3063 SYS_UWORD8 SIM_Memcpy(SYS_UWORD8 *Buff_target, SYS_UWORD8 Buff_source[], SYS_UWORD16 len)
3136 { 3064 {
3137 SYS_UWORD16 i; //unsigned short type counter chosen for copy of 256 bytes 3065 SYS_UWORD16 i; //unsigned short type counter chosen for copy of 256 bytes
3138 3066
3139 for (i = 0; i < len; i++) 3067 for (i = 0; i < len; i++)
3140 { 3068 {
3141 if (i == RSIMBUFSIZE) 3069 if (i == RSIMBUFSIZE)
3142 { 3070 {
3143 return (SIM_ERR_BUFF_OVERFL); 3071 return (SIM_ERR_BUFF_OVERFL);
3144 } 3072 }
3145 else 3073 else
3146 { 3074 {
3147 (*(Buff_target+i)) = Buff_source[i]; 3075 (*(Buff_target+i)) = Buff_source[i];
3148 } 3076 }
3149 } 3077 }
3150 return (0); 3078 return (0);
3151 } 3079 }
3152
3153 3080
3154 3081
3155 /* 3082 /*
3156 * SIM_SleepStatus 3083 * SIM_SleepStatus
3157 * 3084 *
3163 if ((SIM_sleep_status == SIM_SLEEP_ACT) || (SIM_sleep_status == SIM_SLEEP_NONE)) 3090 if ((SIM_sleep_status == SIM_SLEEP_ACT) || (SIM_sleep_status == SIM_SLEEP_NONE))
3164 return(1); // SIM is ready for deep sleep 3091 return(1); // SIM is ready for deep sleep
3165 else 3092 else
3166 return(0); 3093 return(0);
3167 } 3094 }
3168
3169
3170 3095
3171 3096
3172 /* 3097 /*
3173 * Special lock function to force SIM entity to use adequat SIM Driver 3098 * Special lock function to force SIM entity to use adequat SIM Driver
3174 */ 3099 */
3180 void SIM_dbg_write_trace(SYS_UWORD8 *ptr, SYS_UWORD16 len) { 3105 void SIM_dbg_write_trace(SYS_UWORD8 *ptr, SYS_UWORD16 len) {
3181 SYS_UWORD16 i; 3106 SYS_UWORD16 i;
3182 for(i=0;i<len;i++) { 3107 for(i=0;i<len;i++) {
3183 if (SIM_dbg_cmd_cmpt == SIM_DBG_CMD) 3108 if (SIM_dbg_cmd_cmpt == SIM_DBG_CMD)
3184 SIM_dbg_cmd_cmpt = 0; 3109 SIM_dbg_cmd_cmpt = 0;
3185 SIM_dbg_cmd[SIM_dbg_cmd_cmpt++] = ptr[i]; 3110 SIM_dbg_cmd[SIM_dbg_cmd_cmpt++] = ptr[i];
3186 } 3111 }
3187 } 3112 }
3188 #endif 3113 #endif
3189
3190
3191
3192