FreeCalypso > hg > fc-tourmaline
comparison src/cs/drivers/drv_core/abb/abb.c @ 219:d00662aa64d8
abb.c: rm trailing white space
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Mon, 26 Apr 2021 17:12:08 +0000 |
parents | 4e78acac3d88 |
children | 0ed36de51973 |
comparison
equal
deleted
inserted
replaced
218:77b980f09bd9 | 219:d00662aa64d8 |
---|---|
57 #if (RF_FAM == 35) | 57 #if (RF_FAM == 35) |
58 #include "l1_rf35.h" | 58 #include "l1_rf35.h" |
59 #endif | 59 #endif |
60 | 60 |
61 #if (RF_FAM == 12) | 61 #if (RF_FAM == 12) |
62 #include "tpudrv12.h" | 62 #include "tpudrv12.h" |
63 #include "l1_rf12.h" | 63 #include "l1_rf12.h" |
64 #endif | 64 #endif |
65 | 65 |
66 #if (RF_FAM == 10) | 66 #if (RF_FAM == 10) |
67 #include "l1_rf10.h" | 67 #include "l1_rf10.h" |
112 | 112 |
113 #ifdef CONFIG_TARGET_LUNA | 113 #ifdef CONFIG_TARGET_LUNA |
114 int ABB_sleep_allowed = 0; | 114 int ABB_sleep_allowed = 0; |
115 #endif | 115 #endif |
116 | 116 |
117 #if (ABB_SEMAPHORE_PROTECTION) | 117 #if (ABB_SEMAPHORE_PROTECTION) |
118 | 118 |
119 static NU_SEMAPHORE abb_sem; | 119 static NU_SEMAPHORE abb_sem; |
120 | 120 |
121 /*-----------------------------------------------------------------------*/ | 121 /*-----------------------------------------------------------------------*/ |
122 /* ABB_Sem_Create() */ | 122 /* ABB_Sem_Create() */ |
126 /* No check on the result. */ | 126 /* No check on the result. */ |
127 /* */ | 127 /* */ |
128 /*-----------------------------------------------------------------------*/ | 128 /*-----------------------------------------------------------------------*/ |
129 void ABB_Sem_Create(void) | 129 void ABB_Sem_Create(void) |
130 { | 130 { |
131 // create a semaphore with an initial count of 1 and with FIFO type suspension. | 131 // create a semaphore with an initial count of 1 and with FIFO type suspension. |
132 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO); | 132 NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO); |
133 } | 133 } |
134 | 134 |
135 #endif // ABB_SEMAPHORE_PROTECTION | 135 #endif // ABB_SEMAPHORE_PROTECTION |
136 | 136 |
137 /*-----------------------------------------------------------------------*/ | 137 /*-----------------------------------------------------------------------*/ |
138 /* ABB_Wait_IBIC_Access() */ | 138 /* ABB_Wait_IBIC_Access() */ |
139 /* */ | 139 /* */ |
140 /* This function waits for the first IBIC access. */ | 140 /* This function waits for the first IBIC access. */ |
141 /* */ | 141 /* */ |
142 /*-----------------------------------------------------------------------*/ | 142 /*-----------------------------------------------------------------------*/ |
143 void ABB_Wait_IBIC_Access(void) | 143 void ABB_Wait_IBIC_Access(void) |
144 { | 144 { |
145 #if (ANLG_FAM ==1) | 145 #if (ANLG_FAM ==1) |
146 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access | 146 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access |
147 // (i.e wait 60us + 10% security marge = 66us) | 147 // (i.e wait 60us + 10% security marge = 66us) |
148 wait_ARM_cycles(convert_nanosec_to_cycles(66000)); | 148 wait_ARM_cycles(convert_nanosec_to_cycles(66000)); |
149 #elif ((ANLG_FAM ==2) || (ANLG_FAM == 3)) | 149 #elif ((ANLG_FAM ==2) || (ANLG_FAM == 3)) |
150 // Wait 6 x 32 KHz clock cycles for first IBIC access | 150 // Wait 6 x 32 KHz clock cycles for first IBIC access |
151 // (i.e wait 187us + 10% security marge = 210us) | 151 // (i.e wait 187us + 10% security marge = 210us) |
152 wait_ARM_cycles(convert_nanosec_to_cycles(210000)); | 152 wait_ARM_cycles(convert_nanosec_to_cycles(210000)); |
153 #endif | 153 #endif |
154 } | 154 } |
155 | 155 |
159 /* ABB_Write_Register_on_page() */ | 159 /* ABB_Write_Register_on_page() */ |
160 /* */ | 160 /* */ |
161 /* This function manages all the spi serial transfer to write to an */ | 161 /* This function manages all the spi serial transfer to write to an */ |
162 /* ABB register on a specified page. */ | 162 /* ABB register on a specified page. */ |
163 /* */ | 163 /* */ |
164 /*-----------------------------------------------------------------------*/ | 164 /*-----------------------------------------------------------------------*/ |
165 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value) | 165 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value) |
166 { | 166 { |
167 volatile SYS_UWORD16 status; | 167 volatile SYS_UWORD16 status; |
168 | 168 |
169 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. | 169 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
170 SPI_Ready_for_WR | 170 SPI_Ready_for_WR |
171 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 171 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
172 | 172 |
173 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) | 173 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
174 | 174 |
175 // check if the semaphore has been correctly created and try to obtain it. | 175 // check if the semaphore has been correctly created and try to obtain it. |
176 // if the semaphore cannot be obtained, the task is suspended and then resumed | 176 // if the semaphore cannot be obtained, the task is suspended and then resumed |
177 // as soon as the semaphore is released. | 177 // as soon as the semaphore is released. |
178 if(&abb_sem != 0) | 178 if(&abb_sem != 0) |
179 { | 179 { |
180 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); | 180 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
181 } | 181 } |
182 #endif // ABB_SEMAPHORE_PROTECTION | 182 #endif // ABB_SEMAPHORE_PROTECTION |
183 | 183 |
184 // set the ABB page for register access | 184 // set the ABB page for register access |
185 ABB_SetPage(page); | 185 ABB_SetPage(page); |
186 | 186 |
187 // Write value in reg_id | 187 // Write value in reg_id |
188 ABB_WriteRegister(reg_id, value); | 188 ABB_WriteRegister(reg_id, value); |
189 | 189 |
190 // set the ABB page for register access at page 0 | 190 // set the ABB page for register access at page 0 |
191 ABB_SetPage(PAGE0); | 191 ABB_SetPage(PAGE0); |
192 | 192 |
193 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) | 193 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
194 // release the semaphore only if it has correctly been created. | 194 // release the semaphore only if it has correctly been created. |
195 if(&abb_sem != 0) | 195 if(&abb_sem != 0) |
196 { | 196 { |
197 NU_Release_Semaphore(&abb_sem); | 197 NU_Release_Semaphore(&abb_sem); |
198 } | 198 } |
199 #endif // ABB_SEMAPHORE_PROTECTION | 199 #endif // ABB_SEMAPHORE_PROTECTION |
200 | 200 |
201 // Stop the SPI clock | 201 // Stop the SPI clock |
202 #ifdef SPI_CLK_LOW_POWER | 202 #ifdef SPI_CLK_LOW_POWER |
203 SPI_CLK_DISABLE | 203 SPI_CLK_DISABLE |
204 #endif | 204 #endif |
205 } | 205 } |
206 | 206 |
207 | 207 |
208 /*-----------------------------------------------------------------------*/ | 208 /*-----------------------------------------------------------------------*/ |
209 /* ABB_Read_Register_on_page() */ | 209 /* ABB_Read_Register_on_page() */ |
210 /* */ | 210 /* */ |
211 /* This function manages all the spi serial transfer to read one */ | 211 /* This function manages all the spi serial transfer to read one */ |
212 /* ABB register on a specified page. */ | 212 /* ABB register on a specified page. */ |
213 /* */ | 213 /* */ |
214 /* Returns the real data value of the register. */ | 214 /* Returns the real data value of the register. */ |
215 /* */ | 215 /* */ |
216 /*-----------------------------------------------------------------------*/ | 216 /*-----------------------------------------------------------------------*/ |
217 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id) | 217 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id) |
218 { | 218 { |
219 volatile SYS_UWORD16 status; | 219 volatile SYS_UWORD16 status; |
220 SYS_UWORD16 reg_val; | 220 SYS_UWORD16 reg_val; |
221 | 221 |
222 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. | 222 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
223 SPI_Ready_for_RDWR | 223 SPI_Ready_for_RDWR |
224 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 224 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
225 | 225 |
226 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) | 226 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
227 | 227 |
228 // check if the semaphore has been correctly created and try to obtain it. | 228 // check if the semaphore has been correctly created and try to obtain it. |
229 // if the semaphore cannot be obtained, the task is suspended and then resumed | 229 // if the semaphore cannot be obtained, the task is suspended and then resumed |
230 // as soon as the semaphore is released. | 230 // as soon as the semaphore is released. |
231 if(&abb_sem != 0) | 231 if(&abb_sem != 0) |
232 { | 232 { |
233 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); | 233 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
234 } | 234 } |
235 #endif // ABB_SEMAPHORE_PROTECTION | 235 #endif // ABB_SEMAPHORE_PROTECTION |
236 | 236 |
237 /* set the ABB page for register access */ | 237 /* set the ABB page for register access */ |
238 ABB_SetPage(page); | 238 ABB_SetPage(page); |
239 | 239 |
240 /* Read selected ABB register */ | 240 /* Read selected ABB register */ |
241 reg_val = ABB_ReadRegister(reg_id); | 241 reg_val = ABB_ReadRegister(reg_id); |
242 | 242 |
243 /* set the ABB page for register access at page 0 */ | 243 /* set the ABB page for register access at page 0 */ |
244 ABB_SetPage(PAGE0); | 244 ABB_SetPage(PAGE0); |
245 | 245 |
246 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) | 246 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
247 // release the semaphore only if it has correctly been created. | 247 // release the semaphore only if it has correctly been created. |
248 if(&abb_sem != 0) | 248 if(&abb_sem != 0) |
249 { | 249 { |
250 NU_Release_Semaphore(&abb_sem); | 250 NU_Release_Semaphore(&abb_sem); |
251 } | 251 } |
252 #endif // ABB_SEMAPHORE_PROTECTION | 252 #endif // ABB_SEMAPHORE_PROTECTION |
253 | 253 |
254 // Stop the SPI clock | 254 // Stop the SPI clock |
255 #ifdef SPI_CLK_LOW_POWER | 255 #ifdef SPI_CLK_LOW_POWER |
256 SPI_CLK_DISABLE | 256 SPI_CLK_DISABLE |
257 #endif | 257 #endif |
260 } | 260 } |
261 | 261 |
262 /*------------------------------------------------------------------------*/ | 262 /*------------------------------------------------------------------------*/ |
263 /* ABB_free_13M() */ | 263 /* ABB_free_13M() */ |
264 /* */ | 264 /* */ |
265 /* This function sets the 13M clock working in ABB. A wait loop */ | 265 /* This function sets the 13M clock working in ABB. A wait loop */ |
266 /* is required to allow first slow access to ABB clock register. */ | 266 /* is required to allow first slow access to ABB clock register. */ |
267 /* */ | 267 /* */ |
268 /* WARNING !! : this function must not be protected by semaphore !! */ | 268 /* WARNING !! : this function must not be protected by semaphore !! */ |
269 /* */ | 269 /* */ |
270 /*------------------------------------------------------------------------*/ | 270 /*------------------------------------------------------------------------*/ |
271 void ABB_free_13M(void) | 271 void ABB_free_13M(void) |
272 { | 272 { |
273 volatile SYS_UWORD16 status; | 273 volatile SYS_UWORD16 status; |
274 | 274 |
275 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. | 275 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
276 SPI_Ready_for_WR | 276 SPI_Ready_for_WR |
277 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 277 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
278 | 278 |
279 ABB_SetPage(PAGE0); | 279 ABB_SetPage(PAGE0); |
280 | 280 |
281 // This transmission frees the CLK13 in ABB. | 281 // This transmission frees the CLK13 in ABB. |
282 ABB_WriteRegister(TOGBR2, 0x08); | 282 ABB_WriteRegister(TOGBR2, 0x08); |
300 | 300 |
301 /*------------------------------------------------------------------------*/ | 301 /*------------------------------------------------------------------------*/ |
302 /* ABB_stop_13M() */ | 302 /* ABB_stop_13M() */ |
303 /* */ | 303 /* */ |
304 /* This function stops the 13M clock in ABB. */ | 304 /* This function stops the 13M clock in ABB. */ |
305 /* */ | 305 /* */ |
306 /*------------------------------------------------------------------------*/ | 306 /*------------------------------------------------------------------------*/ |
307 void ABB_stop_13M(void) | 307 void ABB_stop_13M(void) |
308 { | 308 { |
309 volatile SYS_UWORD16 status; | 309 volatile SYS_UWORD16 status; |
310 | 310 |
311 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. | 311 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
312 SPI_Ready_for_WR | 312 SPI_Ready_for_WR |
313 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 313 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
314 | 314 |
315 ABB_SetPage(PAGE0); | 315 ABB_SetPage(PAGE0); |
316 | 316 |
317 // Set ACTIVMCLK = 0. | 317 // Set ACTIVMCLK = 0. |
318 ABB_WriteRegister(TOGBR2, 0x04); | 318 ABB_WriteRegister(TOGBR2, 0x04); |
330 | 330 |
331 /*------------------------------------------------------------------------*/ | 331 /*------------------------------------------------------------------------*/ |
332 /* ABB_Read_Status() */ | 332 /* ABB_Read_Status() */ |
333 /* */ | 333 /* */ |
334 /* This function reads and returns the value of VRPCSTS ABB register. */ | 334 /* This function reads and returns the value of VRPCSTS ABB register. */ |
335 /* */ | 335 /* */ |
336 /*------------------------------------------------------------------------*/ | 336 /*------------------------------------------------------------------------*/ |
337 SYS_UWORD16 ABB_Read_Status(void) | 337 SYS_UWORD16 ABB_Read_Status(void) |
338 { | 338 { |
339 volatile SYS_UWORD16 status; | 339 volatile SYS_UWORD16 status; |
340 SYS_UWORD16 reg_val; | 340 SYS_UWORD16 reg_val; |
341 | 341 |
342 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. | 342 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
343 SPI_Ready_for_WR | 343 SPI_Ready_for_WR |
344 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 344 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
345 | 345 |
346 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) | 346 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
347 | 347 |
348 // check if the semaphore has been correctly created and try to obtain it. | 348 // check if the semaphore has been correctly created and try to obtain it. |
349 // if the semaphore cannot be obtained, the task is suspended and then resumed | 349 // if the semaphore cannot be obtained, the task is suspended and then resumed |
350 // as soon as the semaphore is released. | 350 // as soon as the semaphore is released. |
351 if(&abb_sem != 0) | 351 if(&abb_sem != 0) |
352 { | 352 { |
353 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); | 353 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
354 } | 354 } |
355 #endif // ABB_SEMAPHORE_PROTECTION | 355 #endif // ABB_SEMAPHORE_PROTECTION |
356 | 356 |
357 ABB_SetPage(PAGE0); | 357 ABB_SetPage(PAGE0); |
358 | 358 |
359 #if (ANLG_FAM == 1) || (ANLG_FAM == 2) | 359 #if (ANLG_FAM == 1) || (ANLG_FAM == 2) |
360 ABB_SetPage(PAGE0); | 360 ABB_SetPage(PAGE0); |
362 #elif (ANLG_FAM == 3) | 362 #elif (ANLG_FAM == 3) |
363 ABB_SetPage(PAGE1); | 363 ABB_SetPage(PAGE1); |
364 reg_val = ABB_ReadRegister(VRPCCFG); | 364 reg_val = ABB_ReadRegister(VRPCCFG); |
365 #endif | 365 #endif |
366 | 366 |
367 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) | 367 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
368 // release the semaphore only if it has correctly been created. | 368 // release the semaphore only if it has correctly been created. |
369 if(&abb_sem != 0) | 369 if(&abb_sem != 0) |
370 { | 370 { |
371 NU_Release_Semaphore(&abb_sem); | 371 NU_Release_Semaphore(&abb_sem); |
372 } | 372 } |
373 #endif // ABB_SEMAPHORE_PROTECTION | 373 #endif // ABB_SEMAPHORE_PROTECTION |
374 | 374 |
375 // Stop the SPI clock | 375 // Stop the SPI clock |
376 #ifdef SPI_CLK_LOW_POWER | 376 #ifdef SPI_CLK_LOW_POWER |
377 SPI_CLK_DISABLE | 377 SPI_CLK_DISABLE |
378 #endif | 378 #endif |
379 | 379 |
380 return (reg_val); | 380 return (reg_val); |
381 } | 381 } |
382 | 382 |
383 /*------------------------------------------------------------------------*/ | 383 /*------------------------------------------------------------------------*/ |
384 /* ABB_on() */ | 384 /* ABB_on() */ |
385 /* */ | 385 /* */ |
386 /* This function configures ABB registers to work in ON condition */ | 386 /* This function configures ABB registers to work in ON condition */ |
387 /* */ | 387 /* */ |
388 /*------------------------------------------------------------------------*/ | 388 /*------------------------------------------------------------------------*/ |
389 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag) | 389 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag) |
390 { | 390 { |
391 volatile SYS_UWORD16 status; | 391 volatile SYS_UWORD16 status; |
392 #if ((ANLG_FAM ==2) || (ANLG_FAM == 3)) | 392 #if ((ANLG_FAM ==2) || (ANLG_FAM == 3)) |
393 SYS_UWORD32 reg; | 393 SYS_UWORD32 reg; |
394 #endif | 394 #endif |
395 | 395 |
396 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13 | 396 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13 |
397 if (bRecoveryFlag) | 397 if (bRecoveryFlag) |
398 { | 398 { |
399 // RESTITUTE 13MHZ CLOCK TO ABB | 399 // RESTITUTE 13MHZ CLOCK TO ABB |
400 //--------------------------------------------------- | 400 //--------------------------------------------------- |
401 ABB_free_13M(); | 401 ABB_free_13M(); |
402 | 402 |
403 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719) | 403 // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719) |
404 //--------------------------------------------------- | 404 //--------------------------------------------------- |
405 ABB_free_13M(); | 405 ABB_free_13M(); |
406 } | 406 } |
407 | 407 |
408 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. | 408 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
409 SPI_Ready_for_RDWR | 409 SPI_Ready_for_RDWR |
410 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 410 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
411 | 411 |
412 #if (ABB_SEMAPHORE_PROTECTION == 3) | 412 #if (ABB_SEMAPHORE_PROTECTION == 3) |
413 | 413 |
414 // check if the semaphore has been correctly created and try to obtain it. | 414 // check if the semaphore has been correctly created and try to obtain it. |
415 // if the semaphore cannot be obtained, the task is suspended and then resumed | 415 // if the semaphore cannot be obtained, the task is suspended and then resumed |
416 // as soon as the semaphore is released. | 416 // as soon as the semaphore is released. |
417 if(&abb_sem != 0) | 417 if(&abb_sem != 0) |
418 { | 418 { |
419 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); | 419 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
420 } | 420 } |
421 #endif // ABB_SEMAPHORE_PROTECTION | 421 #endif // ABB_SEMAPHORE_PROTECTION |
422 | 422 |
423 ABB_SetPage(PAGE0); | 423 ABB_SetPage(PAGE0); |
424 | 424 |
425 // This transmission disables MADC,AFC,VDL,VUL modules. | 425 // This transmission disables MADC,AFC,VDL,VUL modules. |
426 ABB_WriteRegister(TOGBR1, 0x0155); | 426 ABB_WriteRegister(TOGBR1, 0x0155); |
427 | 427 |
428 #if (ANLG_FAM == 1) | 428 #if (ANLG_FAM == 1) |
429 // This transmission disables Band gap fast mode Enable BB charge. | 429 // This transmission disables Band gap fast mode Enable BB charge. |
430 ABB_WriteRegister(VRPCCTL2, 0x1fc); | 430 ABB_WriteRegister(VRPCCTL2, 0x1fc); |
431 | 431 |
432 /* *********** DC/DC enabling selection ************************************************************** */ | 432 /* *********** DC/DC enabling selection ************************************************************** */ |
433 // This transmission changes the register page in OMEGA for usp to pg1. | 433 // This transmission changes the register page in OMEGA for usp to pg1. |
434 ABB_SetPage(PAGE1); | 434 ABB_SetPage(PAGE1); |
435 | 435 |
442 #else | 442 #else |
443 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05 | 443 vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05 |
444 #endif | 444 #endif |
445 | 445 |
446 if(modules & DCDC) // check if the DCDC is enabled | 446 if(modules & DCDC) // check if the DCDC is enabled |
447 { | 447 { |
448 vrpcctrl3_data |= 0x0002; // set DCDCEN | 448 vrpcctrl3_data |= 0x0002; // set DCDCEN |
449 } | 449 } |
450 | 450 |
451 // This access disables the DCDC. | 451 // This access disables the DCDC. |
452 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data); | 452 ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data); |
453 } | 453 } |
454 | 454 |
455 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */ | 455 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */ |
456 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */ | 456 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */ |
457 /* ***************************************************************************************************/ | 457 /* ***************************************************************************************************/ |
458 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica) | 458 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica) |
459 // This transmission enables Omega test register. | 459 // This transmission enables Omega test register. |
460 ABB_WriteRegister(TAPCTRL, 0x01); | 460 ABB_WriteRegister(TAPCTRL, 0x01); |
461 | 461 |
462 // This transmission select Omega test instruction. | 462 // This transmission select Omega test instruction. |
463 ABB_WriteRegister(TAPREG, TSPTEST1); | 463 ABB_WriteRegister(TAPREG, TSPTEST1); |
464 | 464 |
465 // This transmission disables Omega test register. | 465 // This transmission disables Omega test register. |
466 ABB_WriteRegister(TAPCTRL, 0x00); | 466 ABB_WriteRegister(TAPCTRL, 0x00); |
467 #endif | 467 #endif |
468 /* *************************************************************************************************** */ | 468 /* *************************************************************************************************** */ |
469 | 469 |
470 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue | 470 if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue |
471 { | 471 { |
472 // This transmission changes SIM power supply to 3 volts. | 472 // This transmission changes SIM power supply to 3 volts. |
473 ABB_WriteRegister(VRPCCTRL1, 0x45); | 473 ABB_WriteRegister(VRPCCTRL1, 0x45); |
474 } | 474 } |
475 | 475 |
476 ABB_SetPage(PAGE0); | 476 ABB_SetPage(PAGE0); |
477 | 477 |
478 // This transmission enables selected OMEGA modules. | 478 // This transmission enables selected OMEGA modules. |
479 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6); | 479 ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6); |
480 | 480 |
481 if(modules & MADC) // check if the ADC is enabled | 481 if(modules & MADC) // check if the ADC is enabled |
482 { | 482 { |
483 // This transmission connects the resistive divider to MB and BB. | 483 // This transmission connects the resistive divider to MB and BB. |
484 ABB_WriteRegister(BCICTL1, 0x0005); | 484 ABB_WriteRegister(BCICTL1, 0x0005); |
485 } | 485 } |
486 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) | 486 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
487 // Restore the ABB checks and debouncing if start on TESTRESETZ | 487 // Restore the ABB checks and debouncing if start on TESTRESETZ |
488 | 488 |
489 // This transmission changes the register page in the ABB for usp to pg1. | 489 // This transmission changes the register page in the ABB for usp to pg1. |
490 ABB_SetPage(PAGE1); | 490 ABB_SetPage(PAGE1); |
491 | 491 |
492 // This transmission sets the AFCCK to CKIN/2. | 492 // This transmission sets the AFCCK to CKIN/2. |
493 ABB_WriteRegister(AFCCTLADD, 0x01); | 493 ABB_WriteRegister(AFCCTLADD, 0x01); |
494 | 494 |
495 // This transmission enables the tapreg. | 495 // This transmission enables the tapreg. |
496 ABB_WriteRegister(TAPCTRL, 0x01); | 496 ABB_WriteRegister(TAPCTRL, 0x01); |
497 | 497 |
498 // This transmission enables access to page 2. | 498 // This transmission enables access to page 2. |
499 ABB_WriteRegister(TAPREG, 0x01b); | 499 ABB_WriteRegister(TAPREG, 0x01b); |
500 | 500 |
501 // This transmission changes the register page in the ABB for usp to pg2. | 501 // This transmission changes the register page in the ABB for usp to pg2. |
502 ABB_SetPage(PAGE2); | 502 ABB_SetPage(PAGE2); |
503 | 503 |
504 #if (ANLG_FAM == 2) | 504 #if (ANLG_FAM == 2) |
514 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE | 514 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE |
515 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register | 515 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register |
516 #endif | 516 #endif |
517 // This transmission enables access to page 0. | 517 // This transmission enables access to page 0. |
518 ABB_SetPage(PAGE0); | 518 ABB_SetPage(PAGE0); |
519 | 519 |
520 // reset bit MSKINT1 , if set by TESTRESET | 520 // reset bit MSKINT1 , if set by TESTRESET |
521 reg=ABB_ReadRegister(VRPCSTS) & 0xffe; | 521 reg=ABB_ReadRegister(VRPCSTS) & 0xffe; |
522 | 522 |
523 ABB_WriteRegister(VRPCSTS, reg); | 523 ABB_WriteRegister(VRPCSTS, reg); |
524 | 524 |
525 ABB_SetPage(PAGE2); | 525 ABB_SetPage(PAGE2); |
526 | 526 |
527 // Restore default for BG behavior in sleep mode | 527 // Restore default for BG behavior in sleep mode |
528 ABB_WriteRegister(VRPCAUX, 0xBF); | 528 ABB_WriteRegister(VRPCAUX, 0xBF); |
529 | 529 |
530 // Restore default for deboucing length | 530 // Restore default for deboucing length |
531 ABB_WriteRegister(VRPCLDO, 0x00F); | 531 ABB_WriteRegister(VRPCLDO, 0x00F); |
532 | 532 |
533 // Restore default for INT1 generation, wait time in switch on, checks in switch on | 533 // Restore default for INT1 generation, wait time in switch on, checks in switch on |
534 ABB_WriteRegister(VRPCABBTST, 0x0002); | 534 ABB_WriteRegister(VRPCABBTST, 0x0002); |
535 | 535 |
536 #endif | 536 #endif |
537 | 537 |
538 // This transmission changes the register page in the ABB for usp to pg1. | 538 // This transmission changes the register page in the ABB for usp to pg1. |
539 ABB_SetPage(PAGE1); | 539 ABB_SetPage(PAGE1); |
540 | 540 |
541 // This transmission sets tapinst to id code. | 541 // This transmission sets tapinst to id code. |
542 ABB_WriteRegister(TAPREG, 0x0001); | 542 ABB_WriteRegister(TAPREG, 0x0001); |
543 | 543 |
544 // This transmission disables TAPREG access. | 544 // This transmission disables TAPREG access. |
545 ABB_WriteRegister(TAPCTRL, 0x00); | 545 ABB_WriteRegister(TAPCTRL, 0x00); |
546 | 546 |
547 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows | 547 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows |
548 // This transmission enables BB charge and BB bridge connection for BB measurements. | 548 // This transmission enables BB charge and BB bridge connection for BB measurements. |
549 #if ENABLE_BACKUP_BATTERY | 549 #if ENABLE_BACKUP_BATTERY |
550 ABB_WriteRegister(BCICONF, 0x060); | 550 ABB_WriteRegister(BCICONF, 0x060); |
560 #endif | 560 #endif |
561 | 561 |
562 /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/ | 562 /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/ |
563 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ | 563 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
564 /* ****************************************************************************************************/ | 564 /* ****************************************************************************************************/ |
565 | 565 |
566 // This transmission enables the tapreg. | 566 // This transmission enables the tapreg. |
567 ABB_WriteRegister(TAPCTRL, 0x01); | 567 ABB_WriteRegister(TAPCTRL, 0x01); |
568 | 568 |
569 // This transmission select ABB test instruction. | 569 // This transmission select ABB test instruction. |
570 ABB_WriteRegister(TAPREG, TSPEN); | 570 ABB_WriteRegister(TAPREG, TSPEN); |
571 | 571 |
572 // This transmission changes the register page in ABB for usp to pg0. | 572 // This transmission changes the register page in ABB for usp to pg0. |
573 ABB_SetPage(PAGE0); | 573 ABB_SetPage(PAGE0); |
574 | 574 |
575 // This transmission enables selected ABB modules. | 575 // This transmission enables selected ABB modules. |
576 ABB_WriteRegister(TOGBR1, modules >> 6); | 576 ABB_WriteRegister(TOGBR1, modules >> 6); |
577 | 577 |
578 // enable MB & BB resistive bridges for measurements | 578 // enable MB & BB resistive bridges for measurements |
579 if(modules & MADC) // check if the ADC is enabled | 579 if(modules & MADC) // check if the ADC is enabled |
580 { | 580 { |
581 // This transmission connects the resistive divider to MB and BB. | 581 // This transmission connects the resistive divider to MB and BB. |
582 ABB_WriteRegister(BCICTL1, 0x0001); | 582 ABB_WriteRegister(BCICTL1, 0x0001); |
583 } | 583 } |
584 | 584 |
585 /********* Sleep definition part ******************/ | 585 /********* Sleep definition part ******************/ |
586 // This transmission changes the register page in the ABB for usp to pg1. | 586 // This transmission changes the register page in the ABB for usp to pg1. |
587 #if (ANLG_FAM == 2) | 587 #if (ANLG_FAM == 2) |
588 ABB_SetPage(PAGE1); | 588 ABB_SetPage(PAGE1); |
589 | 589 |
590 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. | 590 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
591 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0; | 591 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
592 | 592 |
593 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg)); | 593 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg)); |
594 | 594 |
595 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value. | 595 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value. |
596 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0; | 596 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0; |
597 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg)); | 597 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg)); |
598 #elif (ANLG_FAM == 3) | 598 #elif (ANLG_FAM == 3) |
599 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY); | 599 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY); |
600 #endif | 600 #endif |
601 // This transmission changes the register page in the ABB for usp to pg0. | 601 // This transmission changes the register page in the ABB for usp to pg0. |
602 ABB_SetPage(PAGE0); | 602 ABB_SetPage(PAGE0); |
603 #endif | 603 #endif |
604 | 604 |
605 // SW workaround for initialization of the audio parts of the ABB to avoid white noise | 605 // SW workaround for initialization of the audio parts of the ABB to avoid white noise |
606 // C.f. BUG1941 | 606 // C.f. BUG1941 |
607 // Set VDLR and VULR bits | 607 // Set VDLR and VULR bits |
608 // Write TOGBR1 register | 608 // Write TOGBR1 register |
609 // This transmission enables selected ABB modules. | 609 // This transmission enables selected ABB modules. |
610 ABB_WriteRegister(TOGBR1, 0x0A); | 610 ABB_WriteRegister(TOGBR1, 0x0A); |
611 | 611 |
612 // wait for 1 ms | 612 // wait for 1 ms |
613 wait_ARM_cycles(convert_nanosec_to_cycles(1000000)); | 613 wait_ARM_cycles(convert_nanosec_to_cycles(1000000)); |
614 | 614 |
615 // Reset VDLS and VULS bits | 615 // Reset VDLS and VULS bits |
616 // Write TOGBR1 register | 616 // Write TOGBR1 register |
617 // This transmission enables selected ABB modules. | 617 // This transmission enables selected ABB modules. |
618 ABB_WriteRegister(TOGBR1, 0x05); | 618 ABB_WriteRegister(TOGBR1, 0x05); |
619 | 619 |
620 #if (ABB_SEMAPHORE_PROTECTION == 3) | 620 #if (ABB_SEMAPHORE_PROTECTION == 3) |
621 // release the semaphore only if it has correctly been created. | 621 // release the semaphore only if it has correctly been created. |
622 if(&abb_sem != 0) | 622 if(&abb_sem != 0) |
623 { | 623 { |
624 NU_Release_Semaphore(&abb_sem); | 624 NU_Release_Semaphore(&abb_sem); |
625 } | 625 } |
626 #endif // ABB_SEMAPHORE_PROTECTION | 626 #endif // ABB_SEMAPHORE_PROTECTION |
627 | 627 |
628 // Stop the SPI clock | 628 // Stop the SPI clock |
629 #ifdef SPI_CLK_LOW_POWER | 629 #ifdef SPI_CLK_LOW_POWER |
630 SPI_CLK_DISABLE | 630 SPI_CLK_DISABLE |
631 #endif | 631 #endif |
632 } | 632 } |
633 | 633 |
634 | 634 |
635 | 635 |
636 /*-----------------------------------------------------------------------*/ | 636 /*-----------------------------------------------------------------------*/ |
637 /* ABB_Read_ADC() */ | 637 /* ABB_Read_ADC() */ |
638 /* */ | 638 /* */ |
639 /* This function manages all the spi serial transfer to read all the */ | 639 /* This function manages all the spi serial transfer to read all the */ |
640 /* ABB ADC conversion channels. */ | 640 /* ABB ADC conversion channels. */ |
641 /* Stores the result in Buff parameter. */ | 641 /* Stores the result in Buff parameter. */ |
642 /* */ | 642 /* */ |
643 /*-----------------------------------------------------------------------*/ | 643 /*-----------------------------------------------------------------------*/ |
644 void ABB_Read_ADC(SYS_UWORD16 *Buff) | 644 void ABB_Read_ADC(SYS_UWORD16 *Buff) |
645 { | 645 { |
646 volatile SYS_UWORD16 status; | 646 volatile SYS_UWORD16 status; |
647 | 647 |
648 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. | 648 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
649 SPI_Ready_for_RDWR | 649 SPI_Ready_for_RDWR |
650 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 650 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
651 | 651 |
652 #if (ABB_SEMAPHORE_PROTECTION == 3) | 652 #if (ABB_SEMAPHORE_PROTECTION == 3) |
653 | 653 |
654 // check if the semaphore has been correctly created and try to obtain it. | 654 // check if the semaphore has been correctly created and try to obtain it. |
655 // if the semaphore cannot be obtained, the task is suspended and then resumed | 655 // if the semaphore cannot be obtained, the task is suspended and then resumed |
656 // as soon as the semaphore is released. | 656 // as soon as the semaphore is released. |
657 if(&abb_sem != 0) | 657 if(&abb_sem != 0) |
658 { | 658 { |
659 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); | 659 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
660 } | 660 } |
661 #endif // ABB_SEMAPHORE_PROTECTION | 661 #endif // ABB_SEMAPHORE_PROTECTION |
662 | 662 |
663 // This transmission changes the register page in the ABB for usp to pg0. | 663 // This transmission changes the register page in the ABB for usp to pg0. |
664 ABB_SetPage(PAGE0); | 664 ABB_SetPage(PAGE0); |
665 | 665 |
666 /* Read all ABB ADC registers */ | 666 /* Read all ABB ADC registers */ |
680 #elif (ANLG_FAM == 3) | 680 #elif (ANLG_FAM == 3) |
681 *Buff++ = ABB_ReadRegister(ADIN4REG); | 681 *Buff++ = ABB_ReadRegister(ADIN4REG); |
682 *Buff++ = ABB_ReadRegister(ADIN5REG); | 682 *Buff++ = ABB_ReadRegister(ADIN5REG); |
683 #endif // ANLG_FAM | 683 #endif // ANLG_FAM |
684 | 684 |
685 #if (ABB_SEMAPHORE_PROTECTION == 3) | 685 #if (ABB_SEMAPHORE_PROTECTION == 3) |
686 // release the semaphore only if it has correctly been created. | 686 // release the semaphore only if it has correctly been created. |
687 if(&abb_sem != 0) | 687 if(&abb_sem != 0) |
688 { | 688 { |
689 NU_Release_Semaphore(&abb_sem); | 689 NU_Release_Semaphore(&abb_sem); |
690 } | 690 } |
691 #endif // ABB_SEMAPHORE_PROTECTION | 691 #endif // ABB_SEMAPHORE_PROTECTION |
692 | 692 |
693 // Stop the SPI clock | 693 // Stop the SPI clock |
694 #ifdef SPI_CLK_LOW_POWER | 694 #ifdef SPI_CLK_LOW_POWER |
695 SPI_CLK_DISABLE | 695 SPI_CLK_DISABLE |
696 #endif | 696 #endif |
698 | 698 |
699 | 699 |
700 | 700 |
701 /*-----------------------------------------------------------------------*/ | 701 /*-----------------------------------------------------------------------*/ |
702 /* ABB_Conf_ADC() */ | 702 /* ABB_Conf_ADC() */ |
703 /* */ | 703 /* */ |
704 /* This function manages all the spi serial transfer to: */ | 704 /* This function manages all the spi serial transfer to: */ |
705 /* - select the ABB ADC channels to be converted */ | 705 /* - select the ABB ADC channels to be converted */ |
706 /* - enable/disable EOC interrupt */ | 706 /* - enable/disable EOC interrupt */ |
707 /* */ | 707 /* */ |
708 /*-----------------------------------------------------------------------*/ | 708 /*-----------------------------------------------------------------------*/ |
709 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal) | 709 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal) |
710 { | 710 { |
711 volatile SYS_UWORD16 status; | 711 volatile SYS_UWORD16 status; |
712 SYS_UWORD16 reg_val; | 712 SYS_UWORD16 reg_val; |
713 | 713 |
714 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. | 714 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
715 SPI_Ready_for_RDWR | 715 SPI_Ready_for_RDWR |
716 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 716 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
717 | 717 |
718 #if (ABB_SEMAPHORE_PROTECTION == 3) | 718 #if (ABB_SEMAPHORE_PROTECTION == 3) |
719 | 719 |
720 // check if the semaphore has been correctly created and try to obtain it. | 720 // check if the semaphore has been correctly created and try to obtain it. |
721 // if the semaphore cannot be obtained, the task is suspended and then resumed | 721 // if the semaphore cannot be obtained, the task is suspended and then resumed |
722 // as soon as the semaphore is released. | 722 // as soon as the semaphore is released. |
723 if(&abb_sem != 0) | 723 if(&abb_sem != 0) |
724 { | 724 { |
725 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); | 725 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
726 } | 726 } |
727 #endif // ABB_SEMAPHORE_PROTECTION | 727 #endif // ABB_SEMAPHORE_PROTECTION |
728 | 728 |
729 // This transmission changes the register page in the ABB for usp to pg0. | 729 // This transmission changes the register page in the ABB for usp to pg0. |
730 ABB_SetPage(PAGE0); | 730 ABB_SetPage(PAGE0); |
731 | 731 |
732 /* select ADC channels to be converted */ | 732 /* select ADC channels to be converted */ |
733 #if (ANLG_FAM == 1) | 733 #if (ANLG_FAM == 1) |
734 ABB_WriteRegister(MADCCTRL1, Channels); | 734 ABB_WriteRegister(MADCCTRL1, Channels); |
735 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) | 735 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
736 ABB_WriteRegister(MADCCTRL, Channels); | 736 ABB_WriteRegister(MADCCTRL, Channels); |
737 #endif | 737 #endif |
738 | 738 |
739 reg_val = ABB_ReadRegister(ITMASK); | 739 reg_val = ABB_ReadRegister(ITMASK); |
740 | 740 |
741 // This transmission configure the End Of Conversion IT without modifying other bits in the same register. | 741 // This transmission configure the End Of Conversion IT without modifying other bits in the same register. |
742 if(ItVal == EOC_INTENA) | 742 if(ItVal == EOC_INTENA) |
743 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA); | 743 ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA); |
744 else if(ItVal == EOC_INTMASK) | 744 else if(ItVal == EOC_INTMASK) |
745 ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK); | 745 ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK); |
746 | 746 |
747 #if (ABB_SEMAPHORE_PROTECTION == 3) | 747 #if (ABB_SEMAPHORE_PROTECTION == 3) |
748 // release the semaphore only if it has correctly been created. | 748 // release the semaphore only if it has correctly been created. |
749 if(&abb_sem != 0) | 749 if(&abb_sem != 0) |
750 { | 750 { |
751 NU_Release_Semaphore(&abb_sem); | 751 NU_Release_Semaphore(&abb_sem); |
752 } | 752 } |
753 #endif // ABB_SEMAPHORE_PROTECTION | 753 #endif // ABB_SEMAPHORE_PROTECTION |
754 | 754 |
755 // Stop the SPI clock | 755 // Stop the SPI clock |
756 #ifdef SPI_CLK_LOW_POWER | 756 #ifdef SPI_CLK_LOW_POWER |
757 SPI_CLK_DISABLE | 757 SPI_CLK_DISABLE |
758 #endif | 758 #endif |
763 | 763 |
764 /*------------------------------------------------------------------------*/ | 764 /*------------------------------------------------------------------------*/ |
765 /* ABB_sleep() */ | 765 /* ABB_sleep() */ |
766 /* */ | 766 /* */ |
767 /* This function disables the DCDC and returns to PAGE 0. It stops then */ | 767 /* This function disables the DCDC and returns to PAGE 0. It stops then */ |
768 /* the 13MHz clock in ABB. A wait loop s required to allow */ | 768 /* the 13MHz clock in ABB. A wait loop s required to allow */ |
769 /* first slow access to ABB clock register. */ | 769 /* first slow access to ABB clock register. */ |
770 /* */ | 770 /* */ |
771 /* WARNING !! : this function must not be protected by semaphore !! */ | 771 /* WARNING !! : this function must not be protected by semaphore !! */ |
772 /* */ | 772 /* */ |
773 /* Returns AFC value. */ | 773 /* Returns AFC value. */ |
774 /* */ | 774 /* */ |
775 /*------------------------------------------------------------------------*/ | 775 /*------------------------------------------------------------------------*/ |
776 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) | 776 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
777 { | 777 { |
778 volatile SYS_UWORD16 status; | 778 volatile SYS_UWORD16 status; |
779 SYS_UWORD32 afcout_index; | 779 SYS_UWORD32 afcout_index; |
780 volatile SYS_UWORD16 nb_it; | 780 volatile SYS_UWORD16 nb_it; |
782 | 782 |
783 // table for AFC allowed values during Sleep mode. First 5th elements | 783 // table for AFC allowed values during Sleep mode. First 5th elements |
784 // are related to positive AFC values, last 5th to negative ones. | 784 // are related to positive AFC values, last 5th to negative ones. |
785 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f}; | 785 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f}; |
786 | 786 |
787 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. | 787 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
788 SPI_Ready_for_RDWR | 788 SPI_Ready_for_RDWR |
789 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 789 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
790 | 790 |
791 // COMPUTATION AND PROGRAMMING OF AFC VALUE | 791 // COMPUTATION AND PROGRAMMING OF AFC VALUE |
792 //--------------------------------------------------- | 792 //--------------------------------------------------- |
793 if(afc & 0x1000) | 793 if(afc & 0x1000) |
794 afcout_index = ((afc + 512)>>10) + 1; | 794 afcout_index = ((afc + 512)>>10) + 1; |
795 else | 795 else |
796 afcout_index = (afc + 512)>>10; | 796 afcout_index = (afc + 512)>>10; |
797 | 797 |
798 if (sleep_performed == FRAME_STOP) // Big sleep | 798 if (sleep_performed == FRAME_STOP) // Big sleep |
799 { | 799 { |
800 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) | 800 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
801 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP //////////////////////////// | 801 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP //////////////////////////// |
802 #endif | 802 #endif |
803 | 803 |
804 } | 804 } |
805 else // Deep sleep | 805 else // Deep sleep |
806 { | 806 { |
807 #if(ANLG_FAM == 1) | 807 #if(ANLG_FAM == 1) |
808 // SELECTION OF AFC TEST MODE FOR OMEGA | 808 // SELECTION OF AFC TEST MODE FOR OMEGA |
809 //--------------------------------------------------- | 809 //--------------------------------------------------- |
810 // This test configuration allows access on the AFCOUT register | 810 // This test configuration allows access on the AFCOUT register |
811 ABB_SetPage(PAGE1); | 811 ABB_SetPage(PAGE1); |
812 | 812 |
813 // This transmission enables OMEGA test register. | 813 // This transmission enables OMEGA test register. |
814 ABB_WriteRegister(TAPCTRL, 0x01); | 814 ABB_WriteRegister(TAPCTRL, 0x01); |
815 | 815 |
816 // This transmission selects OMEGA test instruction. | 816 // This transmission selects OMEGA test instruction. |
817 ABB_WriteRegister(TAPREG, AFCTEST); | 817 ABB_WriteRegister(TAPREG, AFCTEST); |
818 | 818 |
819 // Set AFCOUT to 0. | 819 // Set AFCOUT to 0. |
820 ABB_WriteRegister(AFCOUT, 0x00 >> 6); | 820 ABB_WriteRegister(AFCOUT, 0x00 >> 6); |
821 | 821 |
822 ABB_SetPage(PAGE0); | 822 ABB_SetPage(PAGE0); |
823 | 823 |
824 #elif (ANLG_FAM == 2) | 824 #elif (ANLG_FAM == 2) |
825 // This configuration allows access on the AFCOUT register | 825 // This configuration allows access on the AFCOUT register |
826 ABB_SetPage(PAGE1); | 826 ABB_SetPage(PAGE1); |
827 | 827 |
828 // Read AFCCTLADD value and enable USP access to AFCOUT register | 828 // Read AFCCTLADD value and enable USP access to AFCOUT register |
829 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04); | 829 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04); |
830 | 830 |
831 ABB_WriteRegister(AFCCTLADD, reg_val); | 831 ABB_WriteRegister(AFCCTLADD, reg_val); |
832 | 832 |
833 // Set AFCOUT to 0. | 833 // Set AFCOUT to 0. |
834 ABB_WriteRegister(AFCOUT, 0x00); | 834 ABB_WriteRegister(AFCOUT, 0x00); |
835 | 835 |
836 #if ENABLE_BACKUP_BATTERY | 836 #if ENABLE_BACKUP_BATTERY |
837 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge. | 837 // Read BCICONF value and cut the measurement bridge of BB cut the BB charge. |
838 reg_val = ABB_ReadRegister(BCICONF) & 0x039f; | 838 reg_val = ABB_ReadRegister(BCICONF) & 0x039f; |
839 | 839 |
840 ABB_WriteRegister(BCICONF, reg_val); | 840 ABB_WriteRegister(BCICONF, reg_val); |
841 #endif | 841 #endif |
842 | 842 |
843 // Disable the ABB test mode | 843 // Disable the ABB test mode |
844 ABB_WriteRegister(TAPCTRL, 0x00); | 844 ABB_WriteRegister(TAPCTRL, 0x00); |
845 | 845 |
846 ABB_SetPage(PAGE0); | 846 ABB_SetPage(PAGE0); |
847 | 847 |
848 // Read BCICTL1 value and cut the measurement bridge of MB. | 848 // Read BCICTL1 value and cut the measurement bridge of MB. |
849 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe; | 849 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe; |
850 | 850 |
851 ABB_WriteRegister(BCICTL1, reg_val); | 851 ABB_WriteRegister(BCICTL1, reg_val); |
852 #endif | 852 #endif |
853 | 853 |
854 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected | 854 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected |
855 // in Syren during sleep mode. BB charge stays enabled | 855 // in Syren during sleep mode. BB charge stays enabled |
856 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission | 856 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission |
857 // change the register page in IOTA for usp to pg1 | 857 // change the register page in IOTA for usp to pg1 |
858 | 858 |
859 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode | 859 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode |
860 | 860 |
861 ABB_SetPage(PAGE0); | 861 ABB_SetPage(PAGE0); |
862 #endif | 862 #endif |
863 | 863 |
864 // switch off MADC, AFC, AUXDAC, VOICE. | 864 // switch off MADC, AFC, AUXDAC, VOICE. |
865 ABB_WriteRegister(TOGBR1, 0x155); | 865 ABB_WriteRegister(TOGBR1, 0x155); |
866 | 866 |
867 // Switch off Analog supply LDO | 867 // Switch off Analog supply LDO |
868 //----------------------------- | 868 //----------------------------- |
869 #if (ANLG_FAM == 1) | 869 #if (ANLG_FAM == 1) |
870 ABB_SetPage(PAGE1); | 870 ABB_SetPage(PAGE1); |
871 | 871 |
872 // Read VRPCCTL3 register value and switch off VR3. | 872 // Read VRPCCTL3 register value and switch off VR3. |
873 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df; | 873 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df; |
874 | 874 |
875 ABB_WriteRegister(VRPCCTRL3, reg_val); | 875 ABB_WriteRegister(VRPCCTRL3, reg_val); |
876 | 876 |
877 #elif (ANLG_FAM == 2) | 877 #elif (ANLG_FAM == 2) |
878 // Read VRPCSTS register value and extract status of meaningfull inputs. | 878 // Read VRPCSTS register value and extract status of meaningfull inputs. |
879 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070; | 879 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070; |
880 | 880 |
881 #ifdef CONFIG_TARGET_LUNA | 881 #ifdef CONFIG_TARGET_LUNA |
882 if (reg_val == 0x30 && ABB_sleep_allowed) | 882 if (reg_val == 0x30 && ABB_sleep_allowed) |
883 #else | 883 #else |
884 if (reg_val == 0x30) | 884 if (reg_val == 0x30) |
885 #endif | 885 #endif |
886 { | 886 { |
887 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit. | 887 // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit. |
888 ABB_WriteRegister(VRPCDEV, 0x02); | 888 ABB_WriteRegister(VRPCDEV, 0x02); |
889 } | 889 } |
890 | 890 |
891 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read". | 891 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read". |
892 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); | 892 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
893 | 893 |
894 #elif (ANLG_FAM == 3) | 894 #elif (ANLG_FAM == 3) |
895 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed | 895 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed |
896 // start the SLPDLY counter in order to switch the ABB in sleep mode | 896 // start the SLPDLY counter in order to switch the ABB in sleep mode |
897 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission | 897 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission |
898 // set Syren sleep bit | 898 // set Syren sleep bit |
899 /* | 899 /* |
900 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read". | 900 // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read". |
901 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); | 901 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); |
902 */ | 902 */ |
903 #endif | 903 #endif |
904 | 904 |
905 // Switch to low frequency clock | 905 // Switch to low frequency clock |
906 ABB_stop_13M(); | 906 ABB_stop_13M(); |
907 } | 907 } |
908 | 908 |
909 // Stop the SPI clock | 909 // Stop the SPI clock |
910 #ifdef SPI_CLK_LOW_POWER | 910 #ifdef SPI_CLK_LOW_POWER |
925 | 925 |
926 | 926 |
927 /*------------------------------------------------------------------------*/ | 927 /*------------------------------------------------------------------------*/ |
928 /* ABB_wakeup() */ | 928 /* ABB_wakeup() */ |
929 /* */ | 929 /* */ |
930 /* This function sets the 13MHz clock working in ABB. A wait loop */ | 930 /* This function sets the 13MHz clock working in ABB. A wait loop */ |
931 /* is required to allow first slow access to ABB clock register. */ | 931 /* is required to allow first slow access to ABB clock register. */ |
932 /* Then it re-enables DCDC and returns to PAGE 0. */ | 932 /* Then it re-enables DCDC and returns to PAGE 0. */ |
933 /* */ | 933 /* */ |
934 /* WARNING !! : this function must not be protected by semaphore !! */ | 934 /* WARNING !! : this function must not be protected by semaphore !! */ |
935 /* */ | 935 /* */ |
936 /*------------------------------------------------------------------------*/ | 936 /*------------------------------------------------------------------------*/ |
937 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) | 937 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) |
938 { | 938 { |
939 volatile SYS_UWORD16 status; | 939 volatile SYS_UWORD16 status; |
940 SYS_UWORD16 reg_val; | 940 SYS_UWORD16 reg_val; |
941 | 941 |
942 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. | 942 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. |
943 SPI_Ready_for_RDWR | 943 SPI_Ready_for_RDWR |
944 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 944 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
945 | 945 |
946 if (sleep_performed == FRAME_STOP) // Big sleep | 946 if (sleep_performed == FRAME_STOP) // Big sleep |
947 { | 947 { |
948 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) | 948 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
949 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP //////////////////////////// | 949 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP //////////////////////////// |
950 #endif | 950 #endif |
951 } | 951 } |
952 else // Deep sleep | 952 else // Deep sleep |
953 { | 953 { |
954 #if (OP_L1_STANDALONE == 1) | 954 #if (OP_L1_STANDALONE == 1) |
955 #if (CHIPSET == 12) | 955 #if (CHIPSET == 12) |
956 // restore context from | 956 // restore context from |
957 // workaround to set APLL_DIV_CLK( internal PU) at high level | 957 // workaround to set APLL_DIV_CLK( internal PU) at high level |
958 // by default APLL_DIV_CLK is low pulling 80uA on VRIO | 958 // by default APLL_DIV_CLK is low pulling 80uA on VRIO |
959 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0 | 959 // *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0 |
960 // *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode | 960 // *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode |
961 #endif | 961 #endif |
963 | 963 |
964 // Restitutes 13MHZ Clock to ABB | 964 // Restitutes 13MHZ Clock to ABB |
965 ABB_free_13M(); | 965 ABB_free_13M(); |
966 | 966 |
967 // Switch ON Analog supply LDO | 967 // Switch ON Analog supply LDO |
968 #if (ANLG_FAM == 1) | 968 #if (ANLG_FAM == 1) |
969 ABB_SetPage(PAGE1); | 969 ABB_SetPage(PAGE1); |
970 | 970 |
971 // Read VRPCCTL3 register value and switch on VR3. | 971 // Read VRPCCTL3 register value and switch on VR3. |
972 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020; | 972 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020; |
973 | 973 |
974 ABB_WriteRegister(VRPCCTRL3, reg_val); | 974 ABB_WriteRegister(VRPCCTRL3, reg_val); |
975 ABB_SetPage(PAGE0); | 975 ABB_SetPage(PAGE0); |
976 #endif | 976 #endif |
977 | 977 |
978 // This transmission switches on MADC, AFC. | 978 // This transmission switches on MADC, AFC. |
979 ABB_WriteRegister(TOGBR1, 0x280); | 979 ABB_WriteRegister(TOGBR1, 0x280); |
980 | 980 |
981 // This transmission sets the AUXAFC2. | 981 // This transmission sets the AUXAFC2. |
982 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7)); | 982 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7)); |
983 | 983 |
984 // This transmission sets the AUXAFC1. | 984 // This transmission sets the AUXAFC1. |
985 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff)); | 985 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff)); |
986 | 986 |
987 #if (ANLG_FAM == 1) | 987 #if (ANLG_FAM == 1) |
988 // Remove AFC test mode | 988 // Remove AFC test mode |
989 ABB_SetPage(PAGE1); | 989 ABB_SetPage(PAGE1); |
990 | 990 |
991 // This transmission select Omega test instruction. | 991 // This transmission select Omega test instruction. |
992 ABB_WriteRegister(TAPREG, TSPTEST1); | 992 ABB_WriteRegister(TAPREG, TSPTEST1); |
993 | 993 |
994 // Disable test mode selection | 994 // Disable test mode selection |
995 // This transmission disables Omega test register. | 995 // This transmission disables Omega test register. |
996 ABB_WriteRegister(TAPCTRL, 0x00 >> 6); | 996 ABB_WriteRegister(TAPCTRL, 0x00 >> 6); |
997 | 997 |
998 ABB_SetPage(PAGE0); | 998 ABB_SetPage(PAGE0); |
999 | 999 |
1000 #elif (ANLG_FAM == 2) | 1000 #elif (ANLG_FAM == 2) |
1001 ABB_SetPage(PAGE1); | 1001 ABB_SetPage(PAGE1); |
1002 | 1002 |
1003 // Read AFCCTLADD register value and disable USP access to AFCOUT register. | 1003 // Read AFCCTLADD register value and disable USP access to AFCOUT register. |
1004 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04; | 1004 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04; |
1005 | 1005 |
1006 ABB_WriteRegister(AFCCTLADD, reg_val); | 1006 ABB_WriteRegister(AFCCTLADD, reg_val); |
1007 | 1007 |
1008 #if ENABLE_BACKUP_BATTERY | 1008 #if ENABLE_BACKUP_BATTERY |
1009 // Read BCICONF register value and enable BB measurement bridge enable BB charge. | 1009 // Read BCICONF register value and enable BB measurement bridge enable BB charge. |
1010 reg_val = ABB_ReadRegister(BCICONF) | 0x0060; | 1010 reg_val = ABB_ReadRegister(BCICONF) | 0x0060; |
1011 | 1011 |
1012 ABB_WriteRegister(BCICONF, reg_val); | 1012 ABB_WriteRegister(BCICONF, reg_val); |
1013 #endif | 1013 #endif |
1014 | 1014 |
1015 | 1015 |
1016 /* *************************************************************************************************** */ | 1016 /* *************************************************************************************************** */ |
1017 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. | 1017 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
1018 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; | 1018 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
1019 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); | 1019 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
1020 | 1020 |
1021 // Enable the ABB test mode | 1021 // Enable the ABB test mode |
1022 ABB_WriteRegister(TAPCTRL, 0x01); | 1022 ABB_WriteRegister(TAPCTRL, 0x01); |
1023 ABB_WriteRegister(TAPREG, TSPEN); | 1023 ABB_WriteRegister(TAPREG, TSPEN); |
1024 ABB_SetPage(PAGE0); | 1024 ABB_SetPage(PAGE0); |
1025 | 1025 |
1026 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB. | 1026 // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB. |
1027 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001; | 1027 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001; |
1028 | 1028 |
1029 ABB_WriteRegister(BCICTL1, reg_val); | 1029 ABB_WriteRegister(BCICTL1, reg_val); |
1030 #endif | 1030 #endif |
1031 | 1031 |
1032 #if (ANLG_FAM == 3) | 1032 #if (ANLG_FAM == 3) |
1033 | 1033 |
1034 ABB_SetPage(PAGE1); | 1034 ABB_SetPage(PAGE1); |
1035 | 1035 |
1036 /* *************************************************************************************************** */ | 1036 /* *************************************************************************************************** */ |
1037 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. | 1037 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. |
1038 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; | 1038 reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; |
1039 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); | 1039 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); |
1040 | 1040 |
1041 /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/ | 1041 /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/ |
1042 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ | 1042 /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ |
1043 /* ****************************************************************************************************/ | 1043 /* ****************************************************************************************************/ |
1044 | 1044 |
1045 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register | 1045 ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register |
1046 // This transmission enables IOTA test register | 1046 // This transmission enables IOTA test register |
1047 | 1047 |
1048 ABB_WriteRegister(TAPREG, TSPEN); | 1048 ABB_WriteRegister(TAPREG, TSPEN); |
1049 // This transmission select IOTA test instruction | 1049 // This transmission select IOTA test instruction |
1050 // This transmission select IOTA test instruction | 1050 // This transmission select IOTA test instruction |
1051 /**************************************************************************************************** */ | 1051 /**************************************************************************************************** */ |
1052 | 1052 |
1053 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission | 1053 ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission |
1054 #endif | 1054 #endif |
1055 } | 1055 } |
1056 | 1056 |
1057 // Stop the SPI clock | 1057 // Stop the SPI clock |
1058 #ifdef SPI_CLK_LOW_POWER | 1058 #ifdef SPI_CLK_LOW_POWER |
1059 SPI_CLK_DISABLE | 1059 SPI_CLK_DISABLE |
1060 #endif | 1060 #endif |
1064 /* ABB_wa_VRPC() */ | 1064 /* ABB_wa_VRPC() */ |
1065 /* */ | 1065 /* */ |
1066 /* This function initializes the VRPCCTRL1 or VRPCSIM register */ | 1066 /* This function initializes the VRPCCTRL1 or VRPCSIM register */ |
1067 /* according to the ABB used. */ | 1067 /* according to the ABB used. */ |
1068 /* */ | 1068 /* */ |
1069 /*------------------------------------------------------------------------*/ | 1069 /*------------------------------------------------------------------------*/ |
1070 void ABB_wa_VRPC(SYS_UWORD16 value) | 1070 void ABB_wa_VRPC(SYS_UWORD16 value) |
1071 { | 1071 { |
1072 volatile SYS_UWORD16 status; | 1072 volatile SYS_UWORD16 status; |
1073 | 1073 |
1074 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. | 1074 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
1075 SPI_Ready_for_WR | 1075 SPI_Ready_for_WR |
1076 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 1076 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
1077 | 1077 |
1078 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) | 1078 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
1079 | 1079 |
1080 // check if the semaphore has been correctly created and try to obtain it. | 1080 // check if the semaphore has been correctly created and try to obtain it. |
1081 // if the semaphore cannot be obtained, the task is suspended and then resumed | 1081 // if the semaphore cannot be obtained, the task is suspended and then resumed |
1082 // as soon as the semaphore is released. | 1082 // as soon as the semaphore is released. |
1083 if(&abb_sem != 0) | 1083 if(&abb_sem != 0) |
1084 { | 1084 { |
1085 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); | 1085 NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); |
1086 } | 1086 } |
1087 #endif // ABB_SEMAPHORE_PROTECTION | 1087 #endif // ABB_SEMAPHORE_PROTECTION |
1088 | 1088 |
1089 ABB_SetPage(PAGE1); | 1089 ABB_SetPage(PAGE1); |
1090 | 1090 |
1091 #if (ANLG_FAM == 1) | 1091 #if (ANLG_FAM == 1) |
1092 // This transmission initializes the VRPCCTL1 register. | 1092 // This transmission initializes the VRPCCTL1 register. |
1093 ABB_WriteRegister(VRPCCTRL1, value); | 1093 ABB_WriteRegister(VRPCCTRL1, value); |
1094 | 1094 |
1095 #elif (ANLG_FAM == 2) | 1095 #elif (ANLG_FAM == 2) |
1096 // This transmission initializes the VRPCSIM register. | 1096 // This transmission initializes the VRPCSIM register. |
1097 ABB_WriteRegister(VRPCSIM, value); | 1097 ABB_WriteRegister(VRPCSIM, value); |
1098 | 1098 |
1099 #elif (ANLG_FAM == 3) | 1099 #elif (ANLG_FAM == 3) |
1100 // This transmission initializes the VRPCSIMR register. | 1100 // This transmission initializes the VRPCSIMR register. |
1101 ABB_WriteRegister(VRPCSIMR, value); | 1101 ABB_WriteRegister(VRPCSIMR, value); |
1102 | 1102 |
1103 #endif | 1103 #endif |
1104 | 1104 |
1105 ABB_SetPage(PAGE0); | 1105 ABB_SetPage(PAGE0); |
1106 | 1106 |
1107 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) | 1107 #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) |
1108 // release the semaphore only if it has correctly been created. | 1108 // release the semaphore only if it has correctly been created. |
1109 if(&abb_sem != 0) | 1109 if(&abb_sem != 0) |
1110 { | 1110 { |
1111 NU_Release_Semaphore(&abb_sem); | 1111 NU_Release_Semaphore(&abb_sem); |
1112 } | 1112 } |
1113 #endif // ABB_SEMAPHORE_PROTECTION | 1113 #endif // ABB_SEMAPHORE_PROTECTION |
1114 | 1114 |
1115 // Stop the SPI clock | 1115 // Stop the SPI clock |
1116 #ifdef SPI_CLK_LOW_POWER | 1116 #ifdef SPI_CLK_LOW_POWER |
1117 SPI_CLK_DISABLE | 1117 SPI_CLK_DISABLE |
1118 #endif | 1118 #endif |
1122 /*-----------------------------------------------------------------------*/ | 1122 /*-----------------------------------------------------------------------*/ |
1123 /* ABB_Write_Uplink_Data() */ | 1123 /* ABB_Write_Uplink_Data() */ |
1124 /* */ | 1124 /* */ |
1125 /* This function uses the SPI to write to ABB uplink buffer. */ | 1125 /* This function uses the SPI to write to ABB uplink buffer. */ |
1126 /* */ | 1126 /* */ |
1127 /*-----------------------------------------------------------------------*/ | 1127 /*-----------------------------------------------------------------------*/ |
1128 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data) | 1128 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data) |
1129 { | 1129 { |
1130 SYS_UWORD8 i; | 1130 SYS_UWORD8 i; |
1131 volatile SYS_UWORD16 status; | 1131 volatile SYS_UWORD16 status; |
1132 | 1132 |
1133 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. | 1133 // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. |
1134 SPI_Ready_for_WR | 1134 SPI_Ready_for_WR |
1135 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; | 1135 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; |
1136 | 1136 |
1137 // Select Page 0 for TOGBR2 | 1137 // Select Page 0 for TOGBR2 |
1138 ABB_SetPage(PAGE0); | 1138 ABB_SetPage(PAGE0); |
1139 | 1139 |
1140 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2 | 1140 // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2 |
1141 ABB_WriteRegister(TOGBR2, 0x10); | 1141 ABB_WriteRegister(TOGBR2, 0x10); |
1142 | 1142 |
1143 // Clear, assuming that it works like IBUFPTR of Vega | 1143 // Clear, assuming that it works like IBUFPTR of Vega |
1144 ABB_WriteRegister(TOGBR2, 0x0); | 1144 ABB_WriteRegister(TOGBR2, 0x0); |
1145 | 1145 |
1146 // Write the ramp data | 1146 // Write the ramp data |
1147 for (i=0;i<16;i++) | 1147 for (i=0;i<16;i++) |
1148 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6); | 1148 ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6); |
1149 | 1149 |
1150 // Stop the SPI clock | 1150 // Stop the SPI clock |
1151 #ifdef SPI_CLK_LOW_POWER | 1151 #ifdef SPI_CLK_LOW_POWER |
1152 SPI_CLK_DISABLE | 1152 SPI_CLK_DISABLE |
1153 #endif | 1153 #endif |
1163 volatile SYS_UWORD16 status,sl_ldo_stat; | 1163 volatile SYS_UWORD16 status,sl_ldo_stat; |
1164 | 1164 |
1165 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission | 1165 ABB_SetPage(PAGE1); // Initialize transmit register. This transmission |
1166 // change the register page in ABB for usp to pg1 | 1166 // change the register page in ABB for usp to pg1 |
1167 | 1167 |
1168 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value | 1168 ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value |
1169 | 1169 |
1170 sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374); | 1170 sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374); |
1171 | 1171 |
1172 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration | 1172 ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration |
1173 | 1173 |
1174 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission | 1174 ABB_SetPage(PAGE0); // Initialize transmit register. This transmission |
1175 // change the register page in ABB for usp to pg0 | 1175 // change the register page in ABB for usp to pg0 |
1176 } | 1176 } |
1177 #endif | 1177 #endif |
1181 /*-----------------------------------------------------------------------*/ | 1181 /*-----------------------------------------------------------------------*/ |
1182 /* ABB_Power_Off() */ | 1182 /* ABB_Power_Off() */ |
1183 /* */ | 1183 /* */ |
1184 /* This function uses the SPI to switch off the ABB. */ | 1184 /* This function uses the SPI to switch off the ABB. */ |
1185 /* */ | 1185 /* */ |
1186 /*-----------------------------------------------------------------------*/ | 1186 /*-----------------------------------------------------------------------*/ |
1187 void ABB_Power_Off(void) | 1187 void ABB_Power_Off(void) |
1188 { | 1188 { |
1189 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks). | 1189 // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks). |
1190 NU_Sleep (30); | 1190 NU_Sleep (30); |
1191 | 1191 |
1192 // Wait also until <ON/OFF> key is released. | 1192 // Wait also until <ON/OFF> key is released. |
1193 // This is needed to avoid, if the power key is pressed for a long time, to switch | 1193 // This is needed to avoid, if the power key is pressed for a long time, to switch |
1194 // ON-switch OFF the mobile, until the power key is released. | 1194 // ON-switch OFF the mobile, until the power key is released. |
1195 #if((ANLG_FAM == 1) || (ANLG_FAM == 2)) | 1195 #if((ANLG_FAM == 1) || (ANLG_FAM == 2)) |
1196 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) { | 1196 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) { |
1197 #elif(ANLG_FAM == 3) | 1197 #elif(ANLG_FAM == 3) |
1198 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) { | 1198 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) { |
1199 #endif | 1199 #endif |
1200 | 1200 |
1201 NU_Sleep (1); } | 1201 NU_Sleep (1); } |
1202 | 1202 |
1203 BZ_KeyBeep_OFF(); | 1203 BZ_KeyBeep_OFF(); |
1204 | 1204 |
1205 #if(ANLG_FAM == 1) | 1205 #if(ANLG_FAM == 1) |
1206 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE); | 1206 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE); |
1207 #elif((ANLG_FAM == 2) || (ANLG_FAM == 3)) | 1207 #elif((ANLG_FAM == 2) || (ANLG_FAM == 3)) |
1208 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001); | 1208 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001); |
1209 #endif | 1209 #endif |
1210 } | 1210 } |
1211 #endif | 1211 #endif |
1212 | 1212 |
1213 | 1213 |
1214 | 1214 |