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comparison src/g23m-aci/uart/uart_kers.c @ 1:fa8dc04885d8

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src/g23m-*: import from Magnetite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 16 Oct 2020 06:25:50 +0000
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0:4e78acac3d88 1:fa8dc04885d8
1 /*
2 +-----------------------------------------------------------------------------
3 | Project :
4 | Modul :
5 +-----------------------------------------------------------------------------
6 | Copyright 2002 Texas Instruments Berlin, AG
7 | All rights reserved.
8 |
9 | This file is confidential and a trade secret of Texas
10 | Instruments Berlin, AG
11 | The receipt of or possession of this file does not convey
12 | any rights to reproduce or disclose its contents or to
13 | manufacture, use, or sell anything it may describe, in
14 | whole, or in part, without the specific written consent of
15 | Texas Instruments Berlin, AG.
16 +-----------------------------------------------------------------------------
17 | Purpose : This modul is part of the entity UART and implements all
18 | functions to handles the incoming process internal signals as
19 | described in the SDL-documentation (KER-statemachine)
20 +-----------------------------------------------------------------------------
21 */
22
23 #ifndef UART_KERS_C
24 #define UART_KERS_C
25 #endif /* !UART_KERS_C */
26
27 #define ENTITY_UART
28
29 /*
30 * Turn off spurious LINT warnings
31 */
32 /*lint -e415 access of out-of-bounds pointer */
33
34 /*==== INCLUDES =============================================================*/
35
36 #ifdef WIN32
37 #include "nucleus.h"
38 #endif /* WIN32 */
39 #include "typedefs.h" /* to get Condat data types */
40 #include "vsi.h" /* to get a lot of macros */
41 #include "macdef.h" /* to get a lot of macros */
42 #include "custom.h"
43 #include "gsm.h" /* to get a lot of macros */
44 #include "cnf_uart.h" /* to get cnf-definitions */
45 #include "mon_uart.h" /* to get mon-definitions */
46 #include "prim.h" /* to get the definitions of used SAP and directions */
47 #include "dti.h" /* to get dti lib */
48 #include "pei.h" /* to get PEI interface */
49 #ifdef FF_MULTI_PORT
50 #include "gsi.h" /* to get definitions of serial driver */
51 #else /* FF_MULTI_PORT */
52 #ifdef _TARGET_
53 #include "uart/serialswitch.h"
54 #include "uart/traceswitch.h"
55 #else /* _TARGET_ */
56 #include "serial_dat.h" /* to get definitions of serial driver */
57 #endif /* _TARGET_ */
58 #endif /* FF_MULTI_PORT */
59 #include "uart.h" /* to get the global entity definitions */
60
61 #ifdef FF_MULTI_PORT
62 #include "uart_ptxs.h" /* to get signal definitions for service TX */
63 #include "uart_prxs.h" /* to get rx signals */
64 #else /* FF_MULTI_PORT */
65 #include "uart_txs.h" /* to get signal definitions of service TX */
66 #include "uart_rxs.h" /* to get signal definitions of service RX */
67 #endif /* FF_MULTI_PORT */
68 #include "uart_dtxs.h" /* to get signal definitions of service DTX */
69 #include "uart_drxs.h" /* to get signal definitions of service DRX */
70 #include "uart_kerf.h" /* to get function definitions of service KER */
71 #include "uart_rts.h" /* to get signal definitions of service RT */
72
73 #ifndef _TARGET_
74 #include <stdio.h> /* to get sprintf */
75 #endif /* !_TARGET_ */
76 #include <string.h> /* JK, delete warnings: to get memcpy */
77
78 /*==== CONST ================================================================*/
79
80 /*==== LOCAL VARS ===========================================================*/
81
82 /*==== PRIVATE FUNCTIONS ====================================================*/
83
84 /*==== PUBLIC FUNCTIONS =====================================================*/
85
86
87
88 /*
89 +------------------------------------------------------------------------------
90 | Function : sig_drx_ker_line_states_ind
91 +------------------------------------------------------------------------------
92 | Description : Handles the internal signal SIG_DRX_KER_LINE_STATES_IND
93 |
94 | Parameters : dlc_instance - dlc instance wich belongs to calling DRX
95 | st_flow - flow control state (X bit)
96 | st_line_sa - line state SA
97 | st_line_sa - line state SB
98 | st_break_len - break state
99 |
100 +------------------------------------------------------------------------------
101 */
102 GLOBAL void sig_drx_ker_line_states_ind(UBYTE dlc_instance,
103 UBYTE st_flow,
104 UBYTE st_line_sa,
105 UBYTE st_line_sb,
106 USHORT st_break_len)
107 {
108 T_DLC* dlc;
109 ULONG old_lines;
110 ULONG new_lines;
111
112 TRACE_ISIG( "sig_drx_ker_line_states_ind" );
113
114 /*
115 * set DLC
116 */
117 dlc = &uart_data->dlc_table[dlc_instance];
118
119 switch( GET_STATE( UART_SERVICE_KER ) )
120 {
121 case KER_READY:
122 /*
123 * check for changed line states
124 */
125 old_lines = dlc->lines & (UART_SA_TX_MASK |
126 UART_SB_TX_MASK |
127 UART_X_TX_MASK |
128 UART_BRK_TX_MASK);
129 new_lines = ((ULONG)st_line_sa << UART_SA_TX_POS) |
130 ((ULONG)st_line_sb << UART_SB_TX_POS) |
131 ((ULONG)st_flow << UART_X_TX_POS);
132 if(st_break_len NEQ DTI_BREAK_OFF)
133 {
134 TRACE_EVENT("send Break");
135 new_lines|= UART_BRK_TX_MASK;
136 }
137
138 if(old_lines NEQ new_lines)
139 {
140 /*
141 * trace changes
142 */
143 if(new_lines & UART_X_TX_MASK)
144 {
145 if(!(old_lines & UART_X_TX_MASK))
146 {
147 TRACE_EVENT("TX Flow Control: stop");
148 }
149 }
150 else if(old_lines & UART_X_TX_MASK)
151 {
152 TRACE_EVENT("TX Flow Control: start");
153 }
154
155 if(new_lines & UART_SA_TX_MASK)
156 {
157 if(!(old_lines & UART_SA_TX_MASK))
158 {
159 TRACE_EVENT("DSR: off");
160 }
161 }
162 else if(old_lines & UART_SA_TX_MASK)
163 {
164 TRACE_EVENT("DSR: on");
165 }
166
167 if(new_lines & UART_SB_TX_MASK)
168 {
169 if(!(old_lines & UART_SB_TX_MASK))
170 {
171 TRACE_EVENT("DCD: off");
172 }
173 }
174 else if(old_lines & UART_SB_TX_MASK)
175 {
176 TRACE_EVENT("DCD: on");
177 }
178
179 /*
180 * send new line states
181 * but flush UART before
182 */
183 dlc->lines&= ~(UART_SA_TX_MASK |
184 UART_SB_TX_MASK |
185 UART_X_TX_MASK |
186 UART_BRK_TX_MASK |
187 UART_BRKLEN_TX_MASK);
188
189 if(st_break_len NEQ DTI_BREAK_OFF)
190 new_lines|= ((ULONG)st_break_len << UART_BRKLEN_TX_POS);
191
192 dlc->lines|= new_lines;
193
194 dlc->received_prim|= UART_DTI_DATA_REQ_MASK;
195
196 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
197 {
198 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
199 sig_ker_tx_flush_req();
200 }
201 }
202 break;
203
204 case KER_MUX:
205 /*
206 * check for changed line states
207 */
208 old_lines = dlc->lines & (UART_CTS_MASK |
209 UART_DSR_MASK |
210 UART_DCD_MASK |
211 UART_BRK_TX_MASK);
212 new_lines = ((ULONG)st_flow << UART_CTS_POS) |
213 ((ULONG)st_line_sa << UART_DSR_POS) |
214 ((ULONG)st_line_sb << UART_DCD_POS);
215
216 if(st_break_len NEQ DTI_BREAK_OFF)
217 {
218 TRACE_EVENT_P1("send Break - DLCI=%d", dlc->dlci);
219 new_lines|= UART_BRK_TX_MASK;
220 }
221
222 if(old_lines NEQ new_lines)
223 {
224 /*
225 * trace changes
226 */
227 if(new_lines & UART_CTS_MASK)
228 {
229 if(!(old_lines & UART_CTS_MASK))
230 {
231 TRACE_EVENT_P1("TX Flow Control: stop - DLCI=%d", dlc->dlci);
232 }
233 }
234 else if(old_lines & UART_CTS_MASK)
235 {
236 TRACE_EVENT_P1("TX Flow Control: start - DLCI=%d", dlc->dlci);
237 }
238
239 if(new_lines & UART_DSR_MASK)
240 {
241 if(!(old_lines & UART_DSR_MASK))
242 {
243 TRACE_EVENT_P1("DSR: off - DLCI=%d", dlc->dlci);
244 }
245 }
246 else if(old_lines & UART_DSR_MASK)
247 {
248 TRACE_EVENT_P1("DSR: on - DLCI=%d", dlc->dlci);
249 }
250
251 if(new_lines & UART_DCD_MASK)
252 {
253 if(!(old_lines & UART_DCD_MASK))
254 {
255 TRACE_EVENT_P1("DCD: off - DLCI=%d", dlc->dlci);
256 }
257 }
258 else if(old_lines & UART_DCD_MASK)
259 {
260 TRACE_EVENT_P1("DCD: on - DLCI=%d", dlc->dlci);
261 }
262 /*
263 * build and send MSC command
264 */
265 dlc->lines&= ~(UART_CTS_MASK |
266 UART_DSR_MASK |
267 UART_DCD_MASK |
268 UART_BRK_TX_MASK |
269 UART_BRKLEN_TX_MASK);
270
271 if(st_break_len NEQ DTI_BREAK_OFF)
272 new_lines|= ((ULONG)st_break_len << UART_BRKLEN_TX_POS);
273
274 dlc->lines|= new_lines;
275 ker_mux_send_line_states(dlc_instance);
276 }
277 break;
278
279 default:
280 TRACE_ERROR( "SIG_DRX_KER_LINE_STATES_IND unexpected" );
281 break;
282 }
283 } /* sig_drx_ker_line_states_ind() */
284
285
286
287 /*
288 +------------------------------------------------------------------------------
289 | Function : sig_dtx_ker_enable_ind
290 +------------------------------------------------------------------------------
291 | Description : Handles the internal signal SIG_DTX_KER_ENABLE_IND
292 |
293 | Parameters : dlc_instance - dlc instance wich belongs to calling DTX
294 |
295 +------------------------------------------------------------------------------
296 */
297 GLOBAL void sig_dtx_ker_enable_ind (UBYTE dlc_instance)
298 {
299 TRACE_ISIG( "sig_dtx_ker_enable_ind" );
300
301 switch( GET_STATE( UART_SERVICE_KER ) )
302 {
303 case KER_MUX:
304 /*
305 * build and send MSC command
306 * enable flow control in line states
307 */
308 uart_data->dlc_table[dlc_instance].lines&= ~UART_FC_TX_MASK;
309 /*
310 * send new line states
311 */
312 ker_mux_send_line_states(dlc_instance);
313 break;
314
315 case KER_READY:
316 break;
317
318 default:
319 TRACE_ERROR( "SIG_DTX_KER_ENABLE_IND unexpected" );
320 break;
321 }
322 } /* sig_dtx_ker_enable_ind() */
323
324
325
326 /*
327 +------------------------------------------------------------------------------
328 | Function : sig_dtx_ker_disable_ind
329 +------------------------------------------------------------------------------
330 | Description : Handles the internal signal SIG_DTX_KER_DISABLE_IND
331 |
332 | Parameters : dlc_instance - dlc instance wich belongs to calling DTX
333 |
334 +------------------------------------------------------------------------------
335 */
336 GLOBAL void sig_dtx_ker_disable_ind (UBYTE dlc_instance)
337 {
338 TRACE_ISIG( "sig_dtx_ker_disable_ind" );
339
340 switch( GET_STATE( UART_SERVICE_KER ) )
341 {
342 case KER_MUX:
343 /*
344 * build and send MSC command
345 * disable flow control in line states
346 */
347 uart_data->dlc_table[dlc_instance].lines|= UART_FC_TX_MASK;
348 /*
349 * send new line states
350 */
351 ker_mux_send_line_states(dlc_instance);
352 break;
353
354 case KER_READY:
355 break;
356
357 default:
358 TRACE_ERROR( "SIG_DTX_KER_DISABLE_IND unexpected" );
359 break;
360 }
361 } /* sig_dtx_ker_disable_ind() */
362
363
364
365 /*
366 +------------------------------------------------------------------------------
367 | Function : sig_dtx_ker_escape_detected_ind
368 +------------------------------------------------------------------------------
369 | Description : Handles the internal signal SIG_DTX_KER_ESCAPE_DETECTED_IND
370 |
371 | Parameters : dlc_instance - dlc instance wich belongs to calling DTX
372 |
373 +------------------------------------------------------------------------------
374 */
375 GLOBAL void sig_dtx_ker_escape_detected_ind (U8 dlc_instance)
376 {
377 T_DLC *dlc;
378
379 TRACE_FUNCTION( "sig_dtx_ker_escape_detected_ind" );
380
381 /*
382 * set DLC
383 */
384 dlc = &uart_data->dlc_table[dlc_instance];
385 {
386 PALLOC (uart_detected_ind, UART_DETECTED_IND);
387 uart_detected_ind->device = uart_data->device;
388 uart_detected_ind->dlci = dlc->dlci;
389 uart_detected_ind->cause = UART_DETECT_ESC;
390 PSEND (hCommMMI, uart_detected_ind);
391 }
392 } /* sig_dtx_ker_escape_detected_ind() */
393
394
395
396 /*
397 +------------------------------------------------------------------------------
398 | Function : sig_any_ker_flushed_ind
399 +------------------------------------------------------------------------------
400 | Description : Handles the internal signal SIG_ANY_KER_FLUSHED_IND
401 |
402 | Parameters : dlc_instance - dlc instance wich belongs to this signal
403 |
404 +------------------------------------------------------------------------------
405 */
406 GLOBAL void sig_any_ker_flushed_ind (UBYTE dlc_instance)
407 {
408 T_DLC* dlc;
409 UBYTE i;
410
411 TRACE_ISIG( "sig_any_ker_flushed_ind" );
412
413 /*
414 * reset flush indicator
415 */
416 dlc = &uart_data->dlc_table[dlc_instance];
417 dlc->flushed = TRUE;
418 /*
419 * if the primitive which has triggered the flush belongs to the whole port
420 * we will check each DLC for flush, if it only belongs to this DLC we start
421 * TX flushing immediately
422 */
423 if(uart_data->ker.received_prim)
424 {
425 /*
426 * check each DLC
427 */
428 for(i = 0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
429 {
430 dlc = &uart_data->dlc_table[i];
431 if(dlc->flushed NEQ TRUE)
432 return;
433 }
434 }
435 /*
436 * start TX flushing
437 */
438 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
439 sig_ker_tx_flush_req();
440 } /* sig_any_ker_flushed_ind() */
441
442
443
444 /*
445 +------------------------------------------------------------------------------
446 | Function : sig_tx_ker_flushed_ind
447 +------------------------------------------------------------------------------
448 | Description : Handles the internal signal SIG_TX_KER_FLUSHED_IND
449 |
450 | Parameters : no parameters
451 |
452 +------------------------------------------------------------------------------
453 */
454 GLOBAL void sig_tx_ker_flushed_ind ()
455 {
456 T_DLC* dlc;
457 UBYTE i;
458 #ifndef _SIMULATION_
459 USHORT error_code;
460 #endif
461 TRACE_ISIG( "sig_tx_ker_flushed_ind" );
462
463 if(uart_data->ker.flush_state EQ UART_KER_TX_FLUSH)
464 {
465 /*
466 * primitives of the port
467 */
468 /*
469 * UART_PARAMETERS_REQ
470 */
471 if(uart_data->ker.received_prim & UART_PARAMETERS_REQ_MASK)
472 {
473 /*
474 * disable UART while set new communication parameters
475 */
476 #ifdef _SIMULATION_
477 {
478 /*
479 * send DTI_GETDATA_REQ
480 */
481 PALLOC (dti_getdata_req, DTI2_GETDATA_REQ);
482 dti_getdata_req->link_id = LINK_DISABLE_PORT_1; /* for disable */
483 PSEND (hCommMMI, dti_getdata_req);
484 }
485 #else /* _SIMULATION_ */
486 #ifndef FF_MULTI_PORT
487 if((error_code = UF_Enable (uart_data->device, FALSE)) NEQ UF_OK)
488 {
489 TRACE_ERROR_P2("UF Driver: Can't disable UART, [%d], uart_kerp.c(%d)",
490 error_code,__LINE__);
491 }
492 #endif /* !FF_MULTI_PORT */
493 #endif /* _SIMULATION */
494 /*
495 * set new parameters
496 */
497 ker_setupUart();
498 #ifdef _SIMULATION_
499 {
500 /*
501 * send DTI_GETDATA_REQ
502 */
503 PALLOC (dti_getdata_req, DTI2_GETDATA_REQ);
504 dti_getdata_req->link_id = LINK_ENABLE_PORT_1; /* for enable */
505 PSEND (hCommMMI, dti_getdata_req);
506 }
507 #else /* _SIMULATION_ */
508 #ifndef FF_MULTI_PORT
509 if((error_code = UF_Enable (uart_data->device, TRUE)) NEQ UF_OK)
510 {
511 TRACE_ERROR_P2("UF Driver: Can't enable UART, [%d], uart_kerp.c(%d)",
512 error_code,__LINE__);
513 }
514 #endif /* !FF_MULTI_PORT */
515 #endif /* _SIMULATION */
516 /*
517 * restart suspended read and write procedures
518 */
519 sig_ker_tx_restart_write_req();
520 sig_ker_rx_restart_read_req();
521 /*
522 * send confirm primitive
523 */
524 {
525 PALLOC (uart_parameters_cnf, UART_PARAMETERS_CNF);
526 uart_parameters_cnf->device = uart_data->device;
527 PSEND (hCommMMI, uart_parameters_cnf);
528 }
529 }
530
531 /*
532 * UART_DISABLE_REQ
533 */
534 if(uart_data->ker.received_prim & UART_DISABLE_REQ_MASK)
535 {
536 switch( GET_STATE( UART_SERVICE_KER ) )
537 {
538 case KER_MUX:
539 case KER_MUX_ESTABLISH:
540 case KER_MUX_DLC_CLOSING:
541 case KER_MUX_CLOSING:
542 case KER_MUX_CLOSED:
543 /*
544 * stop timers and
545 * remove all DLC instances
546 */
547 ker_mux_close_down();
548 break;
549
550 case KER_READY:
551 /*
552 * close dlc channel
553 */
554 ker_mux_dlc_release(UART_CONTROL_INSTANCE);
555 break;
556
557 case KER_DEAD:
558 break;
559
560 default:
561 TRACE_ERROR( "SIG_TX_KER_FLUSHED_IND unexpected" );
562 break;
563 }
564
565 SET_STATE( UART_SERVICE_KER, KER_DEAD );
566
567 /*
568 * disable UART
569 */
570 #ifdef _SIMULATION_
571 {
572 /*
573 * send DTI_GETDATA_REQ
574 */
575 PALLOC (dti_getdata_req, DTI2_GETDATA_REQ);
576 dti_getdata_req->link_id = LINK_DISABLE_PORT_1; /* for disable */
577 PSEND (hCommMMI, dti_getdata_req);
578 }
579 #else /* _SIMULATION_ */
580 #ifndef FF_MULTI_PORT
581 if((error_code = UF_Enable (uart_data->device, FALSE)) NEQ UF_OK)
582 {
583 TRACE_ERROR_P2("UF Driver: Can't disable UART, [%d], uart_kerp.c(%d)",
584 error_code,__LINE__);
585 }
586 #endif /* !FF_MULTI_PORT */
587 #endif /* _SIMULATION */
588 sig_ker_rx_dead_mode_req();
589 sig_ker_tx_dead_mode_req();
590 /*
591 * send confirm primitive
592 */
593 {
594 PALLOC (uart_disable_cnf, UART_DISABLE_CNF);
595 uart_disable_cnf->device = uart_data->device;
596 PSEND (hCommMMI, uart_disable_cnf);
597 }
598 }
599
600 /*
601 * UART_MUX_START_REQ
602 */
603 if(uart_data->ker.received_prim & UART_MUX_START_REQ_MASK)
604 {
605 switch( GET_STATE( UART_SERVICE_KER ) )
606 {
607 case KER_READY:
608 /*
609 * close dlc channel
610 */
611 ker_mux_dlc_release(UART_CONTROL_INSTANCE);
612 break;
613
614 default:
615 TRACE_ERROR( "SIG_TX_KER_FLUSHED_IND unexpected" );
616 break;
617 }
618
619 SET_STATE( UART_SERVICE_KER, KER_MUX_ESTABLISH );
620
621 /*
622 * set RX and TX service in mux mode
623 */
624 sig_ker_rx_mux_mode_req();
625 sig_ker_tx_mux_mode_req();
626 /*
627 * start reception
628 */
629 MALLOC(uart_data->ker.rx_data_desc, (USHORT)(sizeof(T_desc2) -
630 1 +
631 uart_data->n1 +
632 2));
633 uart_data->ker.rx_data_desc->next = (ULONG)NULL;
634 uart_data->ker.rx_data_desc->len = 0;
635 sig_ker_rx_ready_to_receive_req(uart_data->ker.rx_data_desc,
636 0,
637 (USHORT)(uart_data->n1 + 2));
638 /*
639 * start timer
640 */
641 sig_ker_rt_start_t3_req();
642
643 /*
644 * send confirm primitive
645 */
646 {
647 PALLOC (uart_mux_start_cnf, UART_MUX_START_CNF);
648 uart_mux_start_cnf->device = uart_data->device;
649 PSEND (hCommMMI, uart_mux_start_cnf);
650 }
651 }
652
653 /*
654 * UART_MUX_CLOSE_REQ
655 */
656 if(uart_data->ker.received_prim & UART_MUX_CLOSE_REQ_MASK)
657 {
658 switch( GET_STATE( UART_SERVICE_KER ) )
659 {
660 case KER_MUX_CLOSED:
661 if(uart_data->ker.receiving_state NEQ UART_KER_RECEIVING)
662 {
663 PALLOC(uart_mux_close_ind, UART_MUX_CLOSE_IND);
664 SET_STATE( UART_SERVICE_KER, KER_READY );
665 /*
666 * stop receiving
667 */
668 sig_ker_rx_not_ready_to_receive_req();
669 MFREE_DESC2(uart_data->ker.rx_data_desc);
670 uart_data->ker.rx_data_desc = NULL;
671 /*
672 * set dlc values
673 */
674 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE];
675 dlc->drx = &uart_data->drx_base[0];
676 dlc->dtx = &uart_data->dtx_base[0];
677 dlc->dlci = 0;
678 dlc->priority = 0;
679 /*
680 * set RX and TX in ready mode
681 */
682 sig_ker_rx_ready_mode_req();
683 sig_ker_tx_ready_mode_req();
684 /*
685 * set frame size for ready mode
686 */
687 uart_data->n1 = UART_N1_READY_MODE;
688 /*
689 * set DRX and DTX in ready mode
690 */
691 uart_data->dtx = dlc->dtx;
692 uart_data->drx = dlc->drx;
693 sig_ker_drx_ready_mode_req(UART_CONTROL_INSTANCE);
694 sig_ker_dtx_ready_mode_req(UART_CONTROL_INSTANCE);
695 /*
696 * inform ACI about entering ready mode
697 */
698 uart_mux_close_ind->device = uart_data->device;
699 PSEND(hCommMMI, uart_mux_close_ind);
700 }
701 break;
702
703 default:
704 TRACE_ERROR( "SIG_TX_KER_FLUSHED_IND unexpected" );
705 break;
706 }
707 }
708
709 /*
710 * no more UART port related primitives
711 * so clear all flags
712 */
713 uart_data->ker.received_prim = 0;
714
715 /*
716 * primitives of the DLC
717 */
718 for(i = 0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
719 {
720 dlc = &uart_data->dlc_table[i];
721 if(dlc->received_prim)
722 {
723 /*
724 * UART_RING_REQ
725 * UART_DCD_REQ
726 * DTI_DATA_REQ (line states)
727 */
728 if((dlc->received_prim & UART_RING_REQ_MASK) ||
729 (dlc->received_prim & UART_DCD_REQ_MASK) ||
730 (dlc->received_prim & UART_DTI_DATA_REQ_MASK))
731 {
732 /*
733 * send new line states
734 */
735 switch( GET_STATE( UART_SERVICE_KER ) )
736 {
737 case KER_READY:
738 sig_ker_tx_line_states_req(UART_CONTROL_INSTANCE);
739 break;
740
741 case KER_MUX:
742 /*
743 * send MSC frame to peer
744 */
745 ker_mux_send_line_states (uart_data->dlc_instance[dlc->dlci]);
746 break;
747
748 default:
749 if(dlc->received_prim & UART_RING_REQ_MASK)
750 {
751 TRACE_ERROR( "UART_RING_REQ unexpected" );
752 }
753 if(dlc->received_prim & UART_DCD_REQ_MASK)
754 {
755 TRACE_ERROR( "UART_DCD_REQ unexpected" );
756 }
757 break;
758 }
759 /*
760 * send confirm primitives
761 */
762 if(dlc->received_prim & UART_RING_REQ_MASK)
763 {
764 PALLOC (uart_ring_cnf, UART_RING_CNF);
765 uart_ring_cnf->device = uart_data->device;
766 uart_ring_cnf->dlci = dlc->dlci;
767 PSEND (hCommMMI, uart_ring_cnf);
768 }
769 if(dlc->received_prim & UART_DCD_REQ_MASK)
770 {
771 PALLOC (uart_dcd_cnf, UART_DCD_CNF);
772 uart_dcd_cnf->device = uart_data->device;
773 uart_dcd_cnf->dlci = dlc->dlci;
774 PSEND (hCommMMI, uart_dcd_cnf);
775 }
776 }
777 /*
778 * no more DLC related primitives
779 * so clear all flags
780 */
781 dlc->received_prim = 0;
782 }
783 }
784 uart_data->ker.flush_state = UART_KER_NOT_FLUSHING;
785 }
786 } /* sig_tx_ker_flushed_ind() */
787
788
789
790 /*
791 +------------------------------------------------------------------------------
792 | Function : sig_tx_ker_sending_ind
793 +------------------------------------------------------------------------------
794 | Description : Handles the internal signal SIG_TX_KER_SENDING_IND
795 |
796 | Parameters : no parameters
797 |
798 +------------------------------------------------------------------------------
799 */
800 GLOBAL void sig_tx_ker_sending_ind ()
801 {
802 TRACE_ISIG( "sig_tx_ker_sending_ind" );
803
804 switch( GET_STATE( UART_SERVICE_KER ) )
805 {
806 case KER_MUX_ESTABLISH:
807 case KER_MUX:
808 case KER_MUX_DLC_CLOSING:
809 case KER_MUX_CLOSING:
810 case KER_MUX_CLOSED:
811 uart_data->ker.sending_state = UART_KER_SENDING;
812 break;
813
814 default:
815 TRACE_ERROR( "SIG_TX_KER_SENDING_IND unexpected" );
816 break;
817 }
818 } /* sig_tx_ker_sending_ind() */
819
820
821
822 /*
823 +------------------------------------------------------------------------------
824 | Function : sig_tx_ker_data_sent_ind
825 +------------------------------------------------------------------------------
826 | Description : Handles the internal signal SIG_TX_KER_DATA_SENT_IND
827 |
828 | Parameters : rest_data - not yet sent data
829 | write_pos - position where the not yet sent data starts
830 |
831 +------------------------------------------------------------------------------
832 */
833 GLOBAL void sig_tx_ker_data_sent_ind (T_desc2* rest_data, USHORT read_pos)
834 {
835 TRACE_ISIG( "sig_tx_ker_data_sent_ind" );
836
837 /*
838 * free sent data descriptor
839 */
840 MFREE_DESC2(uart_data->ker.tx_data_desc);
841 uart_data->ker.tx_data_desc = NULL;
842 uart_data->ker.sending_state = UART_KER_NOT_SENDING;
843 if(uart_data->ker.tx_data_waiting)
844 {
845 /*
846 * send next descriptor in waiting queue
847 */
848 uart_data->ker.tx_data_desc = uart_data->ker.tx_data_waiting;
849 uart_data->ker.tx_data_waiting =
850 (T_desc2*)uart_data->ker.tx_data_waiting->next;
851 /*
852 * only one descriptor is sent at a time
853 */
854 uart_data->ker.tx_data_desc->next = (ULONG)NULL;
855 sig_ker_tx_data_available_req( uart_data->ker.tx_data_desc, 0);
856 }
857 else
858 {
859 switch( GET_STATE( UART_SERVICE_KER ) )
860 {
861 case KER_MUX_ESTABLISH:
862 case KER_MUX:
863 case KER_MUX_DLC_CLOSING:
864 case KER_MUX_CLOSING:
865 break;
866
867 case KER_MUX_CLOSED:
868 /*
869 * flush UART before enter ready mode
870 */
871 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
872
873 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
874 {
875 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
876 sig_ker_tx_flush_req();
877 }
878 break;
879
880 default:
881 TRACE_ERROR( "SIG_TX_KER_DATA_SENT_IND unexpected" );
882 break;
883 }
884 }
885 } /* sig_tx_ker_data_sent_ind() */
886
887
888
889 /*
890 +------------------------------------------------------------------------------
891 | Function : sig_rx_ker_receiving_ind
892 +------------------------------------------------------------------------------
893 | Description : Handles the internal signal SIG_RX_KER_RECEIVING_IND
894 |
895 | Parameters : no parameters
896 |
897 +------------------------------------------------------------------------------
898 */
899 GLOBAL void sig_rx_ker_receiving_ind ()
900 {
901 TRACE_ISIG( "sig_rx_ker_receiving_ind" );
902
903 switch( GET_STATE( UART_SERVICE_KER ) )
904 {
905 case KER_MUX_ESTABLISH:
906 case KER_MUX:
907 case KER_MUX_DLC_CLOSING:
908 case KER_MUX_CLOSING:
909 case KER_MUX_CLOSED:
910 uart_data->ker.receiving_state = UART_KER_RECEIVING;
911 break;
912 default:
913 TRACE_ERROR( "SIG_RX_KER_RECEIVING_IND unexpected" );
914 break;
915 }
916 } /* sig_rx_ker_receiving_ind() */
917
918
919
920 /*
921 +------------------------------------------------------------------------------
922 | Function : sig_rx_ker_data_received_ind
923 +------------------------------------------------------------------------------
924 | Description : Handles the internal signal SIG_RX_KER_DATA_RECEIVED_IND
925 | which is used to process a received frame.
926 |
927 | Precondition is that the frame has a length >2 without flags.
928 |
929 | Parameters : received_data - received data
930 | write_pos - write position for the next reception
931 |
932 +------------------------------------------------------------------------------
933 */
934 GLOBAL void sig_rx_ker_data_received_ind (T_desc2* received_data,
935 USHORT write_pos)
936 {
937 UBYTE i;
938 UBYTE dlci;
939 T_DLC* dlc;
940 ULONG forward;
941 BOOL continuous;
942
943 TRACE_ISIG( "sig_rx_ker_data_received_ind" );
944
945 #ifndef _TARGET_
946 if(received_data->len)
947 {
948 USHORT pos;
949 char buf[90];
950 /*
951 * trace output
952 */
953 TRACE_EVENT("======= IN");
954 i = 0;
955 pos = 0;
956 while(pos < received_data->len)
957 {
958 i+= sprintf(&buf[i], "0x%02x, ", received_data->buffer[pos]);
959 pos++;
960 if(i > 80)
961 {
962 TRACE_EVENT( buf );
963 i = 0;
964 }
965 else if(pos >= received_data->len)
966 {
967 TRACE_EVENT( buf );
968 }
969 }
970 }
971 #endif /* !_TARGET_ */
972
973 uart_data->ker.receiving_state = UART_KER_NOT_RECEIVING;
974
975 switch( GET_STATE( UART_SERVICE_KER ) )
976 {
977 case KER_MUX_ESTABLISH:
978 if(received_data->len EQ 0)
979 {
980 /*
981 * prepare next reception
982 */
983 sig_ker_rx_ready_to_receive_req(received_data,
984 write_pos,
985 (USHORT)(uart_data->n1 + 2));
986 break;
987 }
988 dlci = received_data->buffer[UART_OFFSET_ADDRESS] >> UART_DLCI_POS;
989 if((dlci EQ UART_DLCI_CONTROL) &&
990 (received_data->buffer[UART_OFFSET_CONTROL] EQ UART_SABM_FRAME))
991 {
992 /*
993 * analyze SABM frame
994 */
995 forward = 0;
996 ker_receive_sabm_frame(&forward, received_data);
997 /*
998 * set dlc value
999 */
1000 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE];
1001 if((forward & UART_FORWARD_SABM) &&
1002 (dlc->connection_state EQ UART_CONNECTION_SABM_RCVD) &&
1003 (uart_data->dlc_instance[dlci] NEQ UART_CONTROL_INSTANCE))
1004 {
1005 SET_STATE( UART_SERVICE_KER, KER_MUX );
1006 /*
1007 * stop timer
1008 */
1009 sig_ker_rt_stop_t3_req();
1010 /*
1011 * setup dlc parameter
1012 */
1013 uart_data->dlc_instance[dlci] = UART_CONTROL_INSTANCE;
1014 dlc->connection_state = UART_CONNECTION_OPEN;
1015 /*
1016 * set priority
1017 */
1018 dlc->priority = 0;
1019 /*
1020 * send response frame
1021 */
1022 if(forward & UART_FORWARD_RESPONSE)
1023 {
1024 ker_mux_send_frame(received_data);
1025 /*
1026 * prepare next reception
1027 */
1028 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1029 + uart_data->n1
1030 + 2));
1031 received_data->next = (ULONG)NULL;
1032 }
1033 }
1034 }
1035 /*
1036 * prepare next reception
1037 */
1038 received_data->len = 0;
1039 uart_data->ker.rx_data_desc = received_data;
1040 sig_ker_rx_ready_to_receive_req(received_data,
1041 0,
1042 (USHORT)(uart_data->n1 + 2));
1043 break;
1044
1045 case KER_MUX:
1046 if(received_data->len EQ 0)
1047 {
1048 /*
1049 * prepare next reception
1050 */
1051 sig_ker_rx_ready_to_receive_req(received_data,
1052 write_pos,
1053 (USHORT)(uart_data->n1 + 2));
1054 break;
1055 }
1056 /*
1057 * analyze frame and messages
1058 */
1059 forward = 0;
1060 switch(received_data->buffer[UART_OFFSET_CONTROL])
1061 {
1062 case UART_SABM_FRAME:
1063 ker_receive_sabm_frame(&forward, received_data);
1064 break;
1065
1066 case UART_UA_FRAME:
1067 ker_receive_ua_frame(&forward, received_data);
1068 break;
1069
1070 case UART_DM_CONTROL_FRAME:
1071 case UART_DM_DATA_FRAME:
1072 ker_receive_dm_frame(&forward, received_data);
1073 break;
1074
1075 case UART_DISC_FRAME:
1076 ker_receive_disc_frame(&forward, received_data);
1077 break;
1078
1079 case UART_UIH_CONTROL_FRAME:
1080 ker_receive_uih_control_frame(&forward, received_data);
1081 break;
1082
1083 case UART_UIH_DATA_FRAME:
1084 ker_receive_uih_data_frame(&forward, received_data);
1085 break;
1086
1087 default:
1088 {
1089 TRACE_EVENT_P2("Warning: Unexpected HDLC value: %d, uart_kers.c(%d)",
1090 received_data->buffer[UART_OFFSET_CONTROL], __LINE__);
1091 break;
1092 }
1093 }
1094 /*
1095 * remove resonded frames and send next frames in command queue
1096 */
1097 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1098 {
1099 dlc = &uart_data->dlc_table[i];
1100 switch(dlc->connection_state)
1101 {
1102 case UART_CONNECTION_OPEN:
1103 case UART_CONNECTION_DISC_SENT:
1104 if((dlc->last_command NEQ NULL) &&
1105 (dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1106 UART_UIH_CONTROL_FRAME) &&
1107 (dlc->last_command->len EQ UART_OFFSET_INFO))
1108 {
1109 /*
1110 * remove responded UIH frame
1111 */
1112 MFREE_DESC2(dlc->last_command);
1113 dlc->last_command = NULL;
1114 uart_data->ker.nr_t2--;
1115 if( uart_data->ker.nr_t2 EQ 0 )
1116 sig_ker_rt_stop_t2_req();
1117 }
1118 if((dlc->last_command EQ NULL) &&
1119 (dlc->next_command NEQ NULL))
1120 {
1121 T_desc2* temp_desc;
1122 /*
1123 * transmit next command frame
1124 */
1125 dlc->last_command = dlc->next_command;
1126 dlc->next_command = (T_desc2*)dlc->next_command->next;
1127 dlc->last_command->next = (ULONG)NULL;
1128
1129 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 +
1130 dlc->last_command->len));
1131 temp_desc->next = (ULONG)NULL;
1132 temp_desc->len = dlc->last_command->len;
1133 memcpy(temp_desc->buffer,
1134 dlc->last_command->buffer,
1135 dlc->last_command->len);
1136
1137 dlc->retransmissions = 0;
1138 ker_mux_send_frame(temp_desc);
1139
1140 if(dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1141 UART_UIH_CONTROL_FRAME)
1142 {
1143 uart_data->ker.nr_t2++;
1144 sig_ker_rt_start_t2_req();
1145 }
1146 else
1147 {
1148 uart_data->ker.nr_t1++;
1149 sig_ker_rt_start_t1_req();
1150 }
1151 }
1152 break;
1153
1154 case UART_CONNECTION_DEAD:
1155 break;
1156
1157 default:
1158 {
1159 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
1160 dlc->connection_state, __LINE__);
1161 break;
1162 }
1163 }
1164 }
1165 /*
1166 * process results of analysis
1167 */
1168 if(forward)
1169 {
1170 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1171 {
1172 if(i NEQ UART_CONTROL_INSTANCE)
1173 {
1174 /*
1175 * set dlc values
1176 */
1177 dlc = &uart_data->dlc_table[i];
1178 dlci = dlc->dlci;
1179 /*
1180 * channel to open
1181 */
1182 if((forward & UART_FORWARD_SABM) &&
1183 (dlc->connection_state EQ UART_CONNECTION_SABM_RCVD) &&
1184 (uart_data->dlc_instance[dlci] NEQ i))
1185 {
1186 PALLOC(uart_mux_dlc_establish_ind, UART_MUX_DLC_ESTABLISH_IND);
1187 /*
1188 * setup dlc parameter
1189 */
1190 uart_data->dlc_instance[dlci] = i;
1191 dlc->drx = &uart_data->drx_base[i];
1192 dlc->dtx = &uart_data->dtx_base[i];
1193 /*
1194 * set priority
1195 */
1196 if(dlci < 8)
1197 dlc->priority = 7;
1198 else if(dlci < 16)
1199 dlc->priority = 15;
1200 else if(dlci < 24)
1201 dlc->priority = 23;
1202 else if(dlci < 32)
1203 dlc->priority = 31;
1204 else if(dlci < 40)
1205 dlc->priority = 39;
1206 else if(dlci < 48)
1207 dlc->priority = 47;
1208 else if(dlci < 56)
1209 dlc->priority = 55;
1210 else
1211 dlc->priority = 61;
1212 /*
1213 * store response frame and
1214 * clear appropriate bit in forward mask
1215 */
1216 dlc->next_command = received_data;
1217 forward &= ~UART_FORWARD_RESPONSE;
1218 /*
1219 * create new reception frame
1220 */
1221 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1222 + uart_data->n1
1223 + 2));
1224 received_data->next = (ULONG)NULL;
1225 /*
1226 * inform ACI about new DLC
1227 */
1228 uart_mux_dlc_establish_ind->device = uart_data->device;
1229 uart_mux_dlc_establish_ind->dlci = dlci;
1230 uart_mux_dlc_establish_ind->
1231 convergence = UART_MUX_CONVERGENCE_UOS;
1232 uart_mux_dlc_establish_ind->n1 = uart_data->n1;
1233 uart_mux_dlc_establish_ind->
1234 service = UART_MUX_SERVICE_AT;
1235 PSEND (hCommMMI, uart_mux_dlc_establish_ind);
1236 }
1237 /*
1238 * channel to close
1239 */
1240 if((forward & UART_FORWARD_DLC_RELEASE) &&
1241 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
1242 (dlci NEQ UART_DLCI_INVALID))
1243 {
1244 PALLOC(uart_mux_dlc_release_ind, UART_MUX_DLC_RELEASE_IND);
1245 /*
1246 * release channel
1247 */
1248 ker_mux_dlc_release(i);
1249 /*
1250 * inform ACI about DLC release
1251 */
1252 uart_mux_dlc_release_ind->device = uart_data->device;
1253 uart_mux_dlc_release_ind->dlci = dlci;
1254 PSEND(hCommMMI, uart_mux_dlc_release_ind);
1255 }
1256 /*
1257 * set Flow Control ON
1258 */
1259 if((forward & UART_FORWARD_FCON) &&
1260 (dlc->connection_state EQ UART_CONNECTION_OPEN) &&
1261 (!(dlc->lines & UART_FC_RX_MASK)))
1262 {
1263 uart_data->drx = dlc->drx;
1264 sig_ker_drx_enable_req();
1265 }
1266 /*
1267 * set Flow Control OFF
1268 */
1269 if((forward & UART_FORWARD_FCOFF) &&
1270 (dlc->connection_state EQ UART_CONNECTION_OPEN) &&
1271 (!(dlc->lines & UART_FC_RX_MASK)))
1272 {
1273 uart_data->drx = dlc->drx;
1274 sig_ker_drx_disable_req();
1275 }
1276 /*
1277 * send status lines
1278 */
1279 if((forward & UART_FORWARD_MSC) &&
1280 (dlc->connection_state EQ UART_CONNECTION_OPEN))
1281 {
1282 UBYTE st_flow;
1283 UBYTE st_line_sa;
1284 UBYTE st_break_len;
1285 /*
1286 * send primitive if DTR drop is detected
1287 */
1288 if(dlc->lines & UART_DTR_MASK)
1289 {
1290 PALLOC (uart_detected_ind, UART_DETECTED_IND);
1291 uart_detected_ind->device = uart_data->device;
1292 uart_detected_ind->dlci = dlc->dlci;
1293 uart_detected_ind->cause = UART_DETECT_DTR;
1294 PSEND (hCommMMI, uart_detected_ind);
1295 }
1296 /*
1297 * set line states
1298 */
1299 if(dlc->lines & UART_RTS_MASK)
1300 st_flow = DTI_FLOW_OFF;
1301 else
1302 st_flow = DTI_FLOW_ON;
1303 if(dlc->lines & UART_DTR_MASK)
1304 st_line_sa = DTI_SA_OFF;
1305 else
1306 st_line_sa = DTI_SA_ON;
1307 /*
1308 * set break
1309 */
1310 if(dlc->lines & UART_BRK_RX_MASK)
1311 st_break_len = (UBYTE)((dlc->lines & UART_BRKLEN_RX_MASK) >>
1312 UART_BRKLEN_RX_POS);
1313 else
1314 st_break_len = DTI_BREAK_OFF;
1315 /*
1316 * send flow control signals
1317 */
1318 if(uart_data->ker.data_flow_tx EQ UART_FLOW_ENABLED)
1319 {
1320 uart_data->drx = dlc->drx;
1321 if(dlc->lines & UART_FC_RX_MASK)
1322 sig_ker_drx_disable_req();
1323 else
1324 sig_ker_drx_enable_req();
1325 }
1326 /*
1327 * send line states
1328 */
1329 uart_data->dtx = dlc->dtx;
1330 sig_ker_dtx_line_states_req(st_flow,
1331 st_line_sa,
1332 DTI_SB_ON,
1333 st_break_len);
1334 }
1335 }
1336 }
1337 /*
1338 * send response frame
1339 */
1340 if(forward & UART_FORWARD_RESPONSE)
1341 {
1342 ker_mux_send_frame(received_data);
1343 uart_data->ker.rx_data_desc = NULL;
1344 }
1345 /*
1346 * Close-Down multiplexer
1347 */
1348 if(forward & UART_FORWARD_CLD)
1349 {
1350 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSED );
1351 /*
1352 * stop timers and
1353 * remove all DLC instances
1354 */
1355 ker_mux_close_down();
1356 /*
1357 * flush UART before change the state
1358 */
1359 if(uart_data->ker.tx_data_desc EQ NULL)
1360 {
1361 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
1362
1363 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
1364 {
1365 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
1366 sig_ker_tx_flush_req();
1367 }
1368 }
1369 }
1370 }
1371 /*
1372 * prepare next reception
1373 */
1374 if(forward & UART_FORWARD_RESPONSE)
1375 {
1376 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1377 + uart_data->n1
1378 + 2));
1379 received_data->next = (ULONG)NULL;
1380 }
1381 received_data->len = 0;
1382 uart_data->ker.rx_data_desc = received_data;
1383 sig_ker_rx_ready_to_receive_req(received_data,
1384 0,
1385 (USHORT)(uart_data->n1 + 2));
1386 break;
1387
1388 case KER_MUX_DLC_CLOSING:
1389 if(received_data->len EQ 0)
1390 {
1391 /*
1392 * prepare next reception
1393 */
1394 sig_ker_rx_ready_to_receive_req(received_data,
1395 write_pos,
1396 (USHORT)(uart_data->n1 + 2));
1397 break;
1398 }
1399 /*
1400 * analyze frame and messages
1401 */
1402 forward = 0;
1403 switch(received_data->buffer[UART_OFFSET_CONTROL])
1404 {
1405 case UART_SABM_FRAME:
1406 ker_receive_sabm_frame(&forward, received_data);
1407 break;
1408
1409 case UART_UA_FRAME:
1410 ker_receive_ua_frame(&forward, received_data);
1411 break;
1412
1413 case UART_DM_CONTROL_FRAME:
1414 case UART_DM_DATA_FRAME:
1415 ker_receive_dm_frame(&forward, received_data);
1416 break;
1417
1418 case UART_DISC_FRAME:
1419 ker_receive_disc_frame(&forward, received_data);
1420 break;
1421
1422 case UART_UIH_CONTROL_FRAME:
1423 ker_receive_uih_control_frame(&forward, received_data);
1424 break;
1425
1426 case UART_UIH_DATA_FRAME:
1427 ker_receive_uih_data_frame(&forward, received_data);
1428 break;
1429
1430 default:
1431 {
1432 TRACE_EVENT_P2("Warning: Unexpected HDLC value: %d, uart_kers.c(%d)",
1433 received_data->buffer[UART_OFFSET_CONTROL], __LINE__);
1434 break;
1435 }
1436 }
1437 /*
1438 * remove resonded frames and send next frames in command queue
1439 */
1440 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1441 {
1442 dlc = &uart_data->dlc_table[i];
1443 switch(dlc->connection_state)
1444 {
1445 case UART_CONNECTION_OPEN:
1446 case UART_CONNECTION_DISC_SENT:
1447 if((dlc->last_command NEQ NULL) &&
1448 (dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1449 UART_UIH_CONTROL_FRAME) &&
1450 (dlc->last_command->len EQ UART_OFFSET_INFO))
1451 {
1452 /*
1453 * remove responded UIH frame
1454 */
1455 MFREE_DESC2(dlc->last_command);
1456 dlc->last_command = NULL;
1457 uart_data->ker.nr_t2--;
1458 if( uart_data->ker.nr_t2 EQ 0 )
1459 sig_ker_rt_stop_t2_req();
1460 }
1461 if((dlc->last_command EQ NULL) &&
1462 (dlc->next_command NEQ NULL))
1463 {
1464 T_desc2* temp_desc;
1465 /*
1466 * transmit next command frame
1467 */
1468 dlc->last_command = dlc->next_command;
1469 dlc->next_command = (T_desc2*)dlc->next_command->next;
1470 dlc->last_command->next = (ULONG)NULL;
1471
1472 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 +
1473 dlc->last_command->len));
1474 temp_desc->next = (ULONG)NULL;
1475 temp_desc->len = dlc->last_command->len;
1476 memcpy(temp_desc->buffer,
1477 dlc->last_command->buffer,
1478 dlc->last_command->len);
1479
1480 dlc->retransmissions = 0;
1481 ker_mux_send_frame(temp_desc);
1482
1483 if(dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1484 UART_UIH_CONTROL_FRAME)
1485 {
1486 uart_data->ker.nr_t2++;
1487 sig_ker_rt_start_t2_req();
1488 }
1489 else
1490 {
1491 uart_data->ker.nr_t1++;
1492 sig_ker_rt_start_t1_req();
1493 }
1494 }
1495 break;
1496
1497 case UART_CONNECTION_DEAD:
1498 break;
1499
1500 default:
1501 {
1502 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
1503 dlc->connection_state, __LINE__);
1504 break;
1505 }
1506 }
1507 }
1508 /*
1509 * process results of analysis
1510 */
1511 if(forward)
1512 {
1513 continuous = FALSE;
1514 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1515 {
1516 if(i NEQ UART_CONTROL_INSTANCE)
1517 {
1518 /*
1519 * set dlc values
1520 */
1521 dlc = &uart_data->dlc_table[i];
1522 dlci = dlc->dlci;
1523 /*
1524 * channel to open
1525 */
1526 if((forward & UART_FORWARD_SABM) &&
1527 (dlc->connection_state EQ UART_CONNECTION_SABM_RCVD))
1528 {
1529 /*
1530 * reject all attempts to open a channel
1531 */
1532 received_data->buffer[UART_OFFSET_CONTROL] =
1533 UART_DM_CONTROL_FRAME;
1534 /*
1535 * release channel
1536 */
1537 ker_mux_dlc_release(i);
1538 }
1539 /*
1540 * channel to close
1541 */
1542 if((forward & UART_FORWARD_DLC_RELEASE) &&
1543 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
1544 (dlci NEQ UART_DLCI_INVALID))
1545 {
1546 /*
1547 * release channel
1548 */
1549 ker_mux_dlc_release(i);
1550 }
1551 if(dlc->connection_state NEQ UART_CONNECTION_DEAD)
1552 continuous = TRUE;
1553 }
1554 }
1555 /*
1556 * send response frame
1557 */
1558 if(forward & UART_FORWARD_RESPONSE)
1559 {
1560 ker_mux_send_frame(received_data);
1561 uart_data->ker.rx_data_desc = NULL;
1562 }
1563 /*
1564 * Close-Down multiplexer
1565 */
1566 if(forward & UART_FORWARD_CLD)
1567 {
1568 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSED );
1569 /*
1570 * stop timers and
1571 * remove all DLC instances
1572 */
1573 ker_mux_close_down();
1574 /*
1575 * flush UART before change the state
1576 */
1577 if(uart_data->ker.tx_data_desc EQ NULL)
1578 {
1579 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
1580
1581 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
1582 {
1583 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
1584 sig_ker_tx_flush_req();
1585 }
1586 }
1587 }
1588 /*
1589 * change state if all channels are closed
1590 */
1591 else if(continuous EQ FALSE)
1592 {
1593 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSING );
1594 /*
1595 * build and send CLD command frame:
1596 */
1597 ker_mux_send_close_down();
1598 /*
1599 * start timer
1600 */
1601 sig_ker_rt_start_t3_req();
1602 }
1603 }
1604 /*
1605 * prepare next reception
1606 */
1607 if(forward & UART_FORWARD_RESPONSE)
1608 {
1609 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1610 + uart_data->n1
1611 + 2));
1612 received_data->next = (ULONG)NULL;
1613 }
1614 received_data->len = 0;
1615 uart_data->ker.rx_data_desc = received_data;
1616 sig_ker_rx_ready_to_receive_req(received_data,
1617 0,
1618 (USHORT)(uart_data->n1 + 2));
1619 break;
1620
1621 case KER_MUX_CLOSING:
1622 if(received_data->len EQ 0)
1623 {
1624 /*
1625 * prepare next reception
1626 */
1627 sig_ker_rx_ready_to_receive_req(received_data,
1628 write_pos,
1629 (USHORT)(uart_data->n1 + 2));
1630 break;
1631 }
1632 /*
1633 * analyze frame and messages
1634 */
1635 forward = 0;
1636 switch(received_data->buffer[UART_OFFSET_CONTROL])
1637 {
1638 case UART_SABM_FRAME:
1639 ker_receive_sabm_frame(&forward, received_data);
1640 break;
1641
1642 case UART_UA_FRAME:
1643 ker_receive_ua_frame(&forward, received_data);
1644 break;
1645
1646 case UART_DM_CONTROL_FRAME:
1647 case UART_DM_DATA_FRAME:
1648 ker_receive_dm_frame(&forward, received_data);
1649 break;
1650
1651 case UART_DISC_FRAME:
1652 ker_receive_disc_frame(&forward, received_data);
1653 break;
1654
1655 case UART_UIH_CONTROL_FRAME:
1656 ker_receive_uih_control_frame(&forward, received_data);
1657 break;
1658
1659 case UART_UIH_DATA_FRAME:
1660 ker_receive_uih_data_frame(&forward, received_data);
1661 break;
1662
1663 default:
1664 {
1665 TRACE_EVENT_P2("Warning: Unexpected HDLC value: %d, uart_kers.c(%d)",
1666 received_data->buffer[UART_OFFSET_CONTROL], __LINE__);
1667 break;
1668 }
1669 }
1670 /*
1671 * remove resonded frames and send next frames in command queue
1672 */
1673 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1674 {
1675 dlc = &uart_data->dlc_table[i];
1676 switch(dlc->connection_state)
1677 {
1678 case UART_CONNECTION_OPEN:
1679 case UART_CONNECTION_DISC_SENT:
1680 if((dlc->last_command NEQ NULL) &&
1681 (dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1682 UART_UIH_CONTROL_FRAME) &&
1683 (dlc->last_command->len EQ UART_OFFSET_INFO))
1684 {
1685 /*
1686 * remove responded UIH frame
1687 */
1688 MFREE_DESC2(dlc->last_command);
1689 dlc->last_command = NULL;
1690 uart_data->ker.nr_t2--;
1691 if( uart_data->ker.nr_t2 EQ 0 )
1692 sig_ker_rt_stop_t2_req();
1693 }
1694 if((dlc->last_command EQ NULL) &&
1695 (dlc->next_command NEQ NULL))
1696 {
1697 T_desc2* temp_desc;
1698 /*
1699 * transmit next command frame
1700 */
1701 dlc->last_command = dlc->next_command;
1702 dlc->next_command = (T_desc2*)dlc->next_command->next;
1703 dlc->last_command->next = (ULONG)NULL;
1704
1705 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 +
1706 dlc->last_command->len));
1707 temp_desc->next = (ULONG)NULL;
1708 temp_desc->len = dlc->last_command->len;
1709 memcpy(temp_desc->buffer,
1710 dlc->last_command->buffer,
1711 dlc->last_command->len);
1712
1713 dlc->retransmissions = 0;
1714 ker_mux_send_frame(temp_desc);
1715
1716 if(dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1717 UART_UIH_CONTROL_FRAME)
1718 {
1719 uart_data->ker.nr_t2++;
1720 sig_ker_rt_start_t2_req();
1721 }
1722 else
1723 {
1724 uart_data->ker.nr_t1++;
1725 sig_ker_rt_start_t1_req();
1726 }
1727 }
1728 break;
1729
1730 case UART_CONNECTION_DEAD:
1731 break;
1732
1733 default:
1734 {
1735 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
1736 dlc->connection_state,__LINE__);
1737 break;
1738 }
1739 }
1740 }
1741 /*
1742 * process results of analysis
1743 */
1744 if(forward)
1745 {
1746 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1747 {
1748 if(i NEQ UART_CONTROL_INSTANCE)
1749 {
1750 /*
1751 * set dlc values
1752 */
1753 dlc = &uart_data->dlc_table[i];
1754 dlci = dlc->dlci;
1755 /*
1756 * channel to open
1757 */
1758 if((forward & UART_FORWARD_SABM) &&
1759 (dlc->connection_state EQ UART_CONNECTION_SABM_RCVD))
1760 {
1761 /*
1762 * reject all attempts to open a channel
1763 */
1764 received_data->buffer[UART_OFFSET_CONTROL] =
1765 UART_DM_CONTROL_FRAME;
1766 /*
1767 * release channel
1768 */
1769 ker_mux_dlc_release(i);
1770 }
1771 /*
1772 * channel to close
1773 */
1774 if((forward & UART_FORWARD_DLC_RELEASE) &&
1775 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
1776 (dlci NEQ UART_DLCI_INVALID))
1777 {
1778 /*
1779 * release channel
1780 */
1781 ker_mux_dlc_release(i);
1782 }
1783 }
1784 }
1785 /*
1786 * send response frame
1787 */
1788 if(forward & UART_FORWARD_RESPONSE)
1789 {
1790 ker_mux_send_frame(received_data);
1791 uart_data->ker.rx_data_desc = NULL;
1792 }
1793 /*
1794 * Close-Down multiplexer
1795 */
1796 if(forward & UART_FORWARD_CLD)
1797 {
1798 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSED );
1799 /*
1800 * stop timers and
1801 * remove all DLC instances
1802 */
1803 ker_mux_close_down();
1804 /*
1805 * flush UART before change the state
1806 */
1807 if(uart_data->ker.tx_data_desc EQ NULL)
1808 {
1809 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
1810
1811 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
1812 {
1813 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
1814 sig_ker_tx_flush_req();
1815 }
1816 }
1817 }
1818 }
1819 /*
1820 * prepare next reception
1821 */
1822 if(forward & UART_FORWARD_RESPONSE)
1823 {
1824 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1825 + uart_data->n1
1826 + 2));
1827 received_data->next = (ULONG)NULL;
1828 }
1829 received_data->len = 0;
1830 uart_data->ker.rx_data_desc = received_data;
1831 sig_ker_rx_ready_to_receive_req(received_data,
1832 0,
1833 (USHORT)(uart_data->n1 + 2));
1834 break;
1835
1836 case KER_MUX_CLOSED:
1837 if((uart_data->ker.tx_data_desc EQ NULL) &&
1838 (uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING))
1839 {
1840 PALLOC(uart_mux_close_ind, UART_MUX_CLOSE_IND);
1841 SET_STATE( UART_SERVICE_KER, KER_READY );
1842 /*
1843 * free receiving buffer
1844 */
1845 MFREE_DESC2(uart_data->ker.rx_data_desc);
1846 uart_data->ker.rx_data_desc = NULL;
1847 /*
1848 * set dlc values
1849 */
1850 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE];
1851 dlc->drx = &uart_data->drx_base[0];
1852 dlc->dtx = &uart_data->dtx_base[0];
1853 dlc->dlci = 0;
1854 dlc->priority = 0;
1855 /*
1856 * set RX and TX in ready mode
1857 */
1858 sig_ker_rx_ready_mode_req();
1859 sig_ker_tx_ready_mode_req();
1860 /*
1861 * set frame size for ready mode
1862 */
1863 uart_data->n1 = UART_N1_READY_MODE;
1864 /*
1865 * set DRX and DTX in ready mode
1866 */
1867 uart_data->dtx = dlc->dtx;
1868 uart_data->drx = dlc->drx;
1869 sig_ker_drx_ready_mode_req(UART_CONTROL_INSTANCE);
1870 sig_ker_dtx_ready_mode_req(UART_CONTROL_INSTANCE);
1871 /*
1872 * inform ACI about entering ready mode
1873 */
1874 uart_mux_close_ind->device = uart_data->device;
1875 PSEND(hCommMMI, uart_mux_close_ind);
1876 }
1877 else if(received_data->len EQ 0)
1878 {
1879 /*
1880 * prepare next reception
1881 */
1882 sig_ker_rx_ready_to_receive_req(received_data,
1883 write_pos,
1884 (USHORT)(uart_data->n1 + 2));
1885 }
1886 else
1887 {
1888 /*
1889 * prepare next reception
1890 */
1891 received_data->len = 0;
1892 sig_ker_rx_ready_to_receive_req(received_data,
1893 0,
1894 (USHORT)(uart_data->n1 + 2));
1895 }
1896 break;
1897
1898 default:
1899 TRACE_ERROR( "SIG_RX_KER_DATA_RECEIVED_IND unexpected" );
1900 break;
1901 }
1902 } /* sig_rx_ker_data_received_ind() */
1903
1904
1905
1906 /*
1907 +------------------------------------------------------------------------------
1908 | Function : sig_rx_ker_line_states_ind
1909 +------------------------------------------------------------------------------
1910 | Description : Handles the internal signal SIG_RX_KER_LINE_STATES_IND
1911 |
1912 | Parameters : line_states - new line states
1913 |
1914 +------------------------------------------------------------------------------
1915 */
1916 GLOBAL void sig_rx_ker_line_states_ind (ULONG line_states)
1917 {
1918 T_DLC* dlc;
1919 UBYTE st_flow;
1920 UBYTE st_line_sa;
1921 UBYTE st_line_sb;
1922 UBYTE st_break_len;
1923
1924 TRACE_ISIG( "sig_rx_ker_line_states_ind" );
1925
1926 /*
1927 * set DLC
1928 */
1929 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE];
1930 /*
1931 * send primitive if escape sequence or DTR drop is detected
1932 */
1933 if(line_states & UART_ESC_RX_MASK)
1934 {
1935 PALLOC (uart_detected_ind, UART_DETECTED_IND);
1936 uart_detected_ind->device = uart_data->device;
1937 uart_detected_ind->dlci = dlc->dlci;
1938 uart_detected_ind->cause = UART_DETECT_ESC;
1939 PSEND (hCommMMI, uart_detected_ind);
1940 }
1941 if((line_states & UART_DTR_MASK) AND
1942 (!(dlc->lines & UART_DTR_MASK)))
1943 {
1944 PALLOC (uart_detected_ind, UART_DETECTED_IND);
1945 uart_detected_ind->device = uart_data->device;
1946 uart_detected_ind->dlci = dlc->dlci;
1947 uart_detected_ind->cause = UART_DETECT_DTR;
1948 PSEND (hCommMMI, uart_detected_ind);
1949 }
1950
1951 switch( GET_STATE( UART_SERVICE_KER ) )
1952 {
1953 case KER_READY:
1954 /*
1955 * set line states
1956 */
1957 if(line_states & UART_X_RX_MASK)
1958 st_flow = DTI_FLOW_OFF;
1959 else
1960 st_flow = DTI_FLOW_ON;
1961
1962 if(line_states & UART_SA_RX_MASK)
1963 st_line_sa = DTI_SA_OFF;
1964 else
1965 st_line_sa = DTI_SA_ON;
1966
1967 if(line_states & UART_SB_RX_MASK)
1968 st_line_sb = DTI_SB_OFF;
1969 else
1970 st_line_sb = DTI_SB_ON;
1971
1972 if(line_states & UART_BRK_RX_MASK)
1973 st_break_len = (UBYTE)((line_states & UART_BRKLEN_RX_MASK)
1974 >> UART_BRKLEN_RX_POS);
1975 else
1976 st_break_len = DTI_BREAK_OFF;
1977
1978 uart_data->dtx = dlc->dtx;
1979 sig_ker_dtx_line_states_req(st_flow,
1980 st_line_sa,
1981 st_line_sb,
1982 st_break_len);
1983 break;
1984
1985 case KER_MUX_ESTABLISH:
1986 case KER_MUX:
1987 case KER_MUX_DLC_CLOSING:
1988 case KER_MUX_CLOSING:
1989 case KER_MUX_CLOSED:
1990 break;
1991
1992 default:
1993 TRACE_ERROR( "SIG_RX_KER_LINE_STATES_IND unexpected" );
1994 break;
1995 }
1996 /*
1997 * store new line states
1998 */
1999 dlc->lines &= ~(UART_X_RX_MASK |
2000 UART_SA_RX_MASK |
2001 UART_SB_RX_MASK |
2002 UART_ESC_RX_MASK |
2003 UART_BRK_RX_MASK |
2004 UART_BRKLEN_RX_MASK);
2005 line_states&= ~(UART_ESC_RX_MASK |
2006 UART_BRK_RX_MASK |
2007 UART_BRKLEN_RX_MASK);
2008 dlc->lines |= line_states;
2009 } /* sig_rx_ker_line_states_ind() */
2010
2011
2012
2013 /*
2014 +------------------------------------------------------------------------------
2015 | Function : sig_rt_ker_timeout_t1_ind
2016 +------------------------------------------------------------------------------
2017 | Description : Handles the internal signal SIG_RT_KER_TIMEOUT_T1_IND
2018 |
2019 | Parameters : no parameters
2020 |
2021 +------------------------------------------------------------------------------
2022 */
2023 GLOBAL void sig_rt_ker_timeout_t1_ind ()
2024 {
2025 UBYTE i;
2026 T_desc2* temp_desc;
2027 T_DLC* dlc;
2028 UBYTE j;
2029 UBYTE dlci;
2030 ULONG forward;
2031 BOOL continuous;
2032
2033 TRACE_ISIG( "sig_rt_ker_timeout_t1_ind" );
2034
2035 for( i = 0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++ )
2036 {
2037 /*
2038 * set dlc value
2039 */
2040 dlc = &uart_data->dlc_table[i];
2041 switch(dlc->connection_state)
2042 {
2043 case UART_CONNECTION_OPEN:
2044 case UART_CONNECTION_DISC_SENT:
2045 /*
2046 * T1 is used for non UIH Control frames
2047 */
2048 if((dlc->last_command NEQ NULL) &&
2049 (dlc->last_command->buffer[UART_OFFSET_CONTROL] NEQ
2050 UART_UIH_CONTROL_FRAME))
2051 {
2052 if(dlc->retransmissions < uart_data->ker.n2)
2053 {
2054 /*
2055 * retransmission of Control frame
2056 */
2057 dlc->retransmissions++;
2058 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1
2059 + dlc->last_command->len));
2060
2061 temp_desc->next = (ULONG)NULL;
2062 temp_desc->len = dlc->last_command->len;
2063 memcpy(temp_desc->buffer,
2064 dlc->last_command->buffer,
2065 dlc->last_command->len);
2066
2067 ker_mux_send_frame( temp_desc );
2068 }
2069 else
2070 {
2071 /*
2072 * maximum number of retransmissions reached
2073 */
2074 switch( GET_STATE( UART_SERVICE_KER ) )
2075 {
2076 case KER_MUX:
2077 /*
2078 * act as on reception of a DM frame
2079 */
2080 /*
2081 * create DM frame
2082 */
2083 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 + 2));
2084 temp_desc->next = (ULONG)NULL;
2085 temp_desc->len = 2;
2086 memcpy(temp_desc->buffer, dlc->last_command->buffer, 2)
2087 ;/*lint !e419 !e420 apparent data overrun and access beyond array*/
2088 temp_desc->buffer[UART_OFFSET_CONTROL] = UART_DM_CONTROL_FRAME;
2089 /*
2090 * act as on reception of a DM frame
2091 */
2092 forward = 0;
2093 ker_receive_dm_frame(&forward, temp_desc);
2094 /*
2095 * process results of analysis
2096 */
2097 if(forward)
2098 {
2099 for(j=0; j <= UART_MAX_NUMBER_OF_CHANNELS; j++)
2100 {
2101 if(j NEQ UART_CONTROL_INSTANCE)
2102 {
2103 /*
2104 * set dlc values
2105 */
2106 dlc = &uart_data->dlc_table[j];
2107 dlci = dlc->dlci;
2108 /*
2109 * channel to close
2110 */
2111 if((forward & UART_FORWARD_DLC_RELEASE) &&
2112 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
2113 (dlci NEQ UART_DLCI_INVALID))
2114 {
2115 PALLOC(uart_mux_dlc_release_ind,
2116 UART_MUX_DLC_RELEASE_IND);
2117 /*
2118 * release channel
2119 */
2120 ker_mux_dlc_release(j);
2121 /*
2122 * inform ACI about DLC release
2123 */
2124 uart_mux_dlc_release_ind->device = uart_data->device;
2125 uart_mux_dlc_release_ind->dlci = dlci;
2126 PSEND(hCommMMI, uart_mux_dlc_release_ind);
2127 }
2128 }
2129 }
2130 }
2131 break;
2132
2133 case KER_MUX_DLC_CLOSING:
2134 /*
2135 * act as on reception of a DM frame
2136 */
2137 /*
2138 * create DM frame
2139 */
2140 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 + 2));
2141 temp_desc->next = (ULONG)NULL;
2142 temp_desc->len = 2;
2143 memcpy(temp_desc->buffer, dlc->last_command->buffer, 2)
2144 ;/*lint !e419 !e420 apparent data overrun and access beyond array*/
2145 temp_desc->buffer[UART_OFFSET_CONTROL] = UART_DM_CONTROL_FRAME;
2146 /*
2147 * act as on reception of a DM frame
2148 */
2149 forward = 0;
2150 ker_receive_dm_frame(&forward, temp_desc);
2151 /*
2152 * process results of analysis
2153 */
2154 if(forward)
2155 {
2156 continuous = FALSE;
2157 for(j=0; j <= UART_MAX_NUMBER_OF_CHANNELS; j++)
2158 {
2159 if(j NEQ UART_CONTROL_INSTANCE)
2160 {
2161 /*
2162 * set dlc values
2163 */
2164 dlc = &uart_data->dlc_table[j];
2165 dlci = dlc->dlci;
2166 /*
2167 * channel to close
2168 */
2169 if((forward & UART_FORWARD_DLC_RELEASE) &&
2170 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
2171 (dlci NEQ UART_DLCI_INVALID))
2172 {
2173 /*
2174 * release channel
2175 */
2176 ker_mux_dlc_release(j);
2177 }
2178 if(dlc->connection_state NEQ UART_CONNECTION_DEAD)
2179 continuous = TRUE;
2180 }
2181 }
2182 /*
2183 * change state if all channels are closed
2184 */
2185 if(continuous EQ FALSE)
2186 {
2187 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSING );
2188 /*
2189 * build and send CLD command frame:
2190 */
2191 ker_mux_send_close_down();
2192 /*
2193 * start timer
2194 */
2195 sig_ker_rt_start_t3_req();
2196 }
2197 }
2198 break;
2199
2200 case KER_MUX_CLOSING:
2201 /*
2202 * do not care about retransmission couter
2203 * retransmission stops if T3 expires
2204 */
2205 dlc->retransmissions++;
2206 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1
2207 + dlc->last_command->len));
2208
2209 temp_desc->next = (ULONG)NULL;
2210 temp_desc->len = dlc->last_command->len;
2211 memcpy(temp_desc->buffer,
2212 dlc->last_command->buffer,
2213 dlc->last_command->len);
2214
2215 ker_mux_send_frame( temp_desc );
2216 break;
2217
2218 default:
2219 TRACE_ERROR( "SIG_RT_KER_TIMEOUT_T1_IND unexpected" );
2220 break;
2221 }
2222 }
2223 }
2224 break;
2225
2226 case UART_CONNECTION_DEAD:
2227 break;
2228
2229 default:
2230 {
2231 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
2232 dlc->connection_state, __LINE__);
2233 break;
2234 }
2235 }
2236 }
2237 if(uart_data->ker.nr_t1)
2238 {
2239 /*
2240 * restart timer t1
2241 */
2242 sig_ker_rt_start_t1_req();
2243 }
2244 } /* sig_rt_ker_timeout_t1_ind() */
2245
2246
2247
2248 /*
2249 +------------------------------------------------------------------------------
2250 | Function : sig_rt_ker_timeout_t2_ind
2251 +------------------------------------------------------------------------------
2252 | Description : Handles the internal signal SIG_RT_KER_TIMEOUT_T2_IND
2253 |
2254 | This signal means that no response to a sent command frame
2255 | was received within the allowed time. It is assumed that
2256 | the frame has been lost and a retransmission is done if the
2257 | maximum number of retransmissions is not reached yet.
2258 |
2259 | Parameters : no parameters
2260 |
2261 +------------------------------------------------------------------------------
2262 */
2263 GLOBAL void sig_rt_ker_timeout_t2_ind ()
2264 {
2265 UBYTE i;
2266 T_desc2* temp_desc;
2267 T_DLC* dlc;
2268
2269 TRACE_ISIG( "sig_rt_ker_timeout_t2_ind" );
2270
2271 for( i = 0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++ )
2272 {
2273 /*
2274 * set dlc value
2275 */
2276 dlc = &uart_data->dlc_table[i];
2277 switch(dlc->connection_state)
2278 {
2279 case UART_CONNECTION_OPEN:
2280 case UART_CONNECTION_DISC_SENT:
2281 /*
2282 * T2 is only used for UIH Control frames
2283 */
2284 if((dlc->last_command NEQ NULL) &&
2285 (dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
2286 UART_UIH_CONTROL_FRAME))
2287 {
2288 if(dlc->retransmissions < uart_data->ker.n2)
2289 {
2290 /*
2291 * retransmission of Control frame
2292 */
2293 dlc->retransmissions++;
2294 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1
2295 + dlc->last_command->len));
2296
2297 temp_desc->next = (ULONG)NULL;
2298 temp_desc->len = dlc->last_command->len;
2299 memcpy(temp_desc->buffer,
2300 dlc->last_command->buffer,
2301 dlc->last_command->len);
2302
2303 ker_mux_send_frame( temp_desc );
2304 }
2305 else
2306 {
2307 /*
2308 * maximum number of retransmissions reached
2309 */
2310 switch( GET_STATE( UART_SERVICE_KER ) )
2311 {
2312 case KER_MUX:
2313 case KER_MUX_DLC_CLOSING:
2314 /*
2315 * skip this frame and send next frame
2316 */
2317 /*
2318 * remove current UIH frame
2319 */
2320 MFREE_DESC2(dlc->last_command);
2321 dlc->last_command = NULL;
2322 uart_data->ker.nr_t2--;
2323 if(dlc->next_command)
2324 {
2325 /*
2326 * transmit next command frame
2327 */
2328 dlc->last_command = dlc->next_command;
2329 dlc->next_command = (T_desc2*)dlc->next_command->next;
2330 dlc->last_command->next = (ULONG)NULL;
2331
2332 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 +
2333 dlc->last_command->len));
2334 temp_desc->next = (ULONG)NULL;
2335 temp_desc->len = dlc->last_command->len;
2336 memcpy(temp_desc->buffer,
2337 dlc->last_command->buffer,
2338 dlc->last_command->len);
2339
2340 dlc->retransmissions = 0;
2341 ker_mux_send_frame(temp_desc);
2342 uart_data->ker.nr_t2++;
2343 }
2344 break;
2345
2346 case KER_MUX_CLOSING:
2347 /*
2348 * do not care about retransmission couter
2349 * retransmission stops if T3 expires
2350 */
2351 dlc->retransmissions++;
2352 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1
2353 + dlc->last_command->len));
2354
2355 temp_desc->next = (ULONG)NULL;
2356 temp_desc->len = dlc->last_command->len;
2357 memcpy(temp_desc->buffer,
2358 dlc->last_command->buffer,
2359 dlc->last_command->len);
2360
2361 ker_mux_send_frame( temp_desc );
2362 break;
2363
2364 default:
2365 TRACE_ERROR( "SIG_RT_KER_TIMEOUT_T2_IND unexpected" );
2366 break;
2367 }
2368 }
2369 }
2370 break;
2371
2372 case UART_CONNECTION_DEAD:
2373 break;
2374
2375 default:
2376 {
2377 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
2378 dlc->connection_state, __LINE__);
2379 break;
2380 }
2381 }
2382 }
2383 if(uart_data->ker.nr_t2)
2384 {
2385 /*
2386 * restart timer t2
2387 */
2388 sig_ker_rt_start_t2_req();
2389 }
2390 } /* sig_rt_ker_timeout_t2_ind() */
2391
2392
2393
2394 /*
2395 +------------------------------------------------------------------------------
2396 | Function : sig_rt_ker_timeout_t3_ind
2397 +------------------------------------------------------------------------------
2398 | Description : Handles the internal signal SIG_RT_KER_TIMEOUT_T3_IND
2399 |
2400 | Parameters : no parameters
2401 |
2402 +------------------------------------------------------------------------------
2403 */
2404 GLOBAL void sig_rt_ker_timeout_t3_ind ()
2405 {
2406 TRACE_ISIG( "sig_rt_ker_timeout_t3_ind" );
2407
2408 switch( GET_STATE( UART_SERVICE_KER ) )
2409 {
2410 case KER_MUX_ESTABLISH:
2411 case KER_MUX_CLOSING:
2412 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSED );
2413 /*
2414 * stop timers and
2415 * remove all DLC instances
2416 */
2417 ker_mux_close_down();
2418 if(uart_data->ker.tx_data_desc EQ NULL)
2419 {
2420 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
2421
2422 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
2423 {
2424 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
2425 sig_ker_tx_flush_req();
2426 }
2427 }
2428 break;
2429
2430 default:
2431 TRACE_ERROR( "SIG_RT_KER_TIMEOUT_T3_IND unexpected" );
2432 break;
2433 }
2434 } /* sig_rt_ker_timeout_t3_ind() */
2435
2436
2437 /*
2438 +------------------------------------------------------------------------------
2439 | Function : sig_rt_ker_timeout_tesd_ind
2440 +------------------------------------------------------------------------------
2441 | Description : Handles the internal signal SIG_RT_KER_TIMEOUT_TESD_IND
2442 |
2443 | This signal means that the trailing guard period has completed.
2444 |
2445 | Parameters : no parameters
2446 |
2447 +------------------------------------------------------------------------------
2448 */
2449 GLOBAL void sig_rt_ker_timeout_tesd_ind ()
2450 {
2451 UBYTE i;
2452
2453 TRACE_ISIG( "sig_rt_ker_timeout_tesd_ind" );
2454
2455 switch( GET_STATE( UART_SERVICE_KER ) )
2456 {
2457 case KER_READY:
2458 case KER_MUX:
2459 for( i = 0; i < UART_MAX_NUMBER_OF_CHANNELS; i++ )
2460 { /*
2461 * set current dtx
2462 */
2463 uart_data->dtx = &uart_data->dtx_base[i];
2464 sig_ker_dtx_timeout_tesd_req();
2465 }
2466 break;
2467
2468 default:
2469 TRACE_ERROR( "SIG_RT_KER_TIMEOUT_TESD_IND unexpected" );
2470 break;
2471 }
2472 } /* sig_rt_ker_timeout_tesd_ind() */
2473