FreeCalypso > hg > fc-tourmaline
diff cdg-hybrid/cdginc/p_uart.h @ 14:35f7a1dc9f7d
cdg-hybrid: import from Magnetite
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Fri, 16 Oct 2020 07:15:38 +0000 |
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| children |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/cdg-hybrid/cdginc/p_uart.h Fri Oct 16 07:15:38 2020 +0000 @@ -0,0 +1,584 @@ +/* ++--------------------------------------------------------------------------+ +| PROJECT : PROTOCOL STACK | +| FILE : p_uart.h | +| SOURCE : "sap\uart.pdf" | +| LastModified : "2002-03-11" | +| IdAndVersion : "8441.117.99.014" | +| SrcFileTime : "Thu Nov 29 09:56:02 2007" | +| Generated by CCDGEN_2.5.5A on Fri Oct 14 21:41:52 2016 | +| !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | ++--------------------------------------------------------------------------+ +*/ + +/* PRAGMAS + * PREFIX : NONE + * COMPATIBILITY_DEFINES : NO (require PREFIX) + * ALWAYS_ENUM_IN_VAL_FILE: NO + * ENABLE_GROUP: NO + * CAPITALIZE_TYPENAME: NO + */ + + +#ifndef P_UART_H +#define P_UART_H + + +#define CDG_ENTER__P_UART_H + +#define CDG_ENTER__FILENAME _P_UART_H +#define CDG_ENTER__P_UART_H__FILE_TYPE CDGINC +#define CDG_ENTER__P_UART_H__LAST_MODIFIED _2002_03_11 +#define CDG_ENTER__P_UART_H__ID_AND_VERSION _8441_117_99_014 + +#define CDG_ENTER__P_UART_H__SRC_FILE_TIME _Thu_Nov_29_09_56_02_2007 + +#include "CDG_ENTER.h" + +#undef CDG_ENTER__P_UART_H + +#undef CDG_ENTER__FILENAME + + +#include "p_uart.val" + +#ifndef __T_comPar__ +#define __T_comPar__ +/* + * Parameters of serial link + * CCDGEN:WriteStruct_Count==3109 + */ +typedef struct +{ + U8 speed; /*< 0: 1> baud rate */ + U8 bpc; /*< 1: 1> bits per character */ + U8 nsb; /*< 2: 1> stop bits */ + U8 parity; /*< 3: 1> parity of serial link */ + U8 flow_rx; /*< 4: 1> flow control mode RX */ + U8 flow_tx; /*< 5: 1> flow control mode TX */ + U8 xon_valid; /*< 6: 1> indicator whether xon is valid */ + U8 xon; /*< 7: 1> XOn character for XON/XOFF flow control */ + U8 xoff_valid; /*< 8: 1> indicator whether xoff is valid */ + U8 xoff; /*< 9: 1> XOff character for XON/XOFF flow control */ + U8 esc_valid; /*< 10: 1> indicator whether esc_char and esc_gp are valid */ + U8 esc_char; /*< 11: 1> escape character */ + U16 esc_gp; /*< 12: 2> guard period */ + U8 _align0; /*< 14: 1> alignment */ + U8 _align1; /*< 15: 1> alignment */ +} T_comPar; +#endif + + +/* + * End of substructure section, begin of primitive definition section + */ + +#ifndef __T_UART_PARAMETERS_REQ__ +#define __T_UART_PARAMETERS_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3110 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ + T_comPar comPar; /*< 4: 16> Parameters of serial link */ +} T_UART_PARAMETERS_REQ; +#endif + +#ifndef __T_UART_PARAMETERS_CNF__ +#define __T_UART_PARAMETERS_CNF__ +/* + * + * CCDGEN:WriteStruct_Count==3111 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_PARAMETERS_CNF; +#endif + +#ifndef __T_UART_PARAMETERS_IND__ +#define __T_UART_PARAMETERS_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3112 + */ +typedef struct +{ + U8 uart_instances; /*< 0: 1> number of UART instances */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_PARAMETERS_IND; +#endif + +#ifndef __T_UART_DTI_REQ__ +#define __T_UART_DTI_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3113 + */ +typedef struct +{ + U8 dti_conn; /*< 0: 1> DTI connect */ + U8 device; /*< 1: 1> device number */ + U8 dlci; /*< 2: 1> data link connection identifier */ + U8 direction; /*< 3: 1> direction of the DTI link */ + U32 link_id; /*< 4: 4> identifier of DTI connection */ + U32 entity_name; /*< 8: 4> communication entity name */ +} T_UART_DTI_REQ; +#endif + +#ifndef __T_UART_DTI_CNF__ +#define __T_UART_DTI_CNF__ +/* + * + * CCDGEN:WriteStruct_Count==3114 + */ +typedef struct +{ + U8 dti_conn; /*< 0: 1> DTI connect */ + U8 device; /*< 1: 1> device number */ + U8 dlci; /*< 2: 1> data link connection identifier */ + U8 _align0; /*< 3: 1> alignment */ +} T_UART_DTI_CNF; +#endif + +#ifndef __T_UART_DTI_IND__ +#define __T_UART_DTI_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3115 + */ +typedef struct +{ + U8 dti_conn; /*< 0: 1> DTI connect */ + U8 device; /*< 1: 1> device number */ + U8 dlci; /*< 2: 1> data link connection identifier */ + U8 _align0; /*< 3: 1> alignment */ +} T_UART_DTI_IND; +#endif + +#ifndef __T_UART_DISABLE_REQ__ +#define __T_UART_DISABLE_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3116 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_DISABLE_REQ; +#endif + +#ifndef __T_UART_DISABLE_CNF__ +#define __T_UART_DISABLE_CNF__ +/* + * + * CCDGEN:WriteStruct_Count==3117 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_DISABLE_CNF; +#endif + +#ifndef __T_UART_RING_REQ__ +#define __T_UART_RING_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3118 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 line_state; /*< 2: 1> state of line */ + U8 _align0; /*< 3: 1> alignment */ +} T_UART_RING_REQ; +#endif + +#ifndef __T_UART_RING_CNF__ +#define __T_UART_RING_CNF__ +/* + * + * CCDGEN:WriteStruct_Count==3119 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 _align0; /*< 2: 1> alignment */ + U8 _align1; /*< 3: 1> alignment */ +} T_UART_RING_CNF; +#endif + +#ifndef __T_UART_DCD_REQ__ +#define __T_UART_DCD_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3120 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 line_state; /*< 2: 1> state of line */ + U8 _align0; /*< 3: 1> alignment */ +} T_UART_DCD_REQ; +#endif + +#ifndef __T_UART_DCD_CNF__ +#define __T_UART_DCD_CNF__ +/* + * + * CCDGEN:WriteStruct_Count==3121 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 _align0; /*< 2: 1> alignment */ + U8 _align1; /*< 3: 1> alignment */ +} T_UART_DCD_CNF; +#endif + +#ifndef __T_UART_ESCAPE_REQ__ +#define __T_UART_ESCAPE_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3122 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 detection; /*< 2: 1> escape sequence detection */ + U8 _align0; /*< 3: 1> alignment */ +} T_UART_ESCAPE_REQ; +#endif + +#ifndef __T_UART_ESCAPE_CNF__ +#define __T_UART_ESCAPE_CNF__ +/* + * + * CCDGEN:WriteStruct_Count==3123 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 _align0; /*< 2: 1> alignment */ + U8 _align1; /*< 3: 1> alignment */ +} T_UART_ESCAPE_CNF; +#endif + +#ifndef __T_UART_DETECTED_IND__ +#define __T_UART_DETECTED_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3124 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 cause; /*< 2: 1> cause of indication */ + U8 _align0; /*< 3: 1> alignment */ +} T_UART_DETECTED_IND; +#endif + +#ifndef __T_UART_ERROR_IND__ +#define __T_UART_ERROR_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3125 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 error; /*< 2: 1> error code */ + U8 _align0; /*< 3: 1> alignment */ +} T_UART_ERROR_IND; +#endif + +#ifndef __T_UART_MUX_START_REQ__ +#define __T_UART_MUX_START_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3126 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 mode; /*< 1: 1> transparency mechanism */ + U8 frame_type; /*< 2: 1> type of frame */ + U8 _align0; /*< 3: 1> alignment */ + U16 n1; /*< 4: 2> maximum frame size */ + U8 t1; /*< 6: 1> acknowledgement timer */ + U8 n2; /*< 7: 1> maximum numer of retransmissions */ + U8 t2; /*< 8: 1> response timer for the multiplexer control channel */ + U8 t3; /*< 9: 1> wake up response timer */ + U8 _align1; /*< 10: 1> alignment */ + U8 _align2; /*< 11: 1> alignment */ +} T_UART_MUX_START_REQ; +#endif + +#ifndef __T_UART_MUX_START_CNF__ +#define __T_UART_MUX_START_CNF__ +/* + * + * CCDGEN:WriteStruct_Count==3127 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_MUX_START_CNF; +#endif + +#ifndef __T_UART_MUX_DLC_ESTABLISH_IND__ +#define __T_UART_MUX_DLC_ESTABLISH_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3128 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 convergence; /*< 2: 1> convergence layer */ + U8 _align0; /*< 3: 1> alignment */ + U16 n1; /*< 4: 2> maximum frame size */ + U8 service; /*< 6: 1> service on DLC */ + U8 _align1; /*< 7: 1> alignment */ +} T_UART_MUX_DLC_ESTABLISH_IND; +#endif + +#ifndef __T_UART_MUX_DLC_ESTABLISH_RES__ +#define __T_UART_MUX_DLC_ESTABLISH_RES__ +/* + * + * CCDGEN:WriteStruct_Count==3129 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U16 n1; /*< 2: 2> maximum frame size */ +} T_UART_MUX_DLC_ESTABLISH_RES; +#endif + +#ifndef __T_UART_MUX_DLC_RELEASE_REQ__ +#define __T_UART_MUX_DLC_RELEASE_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3130 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 _align0; /*< 2: 1> alignment */ + U8 _align1; /*< 3: 1> alignment */ +} T_UART_MUX_DLC_RELEASE_REQ; +#endif + +#ifndef __T_UART_MUX_DLC_RELEASE_IND__ +#define __T_UART_MUX_DLC_RELEASE_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3131 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 dlci; /*< 1: 1> data link connection identifier */ + U8 _align0; /*< 2: 1> alignment */ + U8 _align1; /*< 3: 1> alignment */ +} T_UART_MUX_DLC_RELEASE_IND; +#endif + +#ifndef __T_UART_MUX_SLEEP_REQ__ +#define __T_UART_MUX_SLEEP_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3132 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_MUX_SLEEP_REQ; +#endif + +#ifndef __T_UART_MUX_SLEEP_IND__ +#define __T_UART_MUX_SLEEP_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3133 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_MUX_SLEEP_IND; +#endif + +#ifndef __T_UART_MUX_WAKEUP_REQ__ +#define __T_UART_MUX_WAKEUP_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3134 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_MUX_WAKEUP_REQ; +#endif + +#ifndef __T_UART_MUX_WAKEUP_IND__ +#define __T_UART_MUX_WAKEUP_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3135 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_MUX_WAKEUP_IND; +#endif + +#ifndef __T_UART_MUX_CLOSE_REQ__ +#define __T_UART_MUX_CLOSE_REQ__ +/* + * + * CCDGEN:WriteStruct_Count==3136 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_MUX_CLOSE_REQ; +#endif + +#ifndef __T_UART_MUX_CLOSE_IND__ +#define __T_UART_MUX_CLOSE_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3137 + */ +typedef struct +{ + U8 device; /*< 0: 1> device number */ + U8 _align0; /*< 1: 1> alignment */ + U8 _align1; /*< 2: 1> alignment */ + U8 _align2; /*< 3: 1> alignment */ +} T_UART_MUX_CLOSE_IND; +#endif + +#ifndef __T_UART_DRIVER_SENT_IND__ +#define __T_UART_DRIVER_SENT_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3138 + */ +typedef struct +{ + U32 devId; /*< 0: 4> device ID */ +} T_UART_DRIVER_SENT_IND; +#endif + +#ifndef __T_UART_DRIVER_RECEIVED_IND__ +#define __T_UART_DRIVER_RECEIVED_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3139 + */ +typedef struct +{ + U32 devId; /*< 0: 4> device ID */ +} T_UART_DRIVER_RECEIVED_IND; +#endif + +#ifndef __T_UART_DRIVER_FLUSHED_IND__ +#define __T_UART_DRIVER_FLUSHED_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3140 + */ +typedef struct +{ + U32 devId; /*< 0: 4> device ID */ +} T_UART_DRIVER_FLUSHED_IND; +#endif + +#ifndef __T_UART_DRIVER_CONNECT_IND__ +#define __T_UART_DRIVER_CONNECT_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3141 + */ +typedef struct +{ + U32 devId; /*< 0: 4> device ID */ +} T_UART_DRIVER_CONNECT_IND; +#endif + +#ifndef __T_UART_DRIVER_DISCONNECT_IND__ +#define __T_UART_DRIVER_DISCONNECT_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3142 + */ +typedef struct +{ + U32 devId; /*< 0: 4> device ID */ +} T_UART_DRIVER_DISCONNECT_IND; +#endif + +#ifndef __T_UART_DRIVER_CLEAR_IND__ +#define __T_UART_DRIVER_CLEAR_IND__ +/* + * + * CCDGEN:WriteStruct_Count==3143 + */ +typedef struct +{ + U32 devId; /*< 0: 4> device ID */ +} T_UART_DRIVER_CLEAR_IND; +#endif + + +#include "CDG_LEAVE.h" + + +#endif