FreeCalypso > hg > fc-tourmaline
view cdg-hybrid/cdginc/p_mac.h @ 51:04aaa5622fa7
disable deep sleep when Iota LEDB is on
TI's Iota chip docs say that CLK13M must be running in order for
LEDB to work, and practical experience on Mot C139 which uses
Iota LEDB for its keypad backlight concurs: if Calypso enters
deep sleep while the keypad backlight is turned on, the light
flickers visibly as the chipset goes into and out of deep sleep.
TI's original L1 sleep manager code had logic to disable deep sleep
when LT_Status() returns nonzero, but that function only works
for B-Sample and C-Sample LT, always returns 0 on BOARD 41 - no
check of Iota LEDB status anywhere. Change this code for our
current hardware: disable deep sleep when Iota LEDB has been
turned on through LLS.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Mon, 19 Oct 2020 05:11:29 +0000 |
| parents | 35f7a1dc9f7d |
| children |
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/* +--------------------------------------------------------------------------+ | PROJECT : PROTOCOL STACK | | FILE : p_mac.h | | SOURCE : "sap\mac.pdf" | | LastModified : "2003-02-26" | | IdAndVersion : "8441.111.03.009" | | SrcFileTime : "Thu Nov 29 09:45:32 2007" | | Generated by CCDGEN_2.5.5A on Fri Oct 14 21:41:52 2016 | | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | +--------------------------------------------------------------------------+ */ /* PRAGMAS * PREFIX : NONE * COMPATIBILITY_DEFINES : NO (require PREFIX) * ALWAYS_ENUM_IN_VAL_FILE: NO * ENABLE_GROUP: NO * CAPITALIZE_TYPENAME: NO */ #ifndef P_MAC_H #define P_MAC_H #define CDG_ENTER__P_MAC_H #define CDG_ENTER__FILENAME _P_MAC_H #define CDG_ENTER__P_MAC_H__FILE_TYPE CDGINC #define CDG_ENTER__P_MAC_H__LAST_MODIFIED _2003_02_26 #define CDG_ENTER__P_MAC_H__ID_AND_VERSION _8441_111_03_009 #define CDG_ENTER__P_MAC_H__SRC_FILE_TIME _Thu_Nov_29_09_45_32_2007 #include "CDG_ENTER.h" #undef CDG_ENTER__P_MAC_H #undef CDG_ENTER__FILENAME #include "p_mac.val" #ifndef __T_ul_poll_resp__ #define __T_ul_poll_resp__ /* * Uplink Poll Response * CCDGEN:WriteStruct_Count==1778 */ typedef struct { U16 block_status; /*< 0: 2> Block Status */ U16 tn; /*< 2: 2> Timeslot number */ U16 ul_block[13]; /*< 4: 26> Uplink block */ U8 _align0; /*< 30: 1> alignment */ U8 _align1; /*< 31: 1> alignment */ } T_ul_poll_resp; #endif #ifndef __T_ul_data__ #define __T_ul_data__ /* * Uplink Data * CCDGEN:WriteStruct_Count==1779 */ typedef struct { U16 block_status; /*< 0: 2> Block Status */ U16 ul_block[28]; /*< 2: 56> Uplink block */ U8 _align0; /*< 58: 1> alignment */ U8 _align1; /*< 59: 1> alignment */ } T_ul_data; #endif #ifndef __T_dl_data__ #define __T_dl_data__ /* * Downlink Data * CCDGEN:WriteStruct_Count==1780 */ typedef struct { U16 block_status; /*< 0: 2> Block Status */ U16 tn; /*< 2: 2> Timeslot number */ U16 d_macc; /*< 4: 2> Accumulated Metric */ U16 d_nerr; /*< 6: 2> Number of estimated erorrs */ U16 dl_block[27]; /*< 8: 54> Downlink block */ U8 _align0; /*< 62: 1> alignment */ U8 _align1; /*< 63: 1> alignment */ } T_dl_data; #endif /* * End of substructure section, begin of primitive definition section */ #ifndef __T_MAC_DATA_REQ__ #define __T_MAC_DATA_REQ__ /* * * CCDGEN:WriteStruct_Count==1781 */ typedef struct { T_ul_data ul_data; /*< 0: 60> Uplink Data */ } T_MAC_DATA_REQ; #endif #ifndef __T_MAC_DATA_IND__ #define __T_MAC_DATA_IND__ /* * * CCDGEN:WriteStruct_Count==1782 */ typedef struct { U32 fn; /*< 0: 4> Framenumber */ U16 rx_no; /*< 4: 2> Number of received Timeslots */ U8 _align0; /*< 6: 1> alignment */ U8 _align1; /*< 7: 1> alignment */ T_dl_data dl_data; /*< 8: 64> Downlink Data */ } T_MAC_DATA_IND; #endif #ifndef __T_MAC_READY_IND__ #define __T_MAC_READY_IND__ /* * * CCDGEN:WriteStruct_Count==1783 */ typedef struct { U8 nts; /*< 0: 1> Maximum number of Timeslots for uplink TBF */ U8 _align0; /*< 1: 1> alignment */ U8 _align1; /*< 2: 1> alignment */ U8 _align2; /*< 3: 1> alignment */ U32 fn; /*< 4: 4> Framenumber */ U8 rlc_blocks_sent; /*< 8: 1> number of transmitted rlc/mac blocks (except polling) */ U8 last_poll_resp; /*< 9: 1> Last Poll Response */ U8 ta_value; /*< 10: 1> Timing Advance Value */ U8 _align3; /*< 11: 1> alignment */ } T_MAC_READY_IND; #endif #ifndef __T_MAC_POLL_REQ__ #define __T_MAC_POLL_REQ__ /* * * CCDGEN:WriteStruct_Count==1784 */ typedef struct { T_ul_poll_resp ul_poll_resp; /*< 0: 32> Uplink Poll Response */ } T_MAC_POLL_REQ; #endif #ifndef __T_MAC_PWR_CTRL_IND__ #define __T_MAC_PWR_CTRL_IND__ /* * * CCDGEN:WriteStruct_Count==1785 */ typedef struct { U32 assignment_id; /*< 0: 4> assignment identifier; . */ U8 crc_error; /*< 4: 1> CRC error; . */ U8 bcch_level; /*< 5: 1> Signal level of BCCH serving Cell; . */ U16 radio_freq[MAC_BURST_PER_BLOCK]; /*< 6: 8> Radio frequency of the TDMA frame; . */ U8 burst_level[MAC_BURST_PER_BLOCK]; /*< 14: 4> Signal level of the first valid downlink PDCH; . */ U8 _align0; /*< 18: 1> alignment */ U8 _align1; /*< 19: 1> alignment */ } T_MAC_PWR_CTRL_IND; #endif #include "CDG_LEAVE.h" #endif