FreeCalypso > hg > fc-tourmaline
view cdg-hybrid/cdginc/p_rrlc.val @ 51:04aaa5622fa7
disable deep sleep when Iota LEDB is on
TI's Iota chip docs say that CLK13M must be running in order for
LEDB to work, and practical experience on Mot C139 which uses
Iota LEDB for its keypad backlight concurs: if Calypso enters
deep sleep while the keypad backlight is turned on, the light
flickers visibly as the chipset goes into and out of deep sleep.
TI's original L1 sleep manager code had logic to disable deep sleep
when LT_Status() returns nonzero, but that function only works
for B-Sample and C-Sample LT, always returns 0 on BOARD 41 - no
check of Iota LEDB status anywhere. Change this code for our
current hardware: disable deep sleep when Iota LEDB has been
turned on through LLS.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Mon, 19 Oct 2020 05:11:29 +0000 |
parents | 35f7a1dc9f7d |
children |
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/* +--------------------------------------------------------------------------+ | PROJECT : PROTOCOL STACK | | FILE : p_rrlc.val | | SOURCE : "sap\rrlc.pdf" | | LastModified : "2002-10-11" | | IdAndVersion : "8443.101.02.008" | | SrcFileTime : "Thu Nov 29 09:52:52 2007" | | Generated by CCDGEN_2.5.5A on Fri Oct 14 21:41:52 2016 | | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! | +--------------------------------------------------------------------------+ */ /* PRAGMAS * PREFIX : NONE * COMPATIBILITY_DEFINES : NO (require PREFIX) * ALWAYS_ENUM_IN_VAL_FILE: NO * ENABLE_GROUP: NO * CAPITALIZE_TYPENAME: NO */ #ifndef P_RRLC_VAL #define P_RRLC_VAL #define CDG_ENTER__P_RRLC_VAL #define CDG_ENTER__FILENAME _P_RRLC_VAL #define CDG_ENTER__P_RRLC_VAL__FILE_TYPE CDGINC #define CDG_ENTER__P_RRLC_VAL__LAST_MODIFIED _2002_10_11 #define CDG_ENTER__P_RRLC_VAL__ID_AND_VERSION _8443_101_02_008 #define CDG_ENTER__P_RRLC_VAL__SRC_FILE_TIME _Thu_Nov_29_09_52_52_2007 #include "CDG_ENTER.h" #undef CDG_ENTER__P_RRLC_VAL #undef CDG_ENTER__FILENAME /* * Value constants for VAL_cause */ #define LCS_OK (0x0) /* no error */ #define LCS_WRONG_BTS (0xa) /* Serving Cell BTS differs from Reference BTS */ #define LCS_HANDOVER (0x14) /* handover occured during Position Measurement procedure */ /* * Value constants for VAL_sb_flag */ #define EOTD_INVALID (0x0) /* invalid data */ #define EOTD_VALID (0x1) /* valid data */ /* * Value constants for VAL_eotd_mode */ #define EOTD_IDLE (0x0) /* Idle mode */ #define EOTD_DEDIC (0x1) /* Dedicated or packet mode */ /* * Value constants for VAL_exp_otd */ /* * Value constants for VAL_fn */ #define FNMAX (0x297000) /* max Frame Number + 1 (26*51*2048) */ /* * Value constants for VAL_mfrm_offset */ /* * Value constants for VAL_otd_type */ #define ROUGH_RTD (0x0) /* only rough RTD has been provided by the NW */ #define EXPECTED_OTD (0x1) /* only expectedOTD has been provided by the NW */ #define BOTH_OTD (0x2) /* Both OTD / RTD types have been provided by the NW */ /* * Value constants for VAL_rough_rtd */ /* * Value constants for VAL_tav */ #define TA_NOT_AVAIL (0xff) /* no Timing Advance in Idle Mode */ /* * Value constants for VAL_uncertainty */ #define UNC_MAX_2BIT (0x0) /* uncertainty in bits. 0 - 2 bits */ #define UNC_MAX_4BIT (0x1) /* uncertainty in bits. 3 - 4 bits */ #define UNC_MAX_8BIT (0x2) /* uncertainty in bits. 5 - 8 bits */ #define UNC_MAX_12BIT (0x3) /* uncertainty in bits. 9 - 12 bits */ #define UNC_MAX_16BIT (0x4) /* uncertainty in bits. 13 - 16 bits */ #define UNC_MAX_22BIT (0x5) /* uncertainty in bits. 17 - 22 bits */ #define UNC_MAX_30BIT (0x6) /* uncertainty in bits. 23 - 30 bits */ #define UNC_GT_30BIT (0x7) /* uncertainty in bits. > 30 bits */ /* * user defined constants */ #define MAX_NCELL_EOTD_L1 (0xc) #define MAX_NCELL_EOTD (0xf) #define MAX_NCELL_EOTD_SI (0x20) #define XCOR_NO (0x12) #include "CDG_LEAVE.h" #endif