FreeCalypso > hg > fc-tourmaline
view src/cs/layer1/cfile/l1_small_asm.S @ 287:3dee79757ae4
UI fw: load handheld audio mode on boot
We have now reached the point where use of audio mode config files
should be considered mandatory. In ACI usage we can tell users that
they need to perform an AT@AUL of some appropriate audio mode, but
in UI-enabled fw we really need to have the firmware load audio modes
on its own, so that correct audio config gets established when the
handset or development board runs on its own, without a connected host
computer.
Once have FC Venus with both main and headset audio channels and
headset plug insertion detection, our fw will need to automatically
load the handheld mode or the headset mode depending on the plug
insertion state. For now we load only the handheld mode, which has
been tuned for FC-HDS4 on FC Luna.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sat, 13 Nov 2021 03:20:57 +0000 |
| parents | 4e78acac3d88 |
| children |
line wrap: on
line source
/* * Assembly code extracted out of TI's l1_small.c * * This code is correct ONLY for CHIPSET 10 or 11 as currently used * by FreeCalypso; see TI's original code for what changes would be * needed to support other CHIPSETs. */ .text .code 32 /*-------------------------------------------------------*/ /* _GSM_Small_Sleep */ /* (formerly INT_Small_Sleep) */ /*-------------------------------------------------------*/ /* */ /* Description: small sleep */ /* ------------ */ /* Called by TCT_Schedule main loop of Nucleus */ /*-------------------------------------------------------*/ #define SMALL_SLEEP 0x01 #define ALL_SLEEP 0x04 #define BIG_SMALL_SLEEP 0x05 #define PWR_MNGT 0x01 .globl _GSM_Small_Sleep _GSM_Small_Sleep: ldr r0,Switch ldr r0,[r0] ldrb r1,[r0] cmp r1,#PWR_MNGT bne TCT_Schedule_Loop ldr r0,Mode ldr r0,[r0] ldrb r1,[r0] cmp r1,#SMALL_SLEEP beq Small_sleep_ok cmp r1,#ALL_SLEEP beq Small_sleep_ok cmp r1,#BIG_SMALL_SLEEP bne TCT_Schedule_Loop Small_sleep_ok: // ***************************************************** //reset the DEEP_SLEEP bit 12 of CNTL_ARM_CLK register // (Cf BUG_1278) ldr r0,addrCLKM @ pick up CNTL_ARM_CLK register address ldrh r1,[r0] @ take the current value of the register orr r1,r1,#0x1000 @ reset the bit strh r1,[r0] @ store the result ldr r0,addrCLKM @ pick up CLKM clock register address ldrh r1,[r0] @ take the current value of the register bic r1,r1,#1 @ disable ARM clock strh r1,[r0] B TCT_Schedule_Loop @ Return to TCT_Schedule main loop addrCLKM: .word 0xfffffd00 @ CLKM clock register address Mode: .word mode_authorized Switch: .word switch_PWR_MNGT