FreeCalypso > hg > fc-tourmaline

view src/cs/drivers/drv_app/fchg/fchg_struct.h @ 223:740a8e8fc9d7

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
startup sync logic rework for the new PWON button boot scheme Previously we added logic to the MMI task to hold off PEI init until R2D is running, and then extended that condition to wait for FCHG init too. However, the dependencies of MMI upon R2D and FCHG don't start until mmiInit(), and that call is driven by Switch_ON() code, hence the wait for R2D and FCHG init can be made in that code path instead of the MMI task. Furthermore, with our new way of signaling PWON button boot to MMI, we need a new wait to ensure that the MMI task is up - previously this assurance was provided by the wait for Kp pointers to be set. Solution: revert our previous PEI init hold-off additions to MMI, add a new flag indicating MMI task init done, and put the combined wait for all needed conditions into our new PWON button boot code in power.c.
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 27 Apr 2021 06:24:52 +0000
parents 75067af48bfd
children 769cf6273fe4
line wrap: on
line source

/*
 * Internal structure definitions for the FCHG SWE reside here.
 * abb_inth.c will also need to include this header in order to
 * get our T_PWR_CTRL_BLOCK definition.
 */

#ifndef __FCHG_STRUCT_H
#define __FCHG_STRUCT_H

#include "rv/rv_general.h"
#include "rvf/rvf_api.h"
#include "fchg/fchg_common.h"

struct charging_config {
	UINT16	start_delay;
	UINT16	start_thresh;
	UINT16	restart_thresh;
	UINT16	ci2cv_thresh;
	UINT16	cv_init_set;
	UINT16	cv_ctrl_loop_high;
	UINT16	cv_ctrl_loop_low;
	UINT16	cv_dac_max_incr;
	UINT16	cv_dac_max_decr;
	UINT16	cv_samples_needed;
	UINT16	overvoltage;
	UINT16	ci_current;
	UINT16	end_current;
	UINT16	ichg_max_spike;
	UINT16	ichg_samples_needed;
	UINT16	charge_time_limit;
	UINT16	recharge_delay;
	UINT16	bciconf;
};

/* from original PWR SWE */
typedef struct {
	UINT16		bat_voltage;
	T_PWR_PERCENT	remain_capa;
} T_PWR_THRESHOLDS;

#define	MIN_PERCENT_THRESH	5
#define	MAX_PERCENT_THRESH	21	/* allowing 5% steps */
#define	NB_BARS_THRESH		4

struct battery_config {
	UINT8			bars_thresh[NB_BARS_THRESH];
	T_PWR_THRESHOLDS	percent_thresh[MAX_PERCENT_THRESH];
};

#define	ICHG_AVG_WINDOW	6

typedef struct {
	/* RiViera boilerplate */
	T_RVF_ADDR_ID		addr_id;
	T_RVF_MB_ID		prim_id;
	/* interface to upper layers */
	T_FCHG_EVENT_HANDLER	event_handler;
	/* configuration */
	struct charging_config	config;
	BOOL			config_present;
	struct battery_config	batt;
	UINT16			nb_percent_thresh;
	/* state */
	enum fchg_state		state;
	UINT16			batt_mv;
	UINT16			curr_disch_thresh;
	/* valid only during a charging cycle */
	UINT16			i2v_offset;
	UINT16			ci_ichg;
	UINT16			cv_dac_init;
	UINT16			cv_dac_curr;
	UINT16			cv_high_vbat_count;
	UINT16			cv_low_vbat_count;
	UINT16			ichg_avg_buf[ICHG_AVG_WINDOW];
	UINT16			ichg_fill_level;
	UINT16			ichg_ring_ptr;
	UINT16			ichg_average;
	UINT16			ichg_low_count;
	UINT32			start_time;
} T_PWR_CTRL_BLOCK;

#endif	/* include guard */