view src/cs/system/template/gsm_ds_motc139.template @ 275:79cfefc1e2b4

audio mode load: gracefully handle mode files of wrong AEC version Unfortunately our change of enabling L1_NEW_AEC (which is necessary in order to bring our Calypso ARM fw into match with the underlying DSP reality) brings along a change in the audio mode file binary format and file size - all those new tunable AEC parameters do need to be stored somewhere, after all. But we already have existing mode files in the old format, and setting AEC config to garbage when loading old audio modes (which is what would happen without the present change) is not an appealing proposition. The solution implemented in the present change is as follows: the audio mode loading code checks the file size, and if it differs from the active version of T_AUDIO_MODE, the T_AUDIO_AEC_CFG structure is cleared - set to the default (disabled AEC) for the compiled type of AEC. We got lucky in that this varying T_AUDIO_AEC_CFG structure sits at the end of T_AUDIO_MODE!
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 30 Jul 2021 02:55:48 +0000
parents 06a52f3fcec9
children
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/*
 * Integrated Protocol Stack Linker command file (all components)
 *
 * Target : ARM
 *
 * Copyright (c) Texas Instruments 2002, Condat 2002
 *
 * This version of the linker script template has been concocted
 * by Spacefalcon the Outlaw, based on gsm_ds_amd8_lj3.template,
 * in order to build the GSM firmware for the memory configuration
 * found in the Motorola C139.
 */

-c /* Autoinitialize variables at runtime */

/*********************************/
/* SPECIFY THE SYSTEM MEMORY MAP */
/*********************************/

MEMORY
{
  /* CS0: Flash 4 Mbytes ****************************************************/
  /* Interrupt Vectors Table */
  I_MEM   (RXI) : org = 0x00000000   len = 0x00000100

  /* Boot Sector */
  B_MEM   (RXI) : org = 0x00000100   len = 0x00001f00

  /* Magic Word for Calypso Boot ROM */
  MWC_MEM (RXI)  : org = 0x00002000   len = 0x00000004  fill = 0x0000001

  /* Program Memory */
  P_MEM1  (RXI) : org = 0x00010000   len = 0x00000700
  P_MEM2  (RXI) : org = 0x00010700   len = 0x00000004
  P_MEM3  (RXI) : org = 0x00010704   len = 0x002ef8fc

  /* FFS Area */
  FFS_MEM (RX)  : org = 0x00300000   len = 0x00070000
  /**************************************************************************/

  /* CS1: External SRAM 1 Mbytes ********************************************/
  /* Data Memory */

  /*
   *** HACK by Spacefalcon the Outlaw ***
   *
   * The starting Leonardo version (gsm_ds_amd8_lj3.template) had two
   * external SRAM regions: D_MEM1 and D_MEM2.  When I tried removing
   * D_MEM2 and keeping only D_MEM1, the linker started behaving oddly
   * in that the sections were emitted in the wrong order, and the
   * addresses printed in the map file were bogus.  The resulting m0
   * images seemed to still work correctly, but I feel that having the
   * linker act "correctly" is better.
   *
   * My current hack-solution is to split the 1 MiB physical XRAM
   * into D_MEM1 and D_MEM2 of 512 KiB each.  As it happens, the total
   * XRAM usage of the current firmware is a little below 512 KiB anyway.
   *
   * Update for C139: we only have 512 KiB in total now, but we can still
   * split the last 4 KiB off into D_MEM2.
   */

  D_MEM1  (RW)  : org = 0x01000000   len = 0x0007F000
  D_MEM2  (RW)  : org = 0x0107F000   len = 0x00001000
  /**************************************************************************/

  /* CS6: Calypso Internal SRAM 256 kbytes **********************************/
  /* Code & Variables Memory */
  S_MEM   (RXW) : org = 0x00800000   len = 0x00040000
  /**************************************************************************/
}

/***********************************************/
/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
/***********************************************/

/*
 * Since the bootloader directly calls the INT_Initialize() routine located
 * in int.s, this int.s code must always be mapped at the same address
 * (usually in the second flash sector). Its length is about 0x500 bytes.
 * Then comes the code that need to be loaded into the internal RAM.
 */

SECTIONS
{
    .intvecs : {} > I_MEM      /* Interrupt Vectors Table */
    .monitor : > B_MEM         /* Monitor Constants & Code */
    {
        $(CONST_BOOT_LIB)
    }

    .inttext : {} > P_MEM1     /* int.s Code */

    .bss_dar : > D_MEM1        /* DAR SWE Variables */
    {
        $(BSS_DAR_LIB)
    }

    /*
     * The .bss section should not be split to ensure it is initialized to 0
     * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
     * or in D_MEM2.
     *
     * Falcon's note for K5A3281: see the comments above where the memory
     * regions are defined.
     */

    .bss     : > D_MEM1 | D_MEM2        /* Global & Static Variables */
    {
        $(BSS_BOOT_LIB)
    }

    /*
     * All .bss sections, which must be mapped in internal RAM must be
     * grouped in order to initialized the corresponding memory to 0.
     * This initialization is done in int.s file before calling the Nucleus
     * routine.
     */

    GROUP
    {
      S_D_Mem /* Label of start address of .bss section in Int. RAM */
      .DintMem
      {

        /*
         * .bss sections of the application
         */

        $(BSS_LIBS)

      }

      API_HISR_stack : {}
 
      E_D_Mem /* Label of end address of .bss section in Int. RAM */
    } > S_MEM

    /*
     * .text and .const sections which must be mapped in internal RAM.
     */

    .ldfl    : {} > P_MEM2 /* Used to know the start load address */
    GROUP load = P_MEM3, run = S_MEM
    {
      S_P_Mem  /* Label of start address of .text & .const sections in Int. RAM */
      .PIntMem
      {
        /*
         * .text and .const sections of the application.
         *
         * The .veneer sections correspond exactly to .text:v&n sections
         * implementing the veneer functions. The .text:v$n -> .veneer
         * translation is performed by PTOOL software when PTOOL_OPTIONS
         * environement variable is set to veneer_section.
         */

        $(CONST_LIBS)

      }
      E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
    }

    /*
     * The rest of the code is mapped in flash, however the trampolines
     * load address should be consistent with .text.
     */
    COMMENT2START      
    `trampolines load = P_MEM3, run = S_MEM
    COMMENT2END

    .text    : {} > P_MEM3            /* Code */

    /*
     * The rest of the constants is mapped in flash.
     * The .cinit section should not be split.
     */

    .cinit   : {} >  P_MEM3           /* Initialization Tables */
    .const   : {} >  P_MEM3           /* Constant Data */
    KadaAPI  : {} >  P_MEM3           /* ROMized CLDC */

    .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */

    .stackandheap : > D_MEM1   /* System Stacks, etc... */
    {
      /* Leave 20 32bit words for register pushes. */
      . = align(8);
      . += 20 * 4;

      /* Stack for abort and/or undefined modes. */
      exception_stack = .;

      /* Leave 38 32bit words for state saving on exceptions. */
      _xdump_buffer = .;
      . += 38 * 4;
      . = align(8);

      /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
      stack_segment = .;
      . += 0xB00;
    }

    .data    : {} > D_MEM1     /* Initialized Data */
    .sysmem  : {} > D_MEM1     /* Dynamic Memory Allocation Area */

}