FreeCalypso > hg > fc-tourmaline
view src/cs/layer1/cfile/l1_small_asm.S @ 75:8697f358f505
backlight rework: Condat light driver accepts levels
The present change is another intermediate step on the path toward
new FreeCalypso backlight handling. At this intermediate step the
Condat light driver accepts 0-255 backlight levels driven by MFW,
and puts them out on PWL on Luna development boards. At the same
time on C139 it is now possible to turn on the display backlight
with or without the keypad bl - the lsb of the 0-255 backlight level
controls the keypad bl.
MFW presently drives only 0 and 255 backlight levels, thus there is
no visible behavioral change yet - but the plan for subsequent stages
of this backlight rework is to add a dimmed backlight state
(no keypad bl on C139) during active calls.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sat, 24 Oct 2020 20:44:04 +0000 |
| parents | 4e78acac3d88 |
| children |
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/* * Assembly code extracted out of TI's l1_small.c * * This code is correct ONLY for CHIPSET 10 or 11 as currently used * by FreeCalypso; see TI's original code for what changes would be * needed to support other CHIPSETs. */ .text .code 32 /*-------------------------------------------------------*/ /* _GSM_Small_Sleep */ /* (formerly INT_Small_Sleep) */ /*-------------------------------------------------------*/ /* */ /* Description: small sleep */ /* ------------ */ /* Called by TCT_Schedule main loop of Nucleus */ /*-------------------------------------------------------*/ #define SMALL_SLEEP 0x01 #define ALL_SLEEP 0x04 #define BIG_SMALL_SLEEP 0x05 #define PWR_MNGT 0x01 .globl _GSM_Small_Sleep _GSM_Small_Sleep: ldr r0,Switch ldr r0,[r0] ldrb r1,[r0] cmp r1,#PWR_MNGT bne TCT_Schedule_Loop ldr r0,Mode ldr r0,[r0] ldrb r1,[r0] cmp r1,#SMALL_SLEEP beq Small_sleep_ok cmp r1,#ALL_SLEEP beq Small_sleep_ok cmp r1,#BIG_SMALL_SLEEP bne TCT_Schedule_Loop Small_sleep_ok: // ***************************************************** //reset the DEEP_SLEEP bit 12 of CNTL_ARM_CLK register // (Cf BUG_1278) ldr r0,addrCLKM @ pick up CNTL_ARM_CLK register address ldrh r1,[r0] @ take the current value of the register orr r1,r1,#0x1000 @ reset the bit strh r1,[r0] @ store the result ldr r0,addrCLKM @ pick up CLKM clock register address ldrh r1,[r0] @ take the current value of the register bic r1,r1,#1 @ disable ARM clock strh r1,[r0] B TCT_Schedule_Loop @ Return to TCT_Schedule main loop addrCLKM: .word 0xfffffd00 @ CLKM clock register address Mode: .word mode_authorized Switch: .word switch_PWR_MNGT