FreeCalypso > hg > fc-tourmaline
view src/cs/drivers/drv_app/fchg/fchg_struct.h @ 268:f2e52cab0a73
abb_inth.c: check all interrupt causes, not just one
The original code used if - else if - else if etc constructs, thus
the first detected interrupt was the only one handled. However,
Iota ITSTATREG is a clear-on-read register, thus if we only handle
the first detected interrupt and skip checking the others, then the
other interrupts will be lost, if more than one interrupt happened
to occur in one ABB interrupt handling cycle - a form of rare race
condition. Change the code to check all interrupts that were read
in this cycle.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Sun, 13 Jun 2021 18:17:53 +0000 |
parents | 769cf6273fe4 |
children |
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/* * Internal structure definitions for the FCHG SWE reside here. * abb_inth.c will also need to include this header in order to * get our T_PWR_CTRL_BLOCK definition. */ #ifndef __FCHG_STRUCT_H #define __FCHG_STRUCT_H #include "rv/rv_general.h" #include "rvf/rvf_api.h" #include "fchg/fchg_common.h" struct charging_config { UINT16 start_delay; UINT16 start_thresh; UINT16 restart_thresh; UINT16 ci2cv_thresh; UINT16 cv_init_set; UINT16 cv_ctrl_loop_high; UINT16 cv_ctrl_loop_low; UINT16 cv_dac_max_incr; UINT16 cv_dac_max_decr; UINT16 cv_samples_needed; UINT16 overvoltage; UINT16 ci_current; UINT16 end_current; UINT16 ichg_max_spike; UINT16 ichg_samples_needed; UINT16 charge_time_limit; UINT16 recharge_delay; UINT16 bciconf; }; /* from original PWR SWE */ typedef struct { UINT16 bat_voltage; T_PWR_PERCENT remain_capa; } T_PWR_THRESHOLDS; #define MIN_PERCENT_THRESH 5 #define MAX_PERCENT_THRESH 21 /* allowing 5% steps */ #define NB_BARS_THRESH 4 struct battery_config { UINT8 bars_thresh[NB_BARS_THRESH]; T_PWR_THRESHOLDS percent_thresh[MAX_PERCENT_THRESH]; }; struct bsim_config { UINT8 init_percent; UINT8 start_enable; UINT8 pad[2]; }; #define ICHG_AVG_WINDOW 6 typedef struct { /* RiViera boilerplate */ T_RVF_ADDR_ID addr_id; T_RVF_MB_ID prim_id; /* interface to upper layers */ T_FCHG_EVENT_HANDLER event_handler; /* configuration */ struct charging_config config; BOOL config_present; struct battery_config batt; UINT16 nb_percent_thresh; struct bsim_config bsim; BOOL bsim_mode; /* state */ enum fchg_state state; UINT16 batt_mv; UINT16 curr_disch_thresh; /* valid only during a charging cycle */ UINT16 i2v_offset; UINT16 ci_ichg; UINT16 cv_dac_init; UINT16 cv_dac_curr; UINT16 cv_high_vbat_count; UINT16 cv_low_vbat_count; UINT16 ichg_avg_buf[ICHG_AVG_WINDOW]; UINT16 ichg_fill_level; UINT16 ichg_ring_ptr; UINT16 ichg_average; UINT16 ichg_low_count; UINT32 start_time; } T_PWR_CTRL_BLOCK; #endif /* include guard */