FreeCalypso > hg > fc-tourmaline
view src/cs/drivers/drv_app/lcc/lcc_tm_i.h @ 268:f2e52cab0a73
abb_inth.c: check all interrupt causes, not just one
The original code used if - else if - else if etc constructs, thus
the first detected interrupt was the only one handled. However,
Iota ITSTATREG is a clear-on-read register, thus if we only handle
the first detected interrupt and skip checking the others, then the
other interrupts will be lost, if more than one interrupt happened
to occur in one ABB interrupt handling cycle - a form of rare race
condition. Change the code to check all interrupts that were read
in this cycle.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sun, 13 Jun 2021 18:17:53 +0000 |
| parents | 4e78acac3d88 |
| children |
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/****************************************************************************** * Power Task (pwr) * Design and coding by Svend Kristian Lindholm, skl@ti.com * * PWR ETM interface * * $Id: pwr_tm_i.h 1.1 Wed, 20 Aug 2003 10:22:37 +0200 skl $ * ******************************************************************************/ #ifndef _LCC_TM_I_H_ #define _LCC_TM_I_H_ #define PWR_CFG_ID_SIZE 2 #define PWR_COMMON_CFG_SIZE 14 #define PWR_BAT_CFG_SIZE 36 #define PWR_TEMP_CFG_SIZE 72 #define PWR_MMI_CFG_SIZE 2 #define PWR_CHG_CFG_SIZE 8 #define PWR_I2V_CAL_SIZE 6 #define PWR_VBAT_CAL_SIZE 6 #define PWR_DYNAMIC_SIZE 1 #define PWR_TMASK_SIZE 4 // This enumeration should be shared with the PC test mode side enum { PWR_CFG_ID = 0, PWR_COMMON, PWR_CHG, PWR_BAT, PWR_TEMP, PWR_MMI, PWR_I2V_CAL = 10, PWR_VBAT_CAL, PWR_MMI_TEST = 15, PWR_DYNAMIC = 20, PWR_TRACE_MASK= 21 } ; // Test mode indication mail sent to ETM // NOTE: Also used as request mail struct etm_tm_ind_s { T_RV_HDR header; uint8 size; uint8 status; uint8 data[127]; }; typedef struct etm_tm_ind_s T_ETM_TM_IND; // Use same buffer in both directions #endif //_LCC_TM_I_H_